From: Greg Kroah-Hartman Date: Sat, 13 Sep 2014 00:50:59 +0000 (-0700) Subject: 3.10-stable patches X-Git-Tag: v3.10.55~26 X-Git-Url: http://git.ipfire.org/?a=commitdiff_plain;h=9662ee9aced39efa116cd887cb014f822e103878;p=thirdparty%2Fkernel%2Fstable-queue.git 3.10-stable patches added patches: mips-asm-reg.h-make-32-and-64-bit-definitions-available-at-the-same-time.patch mips-asm-thread_info-add-_tif_seccomp-flag.patch mips-cleanup-flags-in-syscall-flags-handlers.patch mips-fix-accessing-to-per-cpu-data-when-flushing-the-cache.patch mips-gic-prevent-array-overrun.patch mips-octeon-make-get_system_type-thread-safe.patch mips-prevent-user-from-setting-fcsr-cause-bits.patch mips-remove-bug_on-is_fpu_owner-in-do_ade.patch mips-tlbex-fix-a-missing-statement-for-hugetlb.patch openrisc-rework-signal-handling.patch --- diff --git a/queue-3.10/mips-asm-reg.h-make-32-and-64-bit-definitions-available-at-the-same-time.patch b/queue-3.10/mips-asm-reg.h-make-32-and-64-bit-definitions-available-at-the-same-time.patch new file mode 100644 index 00000000000..964c7f69fdd --- /dev/null +++ b/queue-3.10/mips-asm-reg.h-make-32-and-64-bit-definitions-available-at-the-same-time.patch @@ -0,0 +1,363 @@ +From bcec7c8da6b092b1ff3327fd83c2193adb12f684 Mon Sep 17 00:00:00 2001 +From: Alex Smith +Date: Wed, 23 Jul 2014 14:40:08 +0100 +Subject: MIPS: asm/reg.h: Make 32- and 64-bit definitions available at the same time + +From: Alex Smith + +commit bcec7c8da6b092b1ff3327fd83c2193adb12f684 upstream. + +Get rid of the WANT_COMPAT_REG_H test and instead define both the 32- +and 64-bit register offset definitions at the same time with +MIPS{32,64}_ prefixes, then define the existing EF_* names to the +correct definitions for the kernel's bitness. + +This patch is a prerequisite of the following bug fix patch. + +Signed-off-by: Alex Smith +Cc: linux-mips@linux-mips.org +Patchwork: https://patchwork.linux-mips.org/patch/7451/ +Signed-off-by: Ralf Baechle +Signed-off-by: Greg Kroah-Hartman + +--- + arch/mips/include/asm/reg.h | 256 +++++++++++++++++++++++++-------------- + arch/mips/kernel/binfmt_elfo32.c | 32 +--- + 2 files changed, 180 insertions(+), 108 deletions(-) + +--- a/arch/mips/include/asm/reg.h ++++ b/arch/mips/include/asm/reg.h +@@ -12,116 +12,194 @@ + #ifndef __ASM_MIPS_REG_H + #define __ASM_MIPS_REG_H + +- +-#if defined(CONFIG_32BIT) || defined(WANT_COMPAT_REG_H) +- +-#define EF_R0 6 +-#define EF_R1 7 +-#define EF_R2 8 +-#define EF_R3 9 +-#define EF_R4 10 +-#define EF_R5 11 +-#define EF_R6 12 +-#define EF_R7 13 +-#define EF_R8 14 +-#define EF_R9 15 +-#define EF_R10 16 +-#define EF_R11 17 +-#define EF_R12 18 +-#define EF_R13 19 +-#define EF_R14 20 +-#define EF_R15 21 +-#define EF_R16 22 +-#define EF_R17 23 +-#define EF_R18 24 +-#define EF_R19 25 +-#define EF_R20 26 +-#define EF_R21 27 +-#define EF_R22 28 +-#define EF_R23 29 +-#define EF_R24 30 +-#define EF_R25 31 ++#define MIPS32_EF_R0 6 ++#define MIPS32_EF_R1 7 ++#define MIPS32_EF_R2 8 ++#define MIPS32_EF_R3 9 ++#define MIPS32_EF_R4 10 ++#define MIPS32_EF_R5 11 ++#define MIPS32_EF_R6 12 ++#define MIPS32_EF_R7 13 ++#define MIPS32_EF_R8 14 ++#define MIPS32_EF_R9 15 ++#define MIPS32_EF_R10 16 ++#define MIPS32_EF_R11 17 ++#define MIPS32_EF_R12 18 ++#define MIPS32_EF_R13 19 ++#define MIPS32_EF_R14 20 ++#define MIPS32_EF_R15 21 ++#define MIPS32_EF_R16 22 ++#define MIPS32_EF_R17 23 ++#define MIPS32_EF_R18 24 ++#define MIPS32_EF_R19 25 ++#define MIPS32_EF_R20 26 ++#define MIPS32_EF_R21 27 ++#define MIPS32_EF_R22 28 ++#define MIPS32_EF_R23 29 ++#define MIPS32_EF_R24 30 ++#define MIPS32_EF_R25 31 + + /* + * k0/k1 unsaved + */ +-#define EF_R26 32 +-#define EF_R27 33 ++#define MIPS32_EF_R26 32 ++#define MIPS32_EF_R27 33 + +-#define EF_R28 34 +-#define EF_R29 35 +-#define EF_R30 36 +-#define EF_R31 37 ++#define MIPS32_EF_R28 34 ++#define MIPS32_EF_R29 35 ++#define MIPS32_EF_R30 36 ++#define MIPS32_EF_R31 37 + + /* + * Saved special registers + */ +-#define EF_LO 38 +-#define EF_HI 39 ++#define MIPS32_EF_LO 38 ++#define MIPS32_EF_HI 39 + +-#define EF_CP0_EPC 40 +-#define EF_CP0_BADVADDR 41 +-#define EF_CP0_STATUS 42 +-#define EF_CP0_CAUSE 43 +-#define EF_UNUSED0 44 +- +-#define EF_SIZE 180 +- +-#endif +- +-#if defined(CONFIG_64BIT) && !defined(WANT_COMPAT_REG_H) +- +-#define EF_R0 0 +-#define EF_R1 1 +-#define EF_R2 2 +-#define EF_R3 3 +-#define EF_R4 4 +-#define EF_R5 5 +-#define EF_R6 6 +-#define EF_R7 7 +-#define EF_R8 8 +-#define EF_R9 9 +-#define EF_R10 10 +-#define EF_R11 11 +-#define EF_R12 12 +-#define EF_R13 13 +-#define EF_R14 14 +-#define EF_R15 15 +-#define EF_R16 16 +-#define EF_R17 17 +-#define EF_R18 18 +-#define EF_R19 19 +-#define EF_R20 20 +-#define EF_R21 21 +-#define EF_R22 22 +-#define EF_R23 23 +-#define EF_R24 24 +-#define EF_R25 25 ++#define MIPS32_EF_CP0_EPC 40 ++#define MIPS32_EF_CP0_BADVADDR 41 ++#define MIPS32_EF_CP0_STATUS 42 ++#define MIPS32_EF_CP0_CAUSE 43 ++#define MIPS32_EF_UNUSED0 44 ++ ++#define MIPS32_EF_SIZE 180 ++ ++#define MIPS64_EF_R0 0 ++#define MIPS64_EF_R1 1 ++#define MIPS64_EF_R2 2 ++#define MIPS64_EF_R3 3 ++#define MIPS64_EF_R4 4 ++#define MIPS64_EF_R5 5 ++#define MIPS64_EF_R6 6 ++#define MIPS64_EF_R7 7 ++#define MIPS64_EF_R8 8 ++#define MIPS64_EF_R9 9 ++#define MIPS64_EF_R10 10 ++#define MIPS64_EF_R11 11 ++#define MIPS64_EF_R12 12 ++#define MIPS64_EF_R13 13 ++#define MIPS64_EF_R14 14 ++#define MIPS64_EF_R15 15 ++#define MIPS64_EF_R16 16 ++#define MIPS64_EF_R17 17 ++#define MIPS64_EF_R18 18 ++#define MIPS64_EF_R19 19 ++#define MIPS64_EF_R20 20 ++#define MIPS64_EF_R21 21 ++#define MIPS64_EF_R22 22 ++#define MIPS64_EF_R23 23 ++#define MIPS64_EF_R24 24 ++#define MIPS64_EF_R25 25 + + /* + * k0/k1 unsaved + */ +-#define EF_R26 26 +-#define EF_R27 27 ++#define MIPS64_EF_R26 26 ++#define MIPS64_EF_R27 27 + + +-#define EF_R28 28 +-#define EF_R29 29 +-#define EF_R30 30 +-#define EF_R31 31 ++#define MIPS64_EF_R28 28 ++#define MIPS64_EF_R29 29 ++#define MIPS64_EF_R30 30 ++#define MIPS64_EF_R31 31 + + /* + * Saved special registers + */ +-#define EF_LO 32 +-#define EF_HI 33 +- +-#define EF_CP0_EPC 34 +-#define EF_CP0_BADVADDR 35 +-#define EF_CP0_STATUS 36 +-#define EF_CP0_CAUSE 37 ++#define MIPS64_EF_LO 32 ++#define MIPS64_EF_HI 33 + +-#define EF_SIZE 304 /* size in bytes */ ++#define MIPS64_EF_CP0_EPC 34 ++#define MIPS64_EF_CP0_BADVADDR 35 ++#define MIPS64_EF_CP0_STATUS 36 ++#define MIPS64_EF_CP0_CAUSE 37 ++ ++#define MIPS64_EF_SIZE 304 /* size in bytes */ ++ ++#if defined(CONFIG_32BIT) ++ ++#define EF_R0 MIPS32_EF_R0 ++#define EF_R1 MIPS32_EF_R1 ++#define EF_R2 MIPS32_EF_R2 ++#define EF_R3 MIPS32_EF_R3 ++#define EF_R4 MIPS32_EF_R4 ++#define EF_R5 MIPS32_EF_R5 ++#define EF_R6 MIPS32_EF_R6 ++#define EF_R7 MIPS32_EF_R7 ++#define EF_R8 MIPS32_EF_R8 ++#define EF_R9 MIPS32_EF_R9 ++#define EF_R10 MIPS32_EF_R10 ++#define EF_R11 MIPS32_EF_R11 ++#define EF_R12 MIPS32_EF_R12 ++#define EF_R13 MIPS32_EF_R13 ++#define EF_R14 MIPS32_EF_R14 ++#define EF_R15 MIPS32_EF_R15 ++#define EF_R16 MIPS32_EF_R16 ++#define EF_R17 MIPS32_EF_R17 ++#define EF_R18 MIPS32_EF_R18 ++#define EF_R19 MIPS32_EF_R19 ++#define EF_R20 MIPS32_EF_R20 ++#define EF_R21 MIPS32_EF_R21 ++#define EF_R22 MIPS32_EF_R22 ++#define EF_R23 MIPS32_EF_R23 ++#define EF_R24 MIPS32_EF_R24 ++#define EF_R25 MIPS32_EF_R25 ++#define EF_R26 MIPS32_EF_R26 ++#define EF_R27 MIPS32_EF_R27 ++#define EF_R28 MIPS32_EF_R28 ++#define EF_R29 MIPS32_EF_R29 ++#define EF_R30 MIPS32_EF_R30 ++#define EF_R31 MIPS32_EF_R31 ++#define EF_LO MIPS32_EF_LO ++#define EF_HI MIPS32_EF_HI ++#define EF_CP0_EPC MIPS32_EF_CP0_EPC ++#define EF_CP0_BADVADDR MIPS32_EF_CP0_BADVADDR ++#define EF_CP0_STATUS MIPS32_EF_CP0_STATUS ++#define EF_CP0_CAUSE MIPS32_EF_CP0_CAUSE ++#define EF_UNUSED0 MIPS32_EF_UNUSED0 ++#define EF_SIZE MIPS32_EF_SIZE ++ ++#elif defined(CONFIG_64BIT) ++ ++#define EF_R0 MIPS64_EF_R0 ++#define EF_R1 MIPS64_EF_R1 ++#define EF_R2 MIPS64_EF_R2 ++#define EF_R3 MIPS64_EF_R3 ++#define EF_R4 MIPS64_EF_R4 ++#define EF_R5 MIPS64_EF_R5 ++#define EF_R6 MIPS64_EF_R6 ++#define EF_R7 MIPS64_EF_R7 ++#define EF_R8 MIPS64_EF_R8 ++#define EF_R9 MIPS64_EF_R9 ++#define EF_R10 MIPS64_EF_R10 ++#define EF_R11 MIPS64_EF_R11 ++#define EF_R12 MIPS64_EF_R12 ++#define EF_R13 MIPS64_EF_R13 ++#define EF_R14 MIPS64_EF_R14 ++#define EF_R15 MIPS64_EF_R15 ++#define EF_R16 MIPS64_EF_R16 ++#define EF_R17 MIPS64_EF_R17 ++#define EF_R18 MIPS64_EF_R18 ++#define EF_R19 MIPS64_EF_R19 ++#define EF_R20 MIPS64_EF_R20 ++#define EF_R21 MIPS64_EF_R21 ++#define EF_R22 MIPS64_EF_R22 ++#define EF_R23 MIPS64_EF_R23 ++#define EF_R24 MIPS64_EF_R24 ++#define EF_R25 MIPS64_EF_R25 ++#define EF_R26 MIPS64_EF_R26 ++#define EF_R27 MIPS64_EF_R27 ++#define EF_R28 MIPS64_EF_R28 ++#define EF_R29 MIPS64_EF_R29 ++#define EF_R30 MIPS64_EF_R30 ++#define EF_R31 MIPS64_EF_R31 ++#define EF_LO MIPS64_EF_LO ++#define EF_HI MIPS64_EF_HI ++#define EF_CP0_EPC MIPS64_EF_CP0_EPC ++#define EF_CP0_BADVADDR MIPS64_EF_CP0_BADVADDR ++#define EF_CP0_STATUS MIPS64_EF_CP0_STATUS ++#define EF_CP0_CAUSE MIPS64_EF_CP0_CAUSE ++#define EF_SIZE MIPS64_EF_SIZE + + #endif /* CONFIG_64BIT */ + +--- a/arch/mips/kernel/binfmt_elfo32.c ++++ b/arch/mips/kernel/binfmt_elfo32.c +@@ -58,12 +58,6 @@ typedef elf_fpreg_t elf_fpregset_t[ELF_N + + #include + +-/* +- * When this file is selected, we are definitely running a 64bit kernel. +- * So using the right regs define in asm/reg.h +- */ +-#define WANT_COMPAT_REG_H +- + /* These MUST be defined before elf.h gets included */ + extern void elf32_core_copy_regs(elf_gregset_t grp, struct pt_regs *regs); + #define ELF_CORE_COPY_REGS(_dest, _regs) elf32_core_copy_regs(_dest, _regs); +@@ -135,21 +129,21 @@ void elf32_core_copy_regs(elf_gregset_t + { + int i; + +- for (i = 0; i < EF_R0; i++) ++ for (i = 0; i < MIPS32_EF_R0; i++) + grp[i] = 0; +- grp[EF_R0] = 0; ++ grp[MIPS32_EF_R0] = 0; + for (i = 1; i <= 31; i++) +- grp[EF_R0 + i] = (elf_greg_t) regs->regs[i]; +- grp[EF_R26] = 0; +- grp[EF_R27] = 0; +- grp[EF_LO] = (elf_greg_t) regs->lo; +- grp[EF_HI] = (elf_greg_t) regs->hi; +- grp[EF_CP0_EPC] = (elf_greg_t) regs->cp0_epc; +- grp[EF_CP0_BADVADDR] = (elf_greg_t) regs->cp0_badvaddr; +- grp[EF_CP0_STATUS] = (elf_greg_t) regs->cp0_status; +- grp[EF_CP0_CAUSE] = (elf_greg_t) regs->cp0_cause; +-#ifdef EF_UNUSED0 +- grp[EF_UNUSED0] = 0; ++ grp[MIPS32_EF_R0 + i] = (elf_greg_t) regs->regs[i]; ++ grp[MIPS32_EF_R26] = 0; ++ grp[MIPS32_EF_R27] = 0; ++ grp[MIPS32_EF_LO] = (elf_greg_t) regs->lo; ++ grp[MIPS32_EF_HI] = (elf_greg_t) regs->hi; ++ grp[MIPS32_EF_CP0_EPC] = (elf_greg_t) regs->cp0_epc; ++ grp[MIPS32_EF_CP0_BADVADDR] = (elf_greg_t) regs->cp0_badvaddr; ++ grp[MIPS32_EF_CP0_STATUS] = (elf_greg_t) regs->cp0_status; ++ grp[MIPS32_EF_CP0_CAUSE] = (elf_greg_t) regs->cp0_cause; ++#ifdef MIPS32_EF_UNUSED0 ++ grp[MIPS32_EF_UNUSED0] = 0; + #endif + } + diff --git a/queue-3.10/mips-asm-thread_info-add-_tif_seccomp-flag.patch b/queue-3.10/mips-asm-thread_info-add-_tif_seccomp-flag.patch new file mode 100644 index 00000000000..9d816419a0c --- /dev/null +++ b/queue-3.10/mips-asm-thread_info-add-_tif_seccomp-flag.patch @@ -0,0 +1,38 @@ +From 137f7df8cead00688524c82360930845396b8a21 Mon Sep 17 00:00:00 2001 +From: Markos Chandras +Date: Wed, 22 Jan 2014 14:40:00 +0000 +Subject: MIPS: asm: thread_info: Add _TIF_SECCOMP flag + +From: Markos Chandras + +commit 137f7df8cead00688524c82360930845396b8a21 upstream. + +Add _TIF_SECCOMP flag to _TIF_WORK_SYSCALL_ENTRY to indicate +that the system call needs to be checked against a seccomp filter. + +Signed-off-by: Markos Chandras +Reviewed-by: Paul Burton +Reviewed-by: James Hogan +Cc: linux-mips@linux-mips.org +Patchwork: https://patchwork.linux-mips.org/patch/6405/ +Signed-off-by: Ralf Baechle +[bwh: Backported to 3.2: various other flags are not included in + _TIF_WORK_SYSCALL_ENTRY] +Signed-off-by: Ben Hutchings +Signed-off-by: Greg Kroah-Hartman + +--- + arch/mips/include/asm/thread_info.h | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +--- a/arch/mips/include/asm/thread_info.h ++++ b/arch/mips/include/asm/thread_info.h +@@ -131,7 +131,7 @@ static inline struct thread_info *curren + #define _TIF_FPUBOUND (1< +Date: Wed, 29 May 2013 01:02:18 +0200 +Subject: MIPS: Cleanup flags in syscall flags handlers. + +From: Ralf Baechle + +commit e7f3b48af7be9f8007a224663a5b91340626fed5 upstream. + +This will simplify further modifications. + +Signed-off-by: Ralf Baechle +Signed-off-by: Greg Kroah-Hartman + +--- + arch/mips/include/asm/thread_info.h | 2 ++ + arch/mips/kernel/scall32-o32.S | 2 +- + arch/mips/kernel/scall64-64.S | 2 +- + arch/mips/kernel/scall64-n32.S | 2 +- + arch/mips/kernel/scall64-o32.S | 2 +- + 5 files changed, 6 insertions(+), 4 deletions(-) + +--- a/arch/mips/include/asm/thread_info.h ++++ b/arch/mips/include/asm/thread_info.h +@@ -131,6 +131,8 @@ static inline struct thread_info *curren + #define _TIF_FPUBOUND (1< yes + +--- a/arch/mips/kernel/scall64-64.S ++++ b/arch/mips/kernel/scall64-64.S +@@ -54,7 +54,7 @@ NESTED(handle_sys64, PT_SIZE, sp) + + sd a3, PT_R26(sp) # save a3 for syscall restarting + +- li t1, _TIF_SYSCALL_TRACE | _TIF_SYSCALL_AUDIT ++ li t1, _TIF_WORK_SYSCALL_ENTRY + LONG_L t0, TI_FLAGS($28) # syscall tracing enabled? + and t0, t1, t0 + bnez t0, syscall_trace_entry +--- a/arch/mips/kernel/scall64-n32.S ++++ b/arch/mips/kernel/scall64-n32.S +@@ -47,7 +47,7 @@ NESTED(handle_sysn32, PT_SIZE, sp) + + sd a3, PT_R26(sp) # save a3 for syscall restarting + +- li t1, _TIF_SYSCALL_TRACE | _TIF_SYSCALL_AUDIT ++ li t1, _TIF_WORK_SYSCALL_ENTRY + LONG_L t0, TI_FLAGS($28) # syscall tracing enabled? + and t0, t1, t0 + bnez t0, n32_syscall_trace_entry +--- a/arch/mips/kernel/scall64-o32.S ++++ b/arch/mips/kernel/scall64-o32.S +@@ -81,7 +81,7 @@ NESTED(handle_sys, PT_SIZE, sp) + PTR 4b, bad_stack + .previous + +- li t1, _TIF_SYSCALL_TRACE | _TIF_SYSCALL_AUDIT ++ li t1, _TIF_WORK_SYSCALL_ENTRY + LONG_L t0, TI_FLAGS($28) # syscall tracing enabled? + and t0, t1, t0 + bnez t0, trace_a_syscall diff --git a/queue-3.10/mips-fix-accessing-to-per-cpu-data-when-flushing-the-cache.patch b/queue-3.10/mips-fix-accessing-to-per-cpu-data-when-flushing-the-cache.patch new file mode 100644 index 00000000000..f155640c577 --- /dev/null +++ b/queue-3.10/mips-fix-accessing-to-per-cpu-data-when-flushing-the-cache.patch @@ -0,0 +1,89 @@ +From ff522058bd717506b2fa066fa564657f2b86477e Mon Sep 17 00:00:00 2001 +From: Ralf Baechle +Date: Tue, 17 Sep 2013 12:44:31 +0200 +Subject: MIPS: Fix accessing to per-cpu data when flushing the cache + +From: Ralf Baechle + +commit ff522058bd717506b2fa066fa564657f2b86477e upstream. + +This fixes the following issue + +BUG: using smp_processor_id() in preemptible [00000000] code: kjournald/1761 +caller is blast_dcache32+0x30/0x254 +Call Trace: +[<8047f02c>] dump_stack+0x8/0x34 +[<802e7e40>] debug_smp_processor_id+0xe0/0xf0 +[<80114d94>] blast_dcache32+0x30/0x254 +[<80118484>] r4k_dma_cache_wback_inv+0x200/0x288 +[<80110ff0>] mips_dma_map_sg+0x108/0x180 +[<80355098>] ide_dma_prepare+0xf0/0x1b8 +[<8034eaa4>] do_rw_taskfile+0x1e8/0x33c +[<8035951c>] ide_do_rw_disk+0x298/0x3e4 +[<8034a3c4>] do_ide_request+0x2e0/0x704 +[<802bb0dc>] __blk_run_queue+0x44/0x64 +[<802be000>] queue_unplugged.isra.36+0x1c/0x54 +[<802beb94>] blk_flush_plug_list+0x18c/0x24c +[<802bec6c>] blk_finish_plug+0x18/0x48 +[<8026554c>] journal_commit_transaction+0x3b8/0x151c +[<80269648>] kjournald+0xec/0x238 +[<8014ac00>] kthread+0xb8/0xc0 +[<8010268c>] ret_from_kernel_thread+0x14/0x1c + +Caches in most systems are identical - but not always, so we can't avoid +the use of smp_call_function() by just looking at the boot CPU's data, +have to fiddle with preemption instead. + +Signed-off-by: Ralf Baechle +Cc: Markos Chandras +Cc: linux-mips@linux-mips.org +Patchwork: https://patchwork.linux-mips.org/patch/5835 +Cc: Guenter Roeck +Signed-off-by: Greg Kroah-Hartman + +--- + arch/mips/mm/c-r4k.c | 5 +++++ + 1 file changed, 5 insertions(+) + +--- a/arch/mips/mm/c-r4k.c ++++ b/arch/mips/mm/c-r4k.c +@@ -12,6 +12,7 @@ + #include + #include + #include ++#include + #include + #include + #include +@@ -601,6 +602,7 @@ static void r4k_dma_cache_wback_inv(unsi + /* Catch bad driver code */ + BUG_ON(size == 0); + ++ preempt_disable(); + if (cpu_has_inclusive_pcaches) { + if (size >= scache_size) + r4k_blast_scache(); +@@ -621,6 +623,7 @@ static void r4k_dma_cache_wback_inv(unsi + R4600_HIT_CACHEOP_WAR_IMPL; + blast_dcache_range(addr, addr + size); + } ++ preempt_enable(); + + bc_wback_inv(addr, size); + __sync(); +@@ -631,6 +634,7 @@ static void r4k_dma_cache_inv(unsigned l + /* Catch bad driver code */ + BUG_ON(size == 0); + ++ preempt_disable(); + if (cpu_has_inclusive_pcaches) { + if (size >= scache_size) + r4k_blast_scache(); +@@ -655,6 +659,7 @@ static void r4k_dma_cache_inv(unsigned l + R4600_HIT_CACHEOP_WAR_IMPL; + blast_inv_dcache_range(addr, addr + size); + } ++ preempt_enable(); + + bc_inv(addr, size); + __sync(); diff --git a/queue-3.10/mips-gic-prevent-array-overrun.patch b/queue-3.10/mips-gic-prevent-array-overrun.patch new file mode 100644 index 00000000000..5faa5e606fe --- /dev/null +++ b/queue-3.10/mips-gic-prevent-array-overrun.patch @@ -0,0 +1,43 @@ +From ffc8415afab20bd97754efae6aad1f67b531132b Mon Sep 17 00:00:00 2001 +From: Jeffrey Deans +Date: Thu, 17 Jul 2014 09:20:56 +0100 +Subject: MIPS: GIC: Prevent array overrun + +From: Jeffrey Deans + +commit ffc8415afab20bd97754efae6aad1f67b531132b upstream. + +A GIC interrupt which is declared as having a GIC_MAP_TO_NMI_MSK +mapping causes the cpu parameter to gic_setup_intr() to be increased +to 32, causing memory corruption when pcpu_masks[] is written to again +later in the function. + +Signed-off-by: Jeffrey Deans +Signed-off-by: Markos Chandras +Cc: linux-mips@linux-mips.org +Patchwork: https://patchwork.linux-mips.org/patch/7375/ +Signed-off-by: Ralf Baechle +Signed-off-by: Greg Kroah-Hartman + +--- + arch/mips/kernel/irq-gic.c | 6 ++++-- + 1 file changed, 4 insertions(+), 2 deletions(-) + +--- a/arch/mips/kernel/irq-gic.c ++++ b/arch/mips/kernel/irq-gic.c +@@ -256,11 +256,13 @@ static void __init gic_setup_intr(unsign + + /* Setup Intr to Pin mapping */ + if (pin & GIC_MAP_TO_NMI_MSK) { ++ int i; ++ + GICWRITE(GIC_REG_ADDR(SHARED, GIC_SH_MAP_TO_PIN(intr)), pin); + /* FIXME: hack to route NMI to all cpu's */ +- for (cpu = 0; cpu < NR_CPUS; cpu += 32) { ++ for (i = 0; i < NR_CPUS; i += 32) { + GICWRITE(GIC_REG_ADDR(SHARED, +- GIC_SH_MAP_TO_VPE_REG_OFF(intr, cpu)), ++ GIC_SH_MAP_TO_VPE_REG_OFF(intr, i)), + 0xffffffff); + } + } else { diff --git a/queue-3.10/mips-octeon-make-get_system_type-thread-safe.patch b/queue-3.10/mips-octeon-make-get_system_type-thread-safe.patch new file mode 100644 index 00000000000..8d0ae0bbdef --- /dev/null +++ b/queue-3.10/mips-octeon-make-get_system_type-thread-safe.patch @@ -0,0 +1,66 @@ +From 608308682addfdc7b8e2aee88f0e028331d88e4d Mon Sep 17 00:00:00 2001 +From: Aaro Koskinen +Date: Tue, 22 Jul 2014 14:51:08 +0300 +Subject: MIPS: OCTEON: make get_system_type() thread-safe + +From: Aaro Koskinen + +commit 608308682addfdc7b8e2aee88f0e028331d88e4d upstream. + +get_system_type() is not thread-safe on OCTEON. It uses static data, +also more dangerous issue is that it's calling cvmx_fuse_read_byte() +every time without any synchronization. Currently it's possible to get +processes stuck looping forever in kernel simply by launching multiple +readers of /proc/cpuinfo: + + (while true; do cat /proc/cpuinfo > /dev/null; done) & + (while true; do cat /proc/cpuinfo > /dev/null; done) & + ... + +Fix by initializing the system type string only once during the early +boot. + +Signed-off-by: Aaro Koskinen +Reviewed-by: Markos Chandras +Patchwork: http://patchwork.linux-mips.org/patch/7437/ +Signed-off-by: James Hogan +Signed-off-by: Greg Kroah-Hartman + +--- + arch/mips/cavium-octeon/setup.c | 18 +++++++++++++----- + 1 file changed, 13 insertions(+), 5 deletions(-) + +--- a/arch/mips/cavium-octeon/setup.c ++++ b/arch/mips/cavium-octeon/setup.c +@@ -463,6 +463,18 @@ static void octeon_halt(void) + octeon_kill_core(NULL); + } + ++static char __read_mostly octeon_system_type[80]; ++ ++static int __init init_octeon_system_type(void) ++{ ++ snprintf(octeon_system_type, sizeof(octeon_system_type), "%s (%s)", ++ cvmx_board_type_to_string(octeon_bootinfo->board_type), ++ octeon_model_get_string(read_c0_prid())); ++ ++ return 0; ++} ++early_initcall(init_octeon_system_type); ++ + /** + * Handle all the error condition interrupts that might occur. + * +@@ -482,11 +494,7 @@ static irqreturn_t octeon_rlm_interrupt( + */ + const char *octeon_board_type_string(void) + { +- static char name[80]; +- sprintf(name, "%s (%s)", +- cvmx_board_type_to_string(octeon_bootinfo->board_type), +- octeon_model_get_string(read_c0_prid())); +- return name; ++ return octeon_system_type; + } + + const char *get_system_type(void) diff --git a/queue-3.10/mips-prevent-user-from-setting-fcsr-cause-bits.patch b/queue-3.10/mips-prevent-user-from-setting-fcsr-cause-bits.patch new file mode 100644 index 00000000000..acea6ade146 --- /dev/null +++ b/queue-3.10/mips-prevent-user-from-setting-fcsr-cause-bits.patch @@ -0,0 +1,58 @@ +From b1442d39fac2fcfbe6a4814979020e993ca59c9e Mon Sep 17 00:00:00 2001 +From: Paul Burton +Date: Tue, 22 Jul 2014 14:21:21 +0100 +Subject: MIPS: Prevent user from setting FCSR cause bits + +From: Paul Burton + +commit b1442d39fac2fcfbe6a4814979020e993ca59c9e upstream. + +If one or more matching FCSR cause & enable bits are set in saved thread +context then when that context is restored the kernel will take an FP +exception. This is of course undesirable and considered an oops, leading +to the kernel writing a backtrace to the console and potentially +rebooting depending upon the configuration. Thus the kernel avoids this +situation by clearing the cause bits of the FCSR register when handling +FP exceptions and after emulating FP instructions. + +However the kernel does not prevent userland from setting arbitrary FCSR +cause & enable bits via ptrace, using either the PTRACE_POKEUSR or +PTRACE_SETFPREGS requests. This means userland can trivially cause the +kernel to oops on any system with an FPU. Prevent this from happening +by clearing the cause bits when writing to the saved FCSR context via +ptrace. + +This problem appears to exist at least back to the beginning of the git +era in the PTRACE_POKEUSR case. + +Signed-off-by: Paul Burton +Cc: linux-mips@linux-mips.org +Cc: Paul Burton +Cc: stable@vger.kernel.org +Patchwork: https://patchwork.linux-mips.org/patch/7438/ +Signed-off-by: Ralf Baechle +Signed-off-by: Greg Kroah-Hartman + +--- + arch/mips/kernel/ptrace.c | 3 ++- + 1 file changed, 2 insertions(+), 1 deletion(-) + +--- a/arch/mips/kernel/ptrace.c ++++ b/arch/mips/kernel/ptrace.c +@@ -161,6 +161,7 @@ int ptrace_setfpregs(struct task_struct + __get_user(fregs[i], i + (__u64 __user *) data); + + __get_user(child->thread.fpu.fcr31, data + 64); ++ child->thread.fpu.fcr31 &= ~FPU_CSR_ALL_X; + + /* FIR may not be written. */ + +@@ -451,7 +452,7 @@ long arch_ptrace(struct task_struct *chi + break; + #endif + case FPC_CSR: +- child->thread.fpu.fcr31 = data; ++ child->thread.fpu.fcr31 = data & ~FPU_CSR_ALL_X; + break; + case DSP_BASE ... DSP_BASE + 5: { + dspreg_t *dregs; diff --git a/queue-3.10/mips-remove-bug_on-is_fpu_owner-in-do_ade.patch b/queue-3.10/mips-remove-bug_on-is_fpu_owner-in-do_ade.patch new file mode 100644 index 00000000000..ab4ad1e6847 --- /dev/null +++ b/queue-3.10/mips-remove-bug_on-is_fpu_owner-in-do_ade.patch @@ -0,0 +1,62 @@ +From 2e5767a27337812f6850b3fa362419e2f085e5c3 Mon Sep 17 00:00:00 2001 +From: Huacai Chen +Date: Wed, 16 Jul 2014 09:19:16 +0800 +Subject: MIPS: Remove BUG_ON(!is_fpu_owner()) in do_ade() + +From: Huacai Chen + +commit 2e5767a27337812f6850b3fa362419e2f085e5c3 upstream. + +In do_ade(), is_fpu_owner() isn't preempt-safe. For example, when an +unaligned ldc1 is executed, do_cpu() is called and then FPU will be +enabled (and TIF_USEDFPU will be set for the current process). Then, +do_ade() is called because the access is unaligned. If the current +process is preempted at this time, TIF_USEDFPU will be cleard. So when +the process is scheduled again, BUG_ON(!is_fpu_owner()) is triggered. + +This small program can trigger this BUG in a preemptible kernel: + +int main (int argc, char *argv[]) +{ + double u64[2]; + + while (1) { + asm volatile ( + ".set push \n\t" + ".set noreorder \n\t" + "ldc1 $f3, 4(%0) \n\t" + ".set pop \n\t" + ::"r"(u64): + ); + } + + return 0; +} + +V2: Remove the BUG_ON() unconditionally due to Paul's suggestion. + +Signed-off-by: Huacai Chen +Signed-off-by: Jie Chen +Signed-off-by: Rui Wang +Cc: John Crispin +Cc: Steven J. Hill +Cc: linux-mips@linux-mips.org +Cc: Fuxin Zhang +Cc: Zhangjin Wu +Signed-off-by: Ralf Baechle +Signed-off-by: Greg Kroah-Hartman + +--- + arch/mips/kernel/unaligned.c | 1 - + 1 file changed, 1 deletion(-) + +--- a/arch/mips/kernel/unaligned.c ++++ b/arch/mips/kernel/unaligned.c +@@ -604,7 +604,6 @@ static void emulate_load_store_insn(stru + case sdc1_op: + die_if_kernel("Unaligned FP access in kernel code", regs); + BUG_ON(!used_math()); +- BUG_ON(!is_fpu_owner()); + + lose_fpu(1); /* Save FPU state for the emulator. */ + res = fpu_emulator_cop1Handler(regs, ¤t->thread.fpu, 1, diff --git a/queue-3.10/mips-tlbex-fix-a-missing-statement-for-hugetlb.patch b/queue-3.10/mips-tlbex-fix-a-missing-statement-for-hugetlb.patch new file mode 100644 index 00000000000..26ac1be17da --- /dev/null +++ b/queue-3.10/mips-tlbex-fix-a-missing-statement-for-hugetlb.patch @@ -0,0 +1,40 @@ +From 8393c524a25609a30129e4a8975cf3b91f6c16a5 Mon Sep 17 00:00:00 2001 +From: Huacai Chen +Date: Tue, 29 Jul 2014 14:54:40 +0800 +Subject: MIPS: tlbex: Fix a missing statement for HUGETLB + +From: Huacai Chen + +commit 8393c524a25609a30129e4a8975cf3b91f6c16a5 upstream. + +In commit 2c8c53e28f1 (MIPS: Optimize TLB handlers for Octeon CPUs) +build_r4000_tlb_refill_handler() is modified. But it doesn't compatible +with the original code in HUGETLB case. Because there is a copy & paste +error and one line of code is missing. It is very easy to produce a bug +with LTP's hugemmap05 test. + +Signed-off-by: Huacai Chen +Signed-off-by: Binbin Zhou +Cc: John Crispin +Cc: Steven J. Hill +Cc: linux-mips@linux-mips.org +Cc: Fuxin Zhang +Cc: Zhangjin Wu +Patchwork: https://patchwork.linux-mips.org/patch/7496/ +Signed-off-by: Ralf Baechle +Signed-off-by: Greg Kroah-Hartman + +--- + arch/mips/mm/tlbex.c | 1 + + 1 file changed, 1 insertion(+) + +--- a/arch/mips/mm/tlbex.c ++++ b/arch/mips/mm/tlbex.c +@@ -1329,6 +1329,7 @@ static void __cpuinit build_r4000_tlb_re + } + #ifdef CONFIG_MIPS_HUGE_TLB_SUPPORT + uasm_l_tlb_huge_update(&l, p); ++ UASM_i_LW(&p, K0, 0, K1); + build_huge_update_entries(&p, htlb_info.huge_pte, K1); + build_huge_tlb_write_entry(&p, &l, &r, K0, tlb_random, + htlb_info.restore_scratch); diff --git a/queue-3.10/openrisc-rework-signal-handling.patch b/queue-3.10/openrisc-rework-signal-handling.patch new file mode 100644 index 00000000000..3c502a04849 --- /dev/null +++ b/queue-3.10/openrisc-rework-signal-handling.patch @@ -0,0 +1,406 @@ +From 10f67dbf6add97751050f294d4c8e0cc1e5c2c23 Mon Sep 17 00:00:00 2001 +From: Jonas Bonn +Date: Sun, 19 Feb 2012 17:36:53 +0100 +Subject: openrisc: Rework signal handling + +From: Jonas Bonn + +commit 10f67dbf6add97751050f294d4c8e0cc1e5c2c23 upstream. + +The mainline signal handling code for OpenRISC has been buggy since day +one with respect to syscall restart. This patch significantly reworks +the signal handling code: + +i) Move the "work pending" loop to C code (borrowed from ARM arch) + +ii) Allow a tracer to muck about with the IP and skip syscall restart + in that case (again, borrowed from ARM) + +iii) Make signal handling WRT syscall restart actually work + +v) Make the signal handling code look more like that of other + architectures so that it's easier for others to follow + +Reported-by: Anders Nystrom +Signed-off-by: Jonas Bonn +Cc: Guenter Roeck +Signed-off-by: Greg Kroah-Hartman + + +--- + arch/openrisc/kernel/entry.S | 59 +++++++----- + arch/openrisc/kernel/signal.c | 198 ++++++++++++++++++++++-------------------- + 2 files changed, 139 insertions(+), 118 deletions(-) + +--- a/arch/openrisc/kernel/entry.S ++++ b/arch/openrisc/kernel/entry.S +@@ -853,37 +853,44 @@ UNHANDLED_EXCEPTION(_vector_0x1f00,0x1f0 + + /* ========================================================[ return ] === */ + ++_resume_userspace: ++ DISABLE_INTERRUPTS(r3,r4) ++ l.lwz r4,TI_FLAGS(r10) ++ l.andi r13,r4,_TIF_WORK_MASK ++ l.sfeqi r13,0 ++ l.bf _restore_all ++ l.nop ++ + _work_pending: +- /* +- * if (current_thread_info->flags & _TIF_NEED_RESCHED) +- * schedule(); +- */ +- l.lwz r5,TI_FLAGS(r10) +- l.andi r3,r5,_TIF_NEED_RESCHED +- l.sfnei r3,0 +- l.bnf _work_notifysig ++ l.lwz r5,PT_ORIG_GPR11(r1) ++ l.sfltsi r5,0 ++ l.bnf 1f + l.nop +- l.jal schedule ++ l.andi r5,r5,0 ++1: ++ l.jal do_work_pending ++ l.ori r3,r1,0 /* pt_regs */ ++ ++ l.sfeqi r11,0 ++ l.bf _restore_all + l.nop +- l.j _resume_userspace ++ l.sfltsi r11,0 ++ l.bnf 1f + l.nop +- +-/* Handle pending signals and notify-resume requests. +- * do_notify_resume must be passed the latest pushed pt_regs, not +- * necessarily the "userspace" ones. Also, pt_regs->syscallno +- * must be set so that the syscall restart functionality works. +- */ +-_work_notifysig: +- l.jal do_notify_resume +- l.ori r3,r1,0 /* pt_regs */ +- +-_resume_userspace: +- DISABLE_INTERRUPTS(r3,r4) +- l.lwz r3,TI_FLAGS(r10) +- l.andi r3,r3,_TIF_WORK_MASK +- l.sfnei r3,0 +- l.bf _work_pending ++ l.and r11,r11,r0 ++ l.ori r11,r11,__NR_restart_syscall ++ l.j _syscall_check_trace_enter + l.nop ++1: ++ l.lwz r11,PT_ORIG_GPR11(r1) ++ /* Restore arg registers */ ++ l.lwz r3,PT_GPR3(r1) ++ l.lwz r4,PT_GPR4(r1) ++ l.lwz r5,PT_GPR5(r1) ++ l.lwz r6,PT_GPR6(r1) ++ l.lwz r7,PT_GPR7(r1) ++ l.j _syscall_check_trace_enter ++ l.lwz r8,PT_GPR8(r1) + + _restore_all: + RESTORE_ALL +--- a/arch/openrisc/kernel/signal.c ++++ b/arch/openrisc/kernel/signal.c +@@ -28,24 +28,24 @@ + #include + + #include ++#include + #include + #include + + #define DEBUG_SIG 0 + + struct rt_sigframe { +- struct siginfo *pinfo; +- void *puc; + struct siginfo info; + struct ucontext uc; + unsigned char retcode[16]; /* trampoline code */ + }; + +-static int restore_sigcontext(struct pt_regs *regs, struct sigcontext *sc) ++static int restore_sigcontext(struct pt_regs *regs, ++ struct sigcontext __user *sc) + { +- unsigned int err = 0; ++ int err = 0; + +- /* Alwys make any pending restarted system call return -EINTR */ ++ /* Always make any pending restarted system calls return -EINTR */ + current_thread_info()->restart_block.fn = do_no_restart_syscall; + + /* +@@ -53,25 +53,21 @@ static int restore_sigcontext(struct pt_ + * (sc is already checked for VERIFY_READ since the sigframe was + * checked in sys_sigreturn previously) + */ +- if (__copy_from_user(regs, sc->regs.gpr, 32 * sizeof(unsigned long))) +- goto badframe; +- if (__copy_from_user(®s->pc, &sc->regs.pc, sizeof(unsigned long))) +- goto badframe; +- if (__copy_from_user(®s->sr, &sc->regs.sr, sizeof(unsigned long))) +- goto badframe; ++ err |= __copy_from_user(regs, sc->regs.gpr, 32 * sizeof(unsigned long)); ++ err |= __copy_from_user(®s->pc, &sc->regs.pc, sizeof(unsigned long)); ++ err |= __copy_from_user(®s->sr, &sc->regs.sr, sizeof(unsigned long)); + + /* make sure the SM-bit is cleared so user-mode cannot fool us */ + regs->sr &= ~SPR_SR_SM; + ++ regs->orig_gpr11 = -1; /* Avoid syscall restart checks */ ++ + /* TODO: the other ports use regs->orig_XX to disable syscall checks + * after this completes, but we don't use that mechanism. maybe we can + * use it now ? + */ + + return err; +- +-badframe: +- return 1; + } + + asmlinkage long _sys_rt_sigreturn(struct pt_regs *regs) +@@ -111,21 +107,18 @@ badframe: + * Set up a signal frame. + */ + +-static int setup_sigcontext(struct sigcontext *sc, struct pt_regs *regs, +- unsigned long mask) ++static int setup_sigcontext(struct pt_regs *regs, struct sigcontext __user *sc) + { + int err = 0; + + /* copy the regs */ +- ++ /* There should be no need to save callee-saved registers here... ++ * ...but we save them anyway. Revisit this ++ */ + err |= __copy_to_user(sc->regs.gpr, regs, 32 * sizeof(unsigned long)); + err |= __copy_to_user(&sc->regs.pc, ®s->pc, sizeof(unsigned long)); + err |= __copy_to_user(&sc->regs.sr, ®s->sr, sizeof(unsigned long)); + +- /* then some other stuff */ +- +- err |= __put_user(mask, &sc->oldmask); +- + return err; + } + +@@ -181,24 +174,18 @@ static int setup_rt_frame(int sig, struc + int err = 0; + + frame = get_sigframe(ka, regs, sizeof(*frame)); +- + if (!access_ok(VERIFY_WRITE, frame, sizeof(*frame))) + goto give_sigsegv; + +- err |= __put_user(&frame->info, &frame->pinfo); +- err |= __put_user(&frame->uc, &frame->puc); +- ++ /* Create siginfo. */ + if (ka->sa.sa_flags & SA_SIGINFO) + err |= copy_siginfo_to_user(&frame->info, info); +- if (err) +- goto give_sigsegv; + +- /* Clear all the bits of the ucontext we don't use. */ +- err |= __clear_user(&frame->uc, offsetof(struct ucontext, uc_mcontext)); ++ /* Create the ucontext. */ + err |= __put_user(0, &frame->uc.uc_flags); + err |= __put_user(NULL, &frame->uc.uc_link); + err |= __save_altstack(&frame->uc.uc_stack, regs->sp); +- err |= setup_sigcontext(&frame->uc.uc_mcontext, regs, set->sig[0]); ++ err |= setup_sigcontext(regs, &frame->uc.uc_mcontext); + + err |= __copy_to_user(&frame->uc.uc_sigmask, set, sizeof(*set)); + +@@ -207,9 +194,12 @@ static int setup_rt_frame(int sig, struc + + /* trampoline - the desired return ip is the retcode itself */ + return_ip = (unsigned long)&frame->retcode; +- /* This is l.ori r11,r0,__NR_sigreturn, l.sys 1 */ +- err |= __put_user(0xa960, (short *)(frame->retcode + 0)); +- err |= __put_user(__NR_rt_sigreturn, (short *)(frame->retcode + 2)); ++ /* This is: ++ l.ori r11,r0,__NR_sigreturn ++ l.sys 1 ++ */ ++ err |= __put_user(0xa960, (short *)(frame->retcode + 0)); ++ err |= __put_user(__NR_rt_sigreturn, (short *)(frame->retcode + 2)); + err |= __put_user(0x20000001, (unsigned long *)(frame->retcode + 4)); + err |= __put_user(0x15000000, (unsigned long *)(frame->retcode + 8)); + +@@ -262,82 +252,106 @@ handle_signal(unsigned long sig, + * mode below. + */ + +-void do_signal(struct pt_regs *regs) ++int do_signal(struct pt_regs *regs, int syscall) + { + siginfo_t info; + int signr; + struct k_sigaction ka; +- +- /* +- * We want the common case to go fast, which +- * is why we may in certain cases get here from +- * kernel mode. Just return without doing anything +- * if so. +- */ +- if (!user_mode(regs)) +- return; +- +- signr = get_signal_to_deliver(&info, &ka, regs, NULL); +- +- /* If we are coming out of a syscall then we need +- * to check if the syscall was interrupted and wants to be +- * restarted after handling the signal. If so, the original +- * syscall number is put back into r11 and the PC rewound to +- * point at the l.sys instruction that resulted in the +- * original syscall. Syscall results other than the four +- * below mean that the syscall executed to completion and no +- * restart is necessary. +- */ +- if (regs->orig_gpr11) { +- int restart = 0; +- +- switch (regs->gpr[11]) { ++ unsigned long continue_addr = 0; ++ unsigned long restart_addr = 0; ++ unsigned long retval = 0; ++ int restart = 0; ++ ++ if (syscall) { ++ continue_addr = regs->pc; ++ restart_addr = continue_addr - 4; ++ retval = regs->gpr[11]; ++ ++ /* ++ * Setup syscall restart here so that a debugger will ++ * see the already changed PC. ++ */ ++ switch (retval) { + case -ERESTART_RESTARTBLOCK: ++ restart = -2; ++ /* Fall through */ + case -ERESTARTNOHAND: +- /* Restart if there is no signal handler */ +- restart = (signr <= 0); +- break; + case -ERESTARTSYS: +- /* Restart if there no signal handler or +- * SA_RESTART flag is set */ +- restart = (signr <= 0 || (ka.sa.sa_flags & SA_RESTART)); +- break; + case -ERESTARTNOINTR: +- /* Always restart */ +- restart = 1; ++ restart++; ++ regs->gpr[11] = regs->orig_gpr11; ++ regs->pc = restart_addr; + break; + } ++ } + +- if (restart) { +- if (regs->gpr[11] == -ERESTART_RESTARTBLOCK) +- regs->gpr[11] = __NR_restart_syscall; +- else +- regs->gpr[11] = regs->orig_gpr11; +- regs->pc -= 4; +- } else { +- regs->gpr[11] = -EINTR; ++ /* ++ * Get the signal to deliver. When running under ptrace, at this ++ * point the debugger may change all our registers ... ++ */ ++ signr = get_signal_to_deliver(&info, &ka, regs, NULL); ++ /* ++ * Depending on the signal settings we may need to revert the ++ * decision to restart the system call. But skip this if a ++ * debugger has chosen to restart at a different PC. ++ */ ++ if (signr > 0) { ++ if (unlikely(restart) && regs->pc == restart_addr) { ++ if (retval == -ERESTARTNOHAND || ++ retval == -ERESTART_RESTARTBLOCK ++ || (retval == -ERESTARTSYS ++ && !(ka.sa.sa_flags & SA_RESTART))) { ++ /* No automatic restart */ ++ regs->gpr[11] = -EINTR; ++ regs->pc = continue_addr; ++ } + } +- } + +- if (signr <= 0) { +- /* no signal to deliver so we just put the saved sigmask +- * back */ +- restore_saved_sigmask(); +- } else { /* signr > 0 */ +- /* Whee! Actually deliver the signal. */ + handle_signal(signr, &info, &ka, regs); ++ } else { ++ /* no handler */ ++ restore_saved_sigmask(); ++ /* ++ * Restore pt_regs PC as syscall restart will be handled by ++ * kernel without return to userspace ++ */ ++ if (unlikely(restart) && regs->pc == restart_addr) { ++ regs->pc = continue_addr; ++ return restart; ++ } + } + +- return; ++ return 0; + } + +-asmlinkage void do_notify_resume(struct pt_regs *regs) ++asmlinkage int ++do_work_pending(struct pt_regs *regs, unsigned int thread_flags, int syscall) + { +- if (current_thread_info()->flags & _TIF_SIGPENDING) +- do_signal(regs); +- +- if (current_thread_info()->flags & _TIF_NOTIFY_RESUME) { +- clear_thread_flag(TIF_NOTIFY_RESUME); +- tracehook_notify_resume(regs); +- } ++ do { ++ if (likely(thread_flags & _TIF_NEED_RESCHED)) { ++ schedule(); ++ } else { ++ if (unlikely(!user_mode(regs))) ++ return 0; ++ local_irq_enable(); ++ if (thread_flags & _TIF_SIGPENDING) { ++ int restart = do_signal(regs, syscall); ++ if (unlikely(restart)) { ++ /* ++ * Restart without handlers. ++ * Deal with it without leaving ++ * the kernel space. ++ */ ++ return restart; ++ } ++ syscall = 0; ++ } else { ++ clear_thread_flag(TIF_NOTIFY_RESUME); ++ tracehook_notify_resume(regs); ++ } ++ } ++ local_irq_disable(); ++ thread_flags = current_thread_info()->flags; ++ } while (thread_flags & _TIF_WORK_MASK); ++ return 0; + } diff --git a/queue-3.10/series b/queue-3.10/series index f8d56aae906..5e6e0263cd8 100644 --- a/queue-3.10/series +++ b/queue-3.10/series @@ -16,3 +16,13 @@ powerpc-mm-use-read-barrier-when-creating-real_pte.patch powerpc-pseries-failure-on-removing-device-node.patch drivers-scsi-storvsc-implement-a-eh_timed_out-handler.patch drivers-scsi-storvsc-correctly-handle-test_unit_ready-failure.patch +mips-gic-prevent-array-overrun.patch +mips-prevent-user-from-setting-fcsr-cause-bits.patch +mips-tlbex-fix-a-missing-statement-for-hugetlb.patch +mips-remove-bug_on-is_fpu_owner-in-do_ade.patch +mips-asm-reg.h-make-32-and-64-bit-definitions-available-at-the-same-time.patch +mips-cleanup-flags-in-syscall-flags-handlers.patch +mips-asm-thread_info-add-_tif_seccomp-flag.patch +mips-octeon-make-get_system_type-thread-safe.patch +mips-fix-accessing-to-per-cpu-data-when-flushing-the-cache.patch +openrisc-rework-signal-handling.patch