From: Qiang Yu Date: Fri, 19 Sep 2025 14:23:25 +0000 (+0530) Subject: dt-bindings: PCI: qcom,pcie-x1e80100: Set clocks minItems for the fifth Glymur PCIe... X-Git-Tag: v6.18-rc1~60^2~19^2 X-Git-Url: http://git.ipfire.org/?a=commitdiff_plain;h=96a17ed17b369109b662b40345df961b412c1cd3;p=thirdparty%2Flinux.git dt-bindings: PCI: qcom,pcie-x1e80100: Set clocks minItems for the fifth Glymur PCIe Controller On the Qualcomm Glymur platform, the fifth PCIe host is compatible with the DWC controller present on the X1E80100 platform, but does not have cnoc_sf_axi clock. Hence, set minItems of clocks and clock-names to six. Signed-off-by: Qiang Yu Signed-off-by: Pankaj Patil Signed-off-by: Bjorn Helgaas Acked-by: Rob Herring (Arm) Link: https://patch.msgid.link/20250919142325.1090059-1-pankaj.patil@oss.qualcomm.com --- diff --git a/Documentation/devicetree/bindings/pci/qcom,pcie-x1e80100.yaml b/Documentation/devicetree/bindings/pci/qcom,pcie-x1e80100.yaml index 257068a182649..61581ffbfb248 100644 --- a/Documentation/devicetree/bindings/pci/qcom,pcie-x1e80100.yaml +++ b/Documentation/devicetree/bindings/pci/qcom,pcie-x1e80100.yaml @@ -32,10 +32,11 @@ properties: - const: mhi # MHI registers clocks: - minItems: 7 + minItems: 6 maxItems: 7 clock-names: + minItems: 6 items: - const: aux # Auxiliary clock - const: cfg # Configuration clock