From: Gabriel Fernandez Date: Thu, 14 Feb 2019 10:40:47 +0000 (+0100) Subject: clk: stm32mp1: fix bit width of hse_rtc divider X-Git-Tag: v5.1-rc1~34^2~8^4~1 X-Git-Url: http://git.ipfire.org/?a=commitdiff_plain;h=97621d22df60d7348826d2e4b0c349673faeb4b8;p=thirdparty%2Fkernel%2Flinux.git clk: stm32mp1: fix bit width of hse_rtc divider Fix the bit width of the hse rtc divider because it's off by one. Fixes: 2c87c9d33117 ("clk: stm32mp1: add RTC clock") Signed-off-by: Gabriel Fernandez Signed-off-by: Stephen Boyd --- diff --git a/drivers/clk/clk-stm32mp1.c b/drivers/clk/clk-stm32mp1.c index ca987632564e1..a0ae8dc169090 100644 --- a/drivers/clk/clk-stm32mp1.c +++ b/drivers/clk/clk-stm32mp1.c @@ -1962,7 +1962,7 @@ static const struct clock_config stm32mp1_clock_cfg[] = { _DIV(RCC_ETHCKSELR, 4, 4, 0, NULL)), /* RTC clock */ - DIV(NO_ID, "ck_hse_rtc", "ck_hse", 0, RCC_RTCDIVR, 0, 7, 0), + DIV(NO_ID, "ck_hse_rtc", "ck_hse", 0, RCC_RTCDIVR, 0, 6, 0), COMPOSITE(RTC, "ck_rtc", rtc_src, CLK_OPS_PARENT_ENABLE | CLK_SET_RATE_PARENT,