From: Greg Kroah-Hartman Date: Mon, 6 Jan 2014 17:45:53 +0000 (-0800) Subject: 3.12-stable patches X-Git-Tag: v3.4.76~43 X-Git-Url: http://git.ipfire.org/?a=commitdiff_plain;h=9767b950b5b33231e3d33739a5e80f01a554b5ea;p=thirdparty%2Fkernel%2Fstable-queue.git 3.12-stable patches added patches: drm-radeon-0x9649-is-sumo2-not-sumo.patch drm-radeon-expose-render-backend-mask-to-the-userspace.patch --- diff --git a/queue-3.12/drm-radeon-0x9649-is-sumo2-not-sumo.patch b/queue-3.12/drm-radeon-0x9649-is-sumo2-not-sumo.patch new file mode 100644 index 00000000000..9ba4e09570d --- /dev/null +++ b/queue-3.12/drm-radeon-0x9649-is-sumo2-not-sumo.patch @@ -0,0 +1,33 @@ +From d00adcc8ae9e22eca9d8af5f66c59ad9a74c90ec Mon Sep 17 00:00:00 2001 +From: Alex Deucher +Date: Mon, 23 Dec 2013 09:31:58 -0500 +Subject: drm/radeon: 0x9649 is SUMO2 not SUMO + +From: Alex Deucher + +commit d00adcc8ae9e22eca9d8af5f66c59ad9a74c90ec upstream. + +Fixes rendering corruption due to incorrect +gfx configuration. + +bug: +https://bugs.freedesktop.org/show_bug.cgi?id=63599 + +Signed-off-by: Alex Deucher +Signed-off-by: Greg Kroah-Hartman + +--- + include/drm/drm_pciids.h | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +--- a/include/drm/drm_pciids.h ++++ b/include/drm/drm_pciids.h +@@ -588,7 +588,7 @@ + {0x1002, 0x9645, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SUMO2|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP|RADEON_IS_IGP}, \ + {0x1002, 0x9647, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SUMO|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP|RADEON_IS_IGP},\ + {0x1002, 0x9648, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SUMO|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP|RADEON_IS_IGP},\ +- {0x1002, 0x9649, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SUMO|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP|RADEON_IS_IGP},\ ++ {0x1002, 0x9649, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SUMO2|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP|RADEON_IS_IGP},\ + {0x1002, 0x964a, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SUMO|RADEON_NEW_MEMMAP|RADEON_IS_IGP}, \ + {0x1002, 0x964b, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SUMO|RADEON_NEW_MEMMAP|RADEON_IS_IGP}, \ + {0x1002, 0x964c, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SUMO|RADEON_NEW_MEMMAP|RADEON_IS_IGP}, \ diff --git a/queue-3.12/drm-radeon-expose-render-backend-mask-to-the-userspace.patch b/queue-3.12/drm-radeon-expose-render-backend-mask-to-the-userspace.patch new file mode 100644 index 00000000000..2d05683fc68 --- /dev/null +++ b/queue-3.12/drm-radeon-expose-render-backend-mask-to-the-userspace.patch @@ -0,0 +1,95 @@ +From 439a1cfffe2c1a06e5a6394ccd5d18a8e89b15d3 Mon Sep 17 00:00:00 2001 +From: Marek Olšák +Date: Sun, 22 Dec 2013 02:18:01 +0100 +Subject: drm/radeon: expose render backend mask to the userspace + +From: Marek Olšák + +commit 439a1cfffe2c1a06e5a6394ccd5d18a8e89b15d3 upstream. + +This will allow userspace to correctly program the PA_SC_RASTER_CONFIG +register, so it can be considered a fix. + +Signed-off-by: Marek Olšák +Signed-off-by: Alex Deucher +Signed-off-by: Greg Kroah-Hartman + +--- + drivers/gpu/drm/radeon/cik.c | 2 ++ + drivers/gpu/drm/radeon/radeon.h | 4 ++-- + drivers/gpu/drm/radeon/radeon_kms.c | 9 +++++++++ + drivers/gpu/drm/radeon/si.c | 2 ++ + include/uapi/drm/radeon_drm.h | 2 ++ + 5 files changed, 17 insertions(+), 2 deletions(-) + +--- a/drivers/gpu/drm/radeon/cik.c ++++ b/drivers/gpu/drm/radeon/cik.c +@@ -2662,6 +2662,8 @@ static void cik_setup_rb(struct radeon_d + mask <<= 1; + } + ++ rdev->config.cik.backend_enable_mask = enabled_rbs; ++ + for (i = 0; i < se_num; i++) { + cik_select_se_sh(rdev, i, 0xffffffff); + data = 0; +--- a/drivers/gpu/drm/radeon/radeon.h ++++ b/drivers/gpu/drm/radeon/radeon.h +@@ -1930,7 +1930,7 @@ struct si_asic { + unsigned sc_earlyz_tile_fifo_size; + + unsigned num_tile_pipes; +- unsigned num_backends_per_se; ++ unsigned backend_enable_mask; + unsigned backend_disable_mask_per_asic; + unsigned backend_map; + unsigned num_texture_channel_caches; +@@ -1960,7 +1960,7 @@ struct cik_asic { + unsigned sc_earlyz_tile_fifo_size; + + unsigned num_tile_pipes; +- unsigned num_backends_per_se; ++ unsigned backend_enable_mask; + unsigned backend_disable_mask_per_asic; + unsigned backend_map; + unsigned num_texture_channel_caches; +--- a/drivers/gpu/drm/radeon/radeon_kms.c ++++ b/drivers/gpu/drm/radeon/radeon_kms.c +@@ -436,6 +436,15 @@ int radeon_info_ioctl(struct drm_device + case RADEON_INFO_SI_CP_DMA_COMPUTE: + *value = 1; + break; ++ case RADEON_INFO_SI_BACKEND_ENABLED_MASK: ++ if (rdev->family >= CHIP_BONAIRE) { ++ *value = rdev->config.cik.backend_enable_mask; ++ } else if (rdev->family >= CHIP_TAHITI) { ++ *value = rdev->config.si.backend_enable_mask; ++ } else { ++ DRM_DEBUG_KMS("BACKEND_ENABLED_MASK is si+ only!\n"); ++ } ++ break; + default: + DRM_DEBUG_KMS("Invalid request %d\n", info->request); + return -EINVAL; +--- a/drivers/gpu/drm/radeon/si.c ++++ b/drivers/gpu/drm/radeon/si.c +@@ -2860,6 +2860,8 @@ static void si_setup_rb(struct radeon_de + mask <<= 1; + } + ++ rdev->config.si.backend_enable_mask = enabled_rbs; ++ + for (i = 0; i < se_num; i++) { + si_select_se_sh(rdev, i, 0xffffffff); + data = 0; +--- a/include/uapi/drm/radeon_drm.h ++++ b/include/uapi/drm/radeon_drm.h +@@ -981,6 +981,8 @@ struct drm_radeon_cs { + #define RADEON_INFO_SI_TILE_MODE_ARRAY 0x16 + /* query if CP DMA is supported on the compute ring */ + #define RADEON_INFO_SI_CP_DMA_COMPUTE 0x17 ++/* query the number of render backends */ ++#define RADEON_INFO_SI_BACKEND_ENABLED_MASK 0x19 + + + struct drm_radeon_info { diff --git a/queue-3.12/series b/queue-3.12/series index 6b2405796ec..196f9efc8e0 100644 --- a/queue-3.12/series +++ b/queue-3.12/series @@ -76,3 +76,5 @@ drm-i915-change-crtc-assertion-on-lcpll-disable.patch drm-i915-use-the-correct-gmch_ctrl-register-for-sandybridge.patch drm-radeon-fix-uvd-256mb-check.patch drm-radeon-fix-render-backend-setup-for-si-and-cik.patch +drm-radeon-expose-render-backend-mask-to-the-userspace.patch +drm-radeon-0x9649-is-sumo2-not-sumo.patch