From: Greg Kroah-Hartman Date: Fri, 8 Mar 2019 10:47:58 +0000 (+0100) Subject: 4.9-stable patches X-Git-Tag: v5.0.1~17 X-Git-Url: http://git.ipfire.org/?a=commitdiff_plain;h=97a42da40a26745a81afda3a676406235a55b9c8;p=thirdparty%2Fkernel%2Fstable-queue.git 4.9-stable patches added patches: x86-cpu-amd-set-the-cpb-bit-unconditionally-on-f17h.patch --- diff --git a/queue-4.9/series b/queue-4.9/series index b831bd88994..cb2b1df5227 100644 --- a/queue-4.9/series +++ b/queue-4.9/series @@ -25,3 +25,4 @@ net-avoid-use-ipcb-in-cipso_v4_error.patch tun-fix-blocking-read.patch tun-remove-unnecessary-memory-barrier.patch net-phy-micrel-ksz8061-link-failure-after-cable-connect.patch +x86-cpu-amd-set-the-cpb-bit-unconditionally-on-f17h.patch diff --git a/queue-4.9/x86-cpu-amd-set-the-cpb-bit-unconditionally-on-f17h.patch b/queue-4.9/x86-cpu-amd-set-the-cpb-bit-unconditionally-on-f17h.patch new file mode 100644 index 00000000000..466e19ab30f --- /dev/null +++ b/queue-4.9/x86-cpu-amd-set-the-cpb-bit-unconditionally-on-f17h.patch @@ -0,0 +1,47 @@ +From 0237199186e7a4aa5310741f0a6498a20c820fd7 Mon Sep 17 00:00:00 2001 +From: Jiaxun Yang +Date: Tue, 20 Nov 2018 11:00:18 +0800 +Subject: x86/CPU/AMD: Set the CPB bit unconditionally on F17h + +From: Jiaxun Yang + +commit 0237199186e7a4aa5310741f0a6498a20c820fd7 upstream. + +Some F17h models do not have CPB set in CPUID even though the CPU +supports it. Set the feature bit unconditionally on all F17h. + + [ bp: Rewrite commit message and patch. ] + +Signed-off-by: Jiaxun Yang +Signed-off-by: Borislav Petkov +Acked-by: Tom Lendacky +Cc: "H. Peter Anvin" +Cc: Ingo Molnar +Cc: Sherry Hurwitz +Cc: Suravee Suthikulpanit +Cc: Thomas Gleixner +Cc: x86-ml +Link: https://lkml.kernel.org/r/20181120030018.5185-1-jiaxun.yang@flygoat.com +Signed-off-by: Greg Kroah-Hartman + +--- + arch/x86/kernel/cpu/amd.c | 8 +++----- + 1 file changed, 3 insertions(+), 5 deletions(-) + +--- a/arch/x86/kernel/cpu/amd.c ++++ b/arch/x86/kernel/cpu/amd.c +@@ -765,11 +765,9 @@ static void init_amd_bd(struct cpuinfo_x + static void init_amd_zn(struct cpuinfo_x86 *c) + { + set_cpu_cap(c, X86_FEATURE_ZEN); +- /* +- * Fix erratum 1076: CPB feature bit not being set in CPUID. It affects +- * all up to and including B1. +- */ +- if (c->x86_model <= 1 && c->x86_stepping <= 1) ++ ++ /* Fix erratum 1076: CPB feature bit not being set in CPUID. */ ++ if (!cpu_has(c, X86_FEATURE_CPB)) + set_cpu_cap(c, X86_FEATURE_CPB); + } +