From: Zenghui Yu Date: Wed, 9 Jul 2025 13:00:46 +0000 (+0800) Subject: irqchip/gic-v3: Fix GICD_CTLR register naming X-Git-Url: http://git.ipfire.org/?a=commitdiff_plain;h=97c03ec2c0e0621bbd7a56f5be19bd2de552e6f4;p=thirdparty%2Fkernel%2Flinux.git irqchip/gic-v3: Fix GICD_CTLR register naming It was incorrectly named as GICD_CTRL in a pr_info() and comments. Fix them. Signed-off-by: Zenghui Yu Signed-off-by: Thomas Gleixner Acked-by: Marc Zyngier Link: https://lore.kernel.org/all/20250709130046.1354-1-yuzenghui@huawei.com --- diff --git a/drivers/irqchip/irq-gic-v3.c b/drivers/irqchip/irq-gic-v3.c index efc791c43d441..dbeb85677b08c 100644 --- a/drivers/irqchip/irq-gic-v3.c +++ b/drivers/irqchip/irq-gic-v3.c @@ -190,12 +190,12 @@ static void __init gic_prio_init(void) /* * How priority values are used by the GIC depends on two things: - * the security state of the GIC (controlled by the GICD_CTRL.DS bit) + * the security state of the GIC (controlled by the GICD_CTLR.DS bit) * and if Group 0 interrupts can be delivered to Linux in the non-secure * world as FIQs (controlled by the SCR_EL3.FIQ bit). These affect the * way priorities are presented in ICC_PMR_EL1 and in the distributor: * - * GICD_CTRL.DS | SCR_EL3.FIQ | ICC_PMR_EL1 | Distributor + * GICD_CTLR.DS | SCR_EL3.FIQ | ICC_PMR_EL1 | Distributor * ------------------------------------------------------- * 1 | - | unchanged | unchanged * ------------------------------------------------------- @@ -223,7 +223,7 @@ static void __init gic_prio_init(void) dist_prio_nmi = __gicv3_prio_to_ns(dist_prio_nmi); } - pr_info("GICD_CTRL.DS=%d, SCR_EL3.FIQ=%d\n", + pr_info("GICD_CTLR.DS=%d, SCR_EL3.FIQ=%d\n", cpus_have_security_disabled, !cpus_have_group0); }