From: Dmitry Osipenko Date: Sun, 23 Aug 2020 14:47:24 +0000 (+0300) Subject: ARM: tegra: acer-a500: Use PLLC for WiFi MMC clock parent X-Git-Tag: v5.10-rc1~26^2~19^2~3 X-Git-Url: http://git.ipfire.org/?a=commitdiff_plain;h=98e710a01738cc99fce0830e4949710bb10fd4ee;p=thirdparty%2Flinux.git ARM: tegra: acer-a500: Use PLLC for WiFi MMC clock parent The default parent for all MMCs is PLLP, which is running at 216 MHz on Tegra20 and 50 MHz clock can't be derived from PLLP. The maximum SDIO clock rate is 50 MHz, but this rate isn't achievable using PLLP. Let's switch the WiFi MMC clock parent to PLLC in order to get true 50 MHz. This patch doesn't fix any problems, it's just a minor improvement. Signed-off-by: Dmitry Osipenko Signed-off-by: Thierry Reding --- diff --git a/arch/arm/boot/dts/tegra20-acer-a500-picasso.dts b/arch/arm/boot/dts/tegra20-acer-a500-picasso.dts index 9489eedcf0c9d..a0b829738e8f2 100644 --- a/arch/arm/boot/dts/tegra20-acer-a500-picasso.dts +++ b/arch/arm/boot/dts/tegra20-acer-a500-picasso.dts @@ -736,6 +736,10 @@ #address-cells = <1>; #size-cells = <0>; + assigned-clocks = <&tegra_car TEGRA20_CLK_SDMMC1>; + assigned-clock-parents = <&tegra_car TEGRA20_CLK_PLL_C>; + assigned-clock-rates = <50000000>; + max-frequency = <50000000>; keep-power-in-suspend; bus-width = <4>;