From: Jiri Vanek Date: Wed, 15 Jun 2022 22:22:21 +0000 (+0200) Subject: drm/bridge/tc358775: Fix DSI clock division for vsync delay calculation X-Git-Tag: v6.0-rc1~138^2~20^2~30 X-Git-Url: http://git.ipfire.org/?a=commitdiff_plain;h=993a87917c2af59efb0ee1ce43c878ca8790ba1c;p=thirdparty%2Flinux.git drm/bridge/tc358775: Fix DSI clock division for vsync delay calculation Use the same PCLK divide option (divide DSI clock to generate pixel clock) which is set to LVDS Configuration Register (LVCFG) also for a VSync delay calculation. Without this change an auxiliary variable could underflow during the calculation for some dual-link LVDS panels and then calculated VSync delay is wrong. This leads to a shifted picture on a panel. Tested-by: Jiri Vanek Signed-off-by: Jiri Vanek Reviewed-by: Vinay Simha BN Signed-off-by: Robert Foss Link: https://patchwork.freedesktop.org/patch/msgid/20220615222221.1501-3-jirivanek1@gmail.com --- diff --git a/drivers/gpu/drm/bridge/tc358775.c b/drivers/gpu/drm/bridge/tc358775.c index 8909b820db0d4..7423b1b9d9612 100644 --- a/drivers/gpu/drm/bridge/tc358775.c +++ b/drivers/gpu/drm/bridge/tc358775.c @@ -430,7 +430,7 @@ static void tc_bridge_enable(struct drm_bridge *bridge) val = TC358775_VPCTRL_MSF(1); dsiclk = mode->crtc_clock * 3 * tc->bpc / tc->num_dsi_lanes / 1000; - clkdiv = dsiclk / DIVIDE_BY_3 * tc->lvds_link; + clkdiv = dsiclk / (tc->lvds_link == DUAL_LINK ? DIVIDE_BY_6 : DIVIDE_BY_3); byteclk = dsiclk / 4; t1 = hactive * (tc->bpc * 3 / 8) / tc->num_dsi_lanes; t2 = ((100000 / clkdiv)) * (hactive + hback_porch + hsync_len + hfront_porch) / 1000;