From: Nelson Chu <nelson@rivosinc.com>
Date: Fri, 4 Jul 2025 05:42:38 +0000 (+0800)
Subject: RISC-V: Fixed dis-assembler to set correct xlen from mapping symbol
X-Git-Tag: binutils-2_45~141
X-Git-Url: http://git.ipfire.org/?a=commitdiff_plain;h=9be7e79a9672391820e41e31d372531671a3eded;p=thirdparty%2Fbinutils-gdb.git

RISC-V: Fixed dis-assembler to set correct xlen from mapping symbol
---

diff --git a/gas/testsuite/gas/riscv/option-arch-dis.d b/gas/testsuite/gas/riscv/option-arch-dis.d
index 6768fe72806..e4b603b83c6 100644
--- a/gas/testsuite/gas/riscv/option-arch-dis.d
+++ b/gas/testsuite/gas/riscv/option-arch-dis.d
@@ -22,5 +22,5 @@ Disassembly of section .text:
 [ 	]+2:[  	]+00b50533[    	]+add[        	]+a0,a0,a1
 [ 	]+6:[  	]+00302573[    	]+frcsr[        	]+a0
 [ 	]+a:[  	]+952e[    	]+add[        	]+a0,a0,a1
-[ 	]+c:[  	]+c8002573[    	]+.insn[ 	]+4, 0xc8002573
+[ 	]+c:[  	]+c8002573[    	]+rdcycleh[ 	]+a0
 #...
diff --git a/gas/testsuite/gas/riscv/option-arch.s b/gas/testsuite/gas/riscv/option-arch.s
index 4d2d261684a..a37659f2c6c 100644
--- a/gas/testsuite/gas/riscv/option-arch.s
+++ b/gas/testsuite/gas/riscv/option-arch.s
@@ -7,5 +7,5 @@ frcsr	a0
 .option pop
 .option arch, +m3p0, +d3p0, +xvendor32x3p0
 add a0, a0, a1			# func-level, rv64i_m3p0_d3p0_c_xvendor32x3p0
-.option arch, rv32i2p1c2p0	# FIXME: maybe we should adjust xlen in dis-assembler according to mappin symbols?
-rdcycleh a0			# func-level, rv32i2p1_c2p0
+.option arch, rv32i2p1c2p0
+rdcycleh a0			# func-level, rv32i2p1_c2p0, won't affcet file-level attribute
diff --git a/gas/testsuite/gas/riscv/option-norvc.d b/gas/testsuite/gas/riscv/option-norvc.d
index 107e3f98275..c2647d382b3 100644
--- a/gas/testsuite/gas/riscv/option-norvc.d
+++ b/gas/testsuite/gas/riscv/option-norvc.d
@@ -27,13 +27,13 @@ Disassembly of section .text:
 0+000 <.text>:
 [ 	]+[0-9a-f]+:[ 	]+0001[ 	]+c\.addi[ 	]+zero,0
 [ 	]+[0-9a-f]+:[ 	]+00000013[ 	]+addi[ 	]+zero,zero,0
-[ 	]+[0-9a-f]+:[ 	]+6108[ 	]+c\.ld[ 	]+a0,0\(a0\)
+[ 	]+[0-9a-f]+:[ 	]+6108[ 	]+c\.flw[ 	]+fa0,0\(a0\)
 [ 	]+[0-9a-f]+:[ 	]+00052507[ 	]+flw[ 	]+fa0,0\(a0\)
 [ 	]+[0-9a-f]+:[ 	]+2108[ 	]+c\.fld[ 	]+fa0,0\(a0\)
 [ 	]+[0-9a-f]+:[ 	]+00053507[ 	]+fld[ 	]+fa0,0\(a0\)
 [ 	]+[0-9a-f]+:[ 	]+0001[ 	]+c\.addi[ 	]+zero,0
 [ 	]+[0-9a-f]+:[ 	]+00000013[ 	]+addi[ 	]+zero,zero,0
-[ 	]+[0-9a-f]+:[ 	]+6108[ 	]+c\.ld[ 	]+a0,0\(a0\)
+[ 	]+[0-9a-f]+:[ 	]+6108[ 	]+c\.flw[ 	]+fa0,0\(a0\)
 [ 	]+[0-9a-f]+:[ 	]+00052507[ 	]+flw[ 	]+fa0,0\(a0\)
 [ 	]+[0-9a-f]+:[ 	]+2108[ 	]+c\.fld[ 	]+fa0,0\(a0\)
 [ 	]+[0-9a-f]+:[ 	]+00053507[ 	]+fld[ 	]+fa0,0\(a0\)
diff --git a/opcodes/riscv-dis.c b/opcodes/riscv-dis.c
index 9c3158a9bf9..f6af9c47a25 100644
--- a/opcodes/riscv-dis.c
+++ b/opcodes/riscv-dis.c
@@ -345,7 +345,7 @@ print_insn_args (const char *oparg, insn_t l, bfd_vma pc, disassemble_info *info
 	    case 'j':
 	      if (((l & MASK_C_ADDI) == MATCH_C_ADDI) && rd != 0)
 		maybe_print_address (pd, rd, EXTRACT_CITYPE_IMM (l), 0);
-	      if (info->mach == bfd_mach_riscv64
+	      if (pd->xlen == 64
 		  && ((l & MASK_C_ADDIW) == MATCH_C_ADDIW) && rd != 0)
 		maybe_print_address (pd, rd, EXTRACT_CITYPE_IMM (l), 1);
 	      print (info->stream, dis_style_immediate, "%d",
@@ -557,7 +557,7 @@ print_insn_args (const char *oparg, insn_t l, bfd_vma pc, disassemble_info *info
 	  if (((l & MASK_ADDI) == MATCH_ADDI && rs1 != 0)
 	      || (l & MASK_JALR) == MATCH_JALR)
 	    maybe_print_address (pd, rs1, EXTRACT_ITYPE_IMM (l), 0);
-	  if (info->mach == bfd_mach_riscv64
+	  if (pd->xlen == 64
 	      && ((l & MASK_ADDIW) == MATCH_ADDIW) && rs1 != 0)
 	    maybe_print_address (pd, rs1, EXTRACT_ITYPE_IMM (l), 1);
 	  print (info->stream, dis_style_immediate, "%d",
@@ -983,7 +983,9 @@ riscv_disassemble_insn (bfd_vma memaddr,
   if (op != NULL)
     {
       /* If XLEN is not known, get its value from the ELF class.  */
-      if (info->mach == bfd_mach_riscv64)
+      if (pd->xlen != 0)
+	;
+      else if (info->mach == bfd_mach_riscv64)
 	pd->xlen = 64;
       else if (info->mach == bfd_mach_riscv32)
 	pd->xlen = 32;