From: Davidlohr Bueso Date: Wed, 13 Nov 2024 18:33:21 +0000 (-0800) Subject: riscv/futex: Optimize atomic cmpxchg X-Git-Tag: v6.14-rc1~15^2~4 X-Git-Url: http://git.ipfire.org/?a=commitdiff_plain;h=9d0593da9459176396c1f2246efafbc80a828c7f;p=thirdparty%2Fkernel%2Flinux.git riscv/futex: Optimize atomic cmpxchg Remove redundant release/acquire barriers, optimizing the lr/sc sequence to provide conditional RCsc synchronization, per the RVWMO. Signed-off-by: Davidlohr Bueso Reviewed-by: Andrea Parri Link: https://lore.kernel.org/r/20241113183321.491113-1-dave@stgolabs.net Signed-off-by: Palmer Dabbelt --- diff --git a/arch/riscv/include/asm/futex.h b/arch/riscv/include/asm/futex.h index fc8130f995c1e..72be100afa236 100644 --- a/arch/riscv/include/asm/futex.h +++ b/arch/riscv/include/asm/futex.h @@ -85,7 +85,7 @@ futex_atomic_cmpxchg_inatomic(u32 *uval, u32 __user *uaddr, __enable_user_access(); __asm__ __volatile__ ( - "1: lr.w.aqrl %[v],%[u] \n" + "1: lr.w %[v],%[u] \n" " bne %[v],%z[ov],3f \n" "2: sc.w.aqrl %[t],%z[nv],%[u] \n" " bnez %[t],1b \n"