From: Nicholas Piggin Date: Mon, 12 May 2025 03:10:23 +0000 (+1000) Subject: ppc/xive: Explicitly zero NSR after accepting X-Git-Tag: v10.1.0-rc0~2^2~36 X-Git-Url: http://git.ipfire.org/?a=commitdiff_plain;h=9d466ab9b6f27a5d5b7a0ec5a7ad6f60e82fafda;p=thirdparty%2Fqemu.git ppc/xive: Explicitly zero NSR after accepting Have xive_tctx_accept clear NSR in one shot rather than masking out bits as they are tested, which makes it clear it's reset to 0, and does not have a partial NSR value in the register. Signed-off-by: Nicholas Piggin Reviewed-by: Glenn Miles Reviewed-by: Michael Kowal Reviewed-by: Caleb Schlossin Tested-by: Gautam Menghani Link: https://lore.kernel.org/qemu-devel/20250512031100.439842-15-npiggin@gmail.com Signed-off-by: Cédric Le Goater --- diff --git a/hw/intc/xive.c b/hw/intc/xive.c index a0a60a24f5..b35d2ec179 100644 --- a/hw/intc/xive.c +++ b/hw/intc/xive.c @@ -68,13 +68,11 @@ static uint64_t xive_tctx_accept(XiveTCTX *tctx, uint8_t ring) * If the interrupt was for a specific VP, reset the pending * buffer bit, otherwise clear the logical server indicator */ - if (regs[TM_NSR] & TM_NSR_GRP_LVL) { - regs[TM_NSR] &= ~TM_NSR_GRP_LVL; - } else { + if (!(regs[TM_NSR] & TM_NSR_GRP_LVL)) { alt_regs[TM_IPB] &= ~xive_priority_to_ipb(cppr); } - /* Drop the exception bit and any group/crowd */ + /* Clear the exception from NSR */ regs[TM_NSR] = 0; trace_xive_tctx_accept(tctx->cs->cpu_index, alt_ring,