From: Taniya Das <tdas@codeaurora.org>
Date: Mon, 11 Feb 2019 07:39:28 +0000 (+0530)
Subject: clk: qcom: gcc-qcs404: Add cfg_offset for blsp1_uart3 clock
X-Git-Tag: v5.1-rc1~34^2~8^5
X-Git-Url: http://git.ipfire.org/?a=commitdiff_plain;h=9d575719ca9b8e177391addb2855be3911dc0d93;p=thirdparty%2Fkernel%2Flinux.git

clk: qcom: gcc-qcs404: Add cfg_offset for blsp1_uart3 clock

The CFG/M/N/D registers are at an offset of 0x20 from the CMD register
only for blsp1_uart3 clock, so add it for uart3 only.

Signed-off-by: Taniya Das <tdas@codeaurora.org>
Signed-off-by: Anu Ramanathan <anur@codeaurora.org>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
Signed-off-by: Vinod Koul <vkoul@kernel.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
---

diff --git a/drivers/clk/qcom/gcc-qcs404.c b/drivers/clk/qcom/gcc-qcs404.c
index 64da032bb9edb..493e055299b48 100644
--- a/drivers/clk/qcom/gcc-qcs404.c
+++ b/drivers/clk/qcom/gcc-qcs404.c
@@ -678,6 +678,7 @@ static struct clk_rcg2 blsp1_uart3_apps_clk_src = {
 	.cmd_rcgr = 0x4014,
 	.mnd_width = 16,
 	.hid_width = 5,
+	.cfg_off = 0x20,
 	.parent_map = gcc_parent_map_0,
 	.freq_tbl = ftbl_blsp1_uart0_apps_clk_src,
 	.clkr.hw.init = &(struct clk_init_data){