From: Greg Kroah-Hartman Date: Wed, 17 Jul 2013 23:51:17 +0000 (-0700) Subject: 3.10-stable patches X-Git-Tag: v3.9.11~16 X-Git-Url: http://git.ipfire.org/?a=commitdiff_plain;h=9e5202d1aea34833061ef268bdfa7b5005235868;p=thirdparty%2Fkernel%2Fstable-queue.git 3.10-stable patches added patches: parisc-ensure-volatile-space-register-sr1-is-not-clobbered.patch parisc-fix-lmmio-mismatch-between-pat-length-and-mask-register.patch parisc-optimize-mtsp-0-sr-inline-assembly.patch slab-fix-init_lock_keys.patch --- diff --git a/queue-3.10/parisc-ensure-volatile-space-register-sr1-is-not-clobbered.patch b/queue-3.10/parisc-ensure-volatile-space-register-sr1-is-not-clobbered.patch new file mode 100644 index 00000000000..eaa31ceb3fc --- /dev/null +++ b/queue-3.10/parisc-ensure-volatile-space-register-sr1-is-not-clobbered.patch @@ -0,0 +1,63 @@ +From e8d8fc219f9a0e63e7fb927881e6f4db8e7d34df Mon Sep 17 00:00:00 2001 +From: John David Anglin +Date: Sat, 29 Jun 2013 16:42:12 -0400 +Subject: parisc: Ensure volatile space register %sr1 is not clobbered + +From: John David Anglin + +commit e8d8fc219f9a0e63e7fb927881e6f4db8e7d34df upstream. + +I still see the occasional random segv on rp3440. Looking at one of +these (a code 15), it appeared the problem must be with the cache +handling of anonymous pages. Reviewing this, I noticed that the space +register %sr1 might be being clobbered when we flush an anonymous page. + +Register %sr1 is used for TLB purges in a couple of places. These +purges are needed on PA8800 and PA8900 processors to ensure cache +consistency of flushed cache lines. + +The solution here is simply to move the %sr1 load into the TLB lock +region needed to ensure that one purge executes at a time on SMP +systems. This was already the case for one use. After a few days of +operation, I haven't had a random segv on my rp3440. + +Signed-off-by: John David Anglin +Signed-off-by: Helge Deller +Signed-off-by: Greg Kroah-Hartman + +--- + arch/parisc/include/asm/tlbflush.h | 5 +++-- + arch/parisc/kernel/cache.c | 2 +- + 2 files changed, 4 insertions(+), 3 deletions(-) + +--- a/arch/parisc/include/asm/tlbflush.h ++++ b/arch/parisc/include/asm/tlbflush.h +@@ -63,13 +63,14 @@ static inline void flush_tlb_mm(struct m + static inline void flush_tlb_page(struct vm_area_struct *vma, + unsigned long addr) + { +- unsigned long flags; ++ unsigned long flags, sid; + + /* For one page, it's not worth testing the split_tlb variable */ + + mb(); +- mtsp(vma->vm_mm->context,1); ++ sid = vma->vm_mm->context; + purge_tlb_start(flags); ++ mtsp(sid, 1); + pdtlb(addr); + pitlb(addr); + purge_tlb_end(flags); +--- a/arch/parisc/kernel/cache.c ++++ b/arch/parisc/kernel/cache.c +@@ -440,8 +440,8 @@ void __flush_tlb_range(unsigned long sid + else { + unsigned long flags; + +- mtsp(sid, 1); + purge_tlb_start(flags); ++ mtsp(sid, 1); + if (split_tlb) { + while (npages--) { + pdtlb(start); diff --git a/queue-3.10/parisc-fix-lmmio-mismatch-between-pat-length-and-mask-register.patch b/queue-3.10/parisc-fix-lmmio-mismatch-between-pat-length-and-mask-register.patch new file mode 100644 index 00000000000..e7392bfa1d7 --- /dev/null +++ b/queue-3.10/parisc-fix-lmmio-mismatch-between-pat-length-and-mask-register.patch @@ -0,0 +1,94 @@ +From dac76f1be5beaea4af9afe85fb475c73de0b8731 Mon Sep 17 00:00:00 2001 +From: Helge Deller +Date: Tue, 18 Jun 2013 23:21:25 +0200 +Subject: parisc: fix LMMIO mismatch between PAT length and MASK register + +From: Helge Deller + +commit dac76f1be5beaea4af9afe85fb475c73de0b8731 upstream. + +The LMMIO length reported by PAT and the length given by the LBA MASK +register are not consistent. This leads e.g. to a not-working ATI FireGL +card with the radeon DRM driver since the memory can't be mapped. + +Fix this by correctly adjusting the resource sizes. + +Signed-off-by: Helge Deller +Signed-off-by: Greg Kroah-Hartman + +--- + drivers/parisc/lba_pci.c | 56 +++++++++++++++++++++++++++++++++++++++++++++++ + 1 file changed, 56 insertions(+) + +--- a/drivers/parisc/lba_pci.c ++++ b/drivers/parisc/lba_pci.c +@@ -613,6 +613,54 @@ truncate_pat_collision(struct resource * + return 0; /* truncation successful */ + } + ++/* ++ * extend_lmmio_len: extend lmmio range to maximum length ++ * ++ * This is needed at least on C8000 systems to get the ATI FireGL card ++ * working. On other systems we will currently not extend the lmmio space. ++ */ ++static unsigned long ++extend_lmmio_len(unsigned long start, unsigned long end, unsigned long lba_len) ++{ ++ struct resource *tmp; ++ ++ pr_debug("LMMIO mismatch: PAT length = 0x%lx, MASK register = 0x%lx\n", ++ end - start, lba_len); ++ ++ lba_len = min(lba_len+1, 256UL*1024*1024); /* limit to 256 MB */ ++ ++ pr_debug("LBA: lmmio_space [0x%lx-0x%lx] - original\n", start, end); ++ ++ if (boot_cpu_data.cpu_type < mako) { ++ pr_info("LBA: Not a C8000 system - not extending LMMIO range.\n"); ++ return end; ++ } ++ ++ end += lba_len; ++ if (end < start) /* fix overflow */ ++ end = -1ULL; ++ ++ pr_debug("LBA: lmmio_space [0x%lx-0x%lx] - current\n", start, end); ++ ++ /* first overlap */ ++ for (tmp = iomem_resource.child; tmp; tmp = tmp->sibling) { ++ pr_debug("LBA: testing %pR\n", tmp); ++ if (tmp->start == start) ++ continue; /* ignore ourself */ ++ if (tmp->end < start) ++ continue; ++ if (tmp->start > end) ++ continue; ++ if (end >= tmp->start) ++ end = tmp->start - 1; ++ } ++ ++ pr_info("LBA: lmmio_space [0x%lx-0x%lx] - new\n", start, end); ++ ++ /* return new end */ ++ return end; ++} ++ + #else + #define truncate_pat_collision(r,n) (0) + #endif +@@ -994,6 +1042,14 @@ lba_pat_resources(struct parisc_device * + case PAT_LMMIO: + /* used to fix up pre-initialized MEM BARs */ + if (!lba_dev->hba.lmmio_space.flags) { ++ unsigned long lba_len; ++ ++ lba_len = ~READ_REG32(lba_dev->hba.base_addr ++ + LBA_LMMIO_MASK); ++ if ((p->end - p->start) != lba_len) ++ p->end = extend_lmmio_len(p->start, ++ p->end, lba_len); ++ + sprintf(lba_dev->hba.lmmio_name, + "PCI%02x LMMIO", + (int)lba_dev->hba.bus_num.start); diff --git a/queue-3.10/parisc-optimize-mtsp-0-sr-inline-assembly.patch b/queue-3.10/parisc-optimize-mtsp-0-sr-inline-assembly.patch new file mode 100644 index 00000000000..db56d205516 --- /dev/null +++ b/queue-3.10/parisc-optimize-mtsp-0-sr-inline-assembly.patch @@ -0,0 +1,37 @@ +From 92b59929825d67db575043a76651865d16873b36 Mon Sep 17 00:00:00 2001 +From: Helge Deller +Date: Sat, 29 Jun 2013 22:08:03 +0200 +Subject: parisc: optimize mtsp(0,sr) inline assembly + +From: Helge Deller + +commit 92b59929825d67db575043a76651865d16873b36 upstream. + +If the value which should be moved into a space register is zero, we can +optimize the inline assembly to become "mtsp %r0,%srX". + +Signed-off-by: Helge Deller +Signed-off-by: Greg Kroah-Hartman + +--- + arch/parisc/include/asm/special_insns.h | 9 ++++++--- + 1 file changed, 6 insertions(+), 3 deletions(-) + +--- a/arch/parisc/include/asm/special_insns.h ++++ b/arch/parisc/include/asm/special_insns.h +@@ -32,9 +32,12 @@ static inline void set_eiem(unsigned lon + cr; \ + }) + +-#define mtsp(gr, cr) \ +- __asm__ __volatile__("mtsp %0,%1" \ ++#define mtsp(val, cr) \ ++ { if (__builtin_constant_p(val) && ((val) == 0)) \ ++ __asm__ __volatile__("mtsp %%r0,%0" : : "i" (cr) : "memory"); \ ++ else \ ++ __asm__ __volatile__("mtsp %0,%1" \ + : /* no outputs */ \ +- : "r" (gr), "i" (cr) : "memory") ++ : "r" (val), "i" (cr) : "memory"); } + + #endif /* __PARISC_SPECIAL_INSNS_H */ diff --git a/queue-3.10/series b/queue-3.10/series index dde1db74048..5fa8d297508 100644 --- a/queue-3.10/series +++ b/queue-3.10/series @@ -20,3 +20,7 @@ cgroup-fix-umount-vs-cgroup_event_remove-race.patch cgroup-fix-rcu-accesses-to-task-cgroups.patch parisc-document-the-shadow-registers.patch parisc-fix-gcc-miscompilation-in-pa_memcpy.patch +slab-fix-init_lock_keys.patch +parisc-ensure-volatile-space-register-sr1-is-not-clobbered.patch +parisc-fix-lmmio-mismatch-between-pat-length-and-mask-register.patch +parisc-optimize-mtsp-0-sr-inline-assembly.patch diff --git a/queue-3.10/slab-fix-init_lock_keys.patch b/queue-3.10/slab-fix-init_lock_keys.patch new file mode 100644 index 00000000000..4edc04b99c4 --- /dev/null +++ b/queue-3.10/slab-fix-init_lock_keys.patch @@ -0,0 +1,42 @@ +From 0f8f8094d28eb53368ac09186ea6b3a324cc7d44 Mon Sep 17 00:00:00 2001 +From: Christoph Lameter +Date: Tue, 2 Jul 2013 12:12:10 -0700 +Subject: slab: fix init_lock_keys + +From: Christoph Lameter + +commit 0f8f8094d28eb53368ac09186ea6b3a324cc7d44 upstream. + +Some architectures (e.g. powerpc built with CONFIG_PPC_256K_PAGES=y +CONFIG_FORCE_MAX_ZONEORDER=11) get PAGE_SHIFT + MAX_ORDER > 26. + +In 3.10 kernels, CONFIG_LOCKDEP=y with PAGE_SHIFT + MAX_ORDER > 26 makes +init_lock_keys() dereference beyond kmalloc_caches[26]. +This leads to an unbootable system (kernel panic at initializing SLAB) +if one of kmalloc_caches[26...PAGE_SHIFT+MAX_ORDER-1] is not NULL. + +Fix this by making sure that init_lock_keys() does not dereference beyond +kmalloc_caches[26] arrays. + +Signed-off-by: Christoph Lameter +Reported-by: Tetsuo Handa +Cc: Pekka Enberg +Signed-off-by: Andrew Morton +Signed-off-by: Pekka Enberg +Signed-off-by: Greg Kroah-Hartman + +--- + mm/slab.c | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +--- a/mm/slab.c ++++ b/mm/slab.c +@@ -565,7 +565,7 @@ static void init_node_lock_keys(int q) + if (slab_state < UP) + return; + +- for (i = 1; i < PAGE_SHIFT + MAX_ORDER; i++) { ++ for (i = 1; i <= KMALLOC_SHIFT_HIGH; i++) { + struct kmem_cache_node *n; + struct kmem_cache *cache = kmalloc_caches[i]; +