From: Greg Kroah-Hartman Date: Fri, 13 Jan 2017 07:56:55 +0000 (+0100) Subject: 4.4-stable patches X-Git-Tag: v4.4.43~4 X-Git-Url: http://git.ipfire.org/?a=commitdiff_plain;h=9e87a9d543a54aaa53802216b057d88c821f3981;p=thirdparty%2Fkernel%2Fstable-queue.git 4.4-stable patches added patches: alsa-firewire-tascam-fix-to-handle-error-from-initialization-of-stream-data.patch arm-omap4-fix-bad-fallthrough-for-cpuidle.patch arm-zynq-reserve-correct-amount-of-non-dma-ram.patch hid-hid-cypress-validate-length-of-report.patch powerpc-fix-build-warning-on-32-bit-ppc.patch spi-mvebu-fix-baudrate-calculation-for-armada-variant.patch --- diff --git a/queue-4.4/alsa-firewire-tascam-fix-to-handle-error-from-initialization-of-stream-data.patch b/queue-4.4/alsa-firewire-tascam-fix-to-handle-error-from-initialization-of-stream-data.patch new file mode 100644 index 00000000000..07168eca98f --- /dev/null +++ b/queue-4.4/alsa-firewire-tascam-fix-to-handle-error-from-initialization-of-stream-data.patch @@ -0,0 +1,34 @@ +From 6a2a2f45560a9cb7bc49820883b042e44f83726c Mon Sep 17 00:00:00 2001 +From: Takashi Sakamoto +Date: Tue, 3 Jan 2017 11:58:33 +0900 +Subject: ALSA: firewire-tascam: Fix to handle error from initialization of stream data + +From: Takashi Sakamoto + +commit 6a2a2f45560a9cb7bc49820883b042e44f83726c upstream. + +This module has a bug not to return error code in a case that data +structure for transmitted packets fails to be initialized. + +This commit fixes the bug. + +Fixes: 35efa5c489de ("ALSA: firewire-tascam: add streaming functionality") +Signed-off-by: Takashi Sakamoto +Signed-off-by: Takashi Iwai +Signed-off-by: Greg Kroah-Hartman + +--- + sound/firewire/tascam/tascam-stream.c | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +--- a/sound/firewire/tascam/tascam-stream.c ++++ b/sound/firewire/tascam/tascam-stream.c +@@ -343,7 +343,7 @@ int snd_tscm_stream_init_duplex(struct s + if (err < 0) + amdtp_stream_destroy(&tscm->rx_stream); + +- return 0; ++ return err; + } + + /* At bus reset, streaming is stopped and some registers are clear. */ diff --git a/queue-4.4/arm-omap4-fix-bad-fallthrough-for-cpuidle.patch b/queue-4.4/arm-omap4-fix-bad-fallthrough-for-cpuidle.patch new file mode 100644 index 00000000000..e44078ebaa9 --- /dev/null +++ b/queue-4.4/arm-omap4-fix-bad-fallthrough-for-cpuidle.patch @@ -0,0 +1,36 @@ +From cbf2642872333547b56b8c4d943f5ed04ac9a4ee Mon Sep 17 00:00:00 2001 +From: Tony Lindgren +Date: Mon, 7 Nov 2016 16:50:11 -0700 +Subject: ARM: OMAP4+: Fix bad fallthrough for cpuidle + +From: Tony Lindgren + +commit cbf2642872333547b56b8c4d943f5ed04ac9a4ee upstream. + +We don't want to fall through to a bunch of errors for retention +if PM_OMAP4_CPU_OSWR_DISABLE is not configured for a SoC. + +Fixes: 6099dd37c669 ("ARM: OMAP5 / DRA7: Enable CPU RET on suspend") +Acked-by: Santosh Shilimkar +Signed-off-by: Tony Lindgren +Signed-off-by: Greg Kroah-Hartman + +--- + arch/arm/mach-omap2/omap-mpuss-lowpower.c | 5 ++--- + 1 file changed, 2 insertions(+), 3 deletions(-) + +--- a/arch/arm/mach-omap2/omap-mpuss-lowpower.c ++++ b/arch/arm/mach-omap2/omap-mpuss-lowpower.c +@@ -243,10 +243,9 @@ int omap4_enter_lowpower(unsigned int cp + save_state = 1; + break; + case PWRDM_POWER_RET: +- if (IS_PM44XX_ERRATUM(PM_OMAP4_CPU_OSWR_DISABLE)) { ++ if (IS_PM44XX_ERRATUM(PM_OMAP4_CPU_OSWR_DISABLE)) + save_state = 0; +- break; +- } ++ break; + default: + /* + * CPUx CSWR is invalid hardware state. Also CPUx OSWR diff --git a/queue-4.4/arm-zynq-reserve-correct-amount-of-non-dma-ram.patch b/queue-4.4/arm-zynq-reserve-correct-amount-of-non-dma-ram.patch new file mode 100644 index 00000000000..c0a6a601222 --- /dev/null +++ b/queue-4.4/arm-zynq-reserve-correct-amount-of-non-dma-ram.patch @@ -0,0 +1,37 @@ +From 7a3cc2a7b2c723aa552028f4e66841cec183756d Mon Sep 17 00:00:00 2001 +From: Kyle Roeschley +Date: Mon, 31 Oct 2016 11:26:17 -0500 +Subject: ARM: zynq: Reserve correct amount of non-DMA RAM + +From: Kyle Roeschley + +commit 7a3cc2a7b2c723aa552028f4e66841cec183756d upstream. + +On Zynq, we haven't been reserving the correct amount of DMA-incapable +RAM to keep DMA away from it (per the Zynq TRM Section 4.1, it should be +the first 512k). In older kernels, this was masked by the +memblock_reserve call in arm_memblock_init(). Now, reserve the correct +amount excplicitly rather than relying on swapper_pg_dir, which is an +address and not a size anyway. + +Fixes: 46f5b96 ("ARM: zynq: Reserve not DMAable space in front of the kernel") +Signed-off-by: Kyle Roeschley +Tested-by: Nathan Rossi +Signed-off-by: Michal Simek +Signed-off-by: Greg Kroah-Hartman + +--- + arch/arm/mach-zynq/common.c | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +--- a/arch/arm/mach-zynq/common.c ++++ b/arch/arm/mach-zynq/common.c +@@ -59,7 +59,7 @@ void __iomem *zynq_scu_base; + static void __init zynq_memory_init(void) + { + if (!__pa(PAGE_OFFSET)) +- memblock_reserve(__pa(PAGE_OFFSET), __pa(swapper_pg_dir)); ++ memblock_reserve(__pa(PAGE_OFFSET), 0x80000); + } + + static struct platform_device zynq_cpuidle_device = { diff --git a/queue-4.4/hid-hid-cypress-validate-length-of-report.patch b/queue-4.4/hid-hid-cypress-validate-length-of-report.patch new file mode 100644 index 00000000000..956b6b513d4 --- /dev/null +++ b/queue-4.4/hid-hid-cypress-validate-length-of-report.patch @@ -0,0 +1,33 @@ +From 1ebb71143758f45dc0fa76e2f48429e13b16d110 Mon Sep 17 00:00:00 2001 +From: Greg Kroah-Hartman +Date: Fri, 6 Jan 2017 15:33:36 +0100 +Subject: HID: hid-cypress: validate length of report + +From: Greg Kroah-Hartman + +commit 1ebb71143758f45dc0fa76e2f48429e13b16d110 upstream. + +Make sure we have enough of a report structure to validate before +looking at it. + +Reported-by: Benoit Camredon +Tested-by: Benoit Camredon +Signed-off-by: Greg Kroah-Hartman +Signed-off-by: Jiri Kosina + +--- + drivers/hid/hid-cypress.c | 3 +++ + 1 file changed, 3 insertions(+) + +--- a/drivers/hid/hid-cypress.c ++++ b/drivers/hid/hid-cypress.c +@@ -39,6 +39,9 @@ static __u8 *cp_report_fixup(struct hid_ + if (!(quirks & CP_RDESC_SWAPPED_MIN_MAX)) + return rdesc; + ++ if (*rsize < 4) ++ return rdesc; ++ + for (i = 0; i < *rsize - 4; i++) + if (rdesc[i] == 0x29 && rdesc[i + 2] == 0x19) { + rdesc[i] = 0x19; diff --git a/queue-4.4/powerpc-fix-build-warning-on-32-bit-ppc.patch b/queue-4.4/powerpc-fix-build-warning-on-32-bit-ppc.patch new file mode 100644 index 00000000000..04882285f7c --- /dev/null +++ b/queue-4.4/powerpc-fix-build-warning-on-32-bit-ppc.patch @@ -0,0 +1,52 @@ +From 8ae679c4bc2ea2d16d92620da8e3e9332fa4039f Mon Sep 17 00:00:00 2001 +From: Larry Finger +Date: Thu, 22 Dec 2016 21:06:53 -0600 +Subject: powerpc: Fix build warning on 32-bit PPC + +From: Larry Finger + +commit 8ae679c4bc2ea2d16d92620da8e3e9332fa4039f upstream. + +I am getting the following warning when I build kernel 4.9-git on my +PowerBook G4 with a 32-bit PPC processor: + + AS arch/powerpc/kernel/misc_32.o + arch/powerpc/kernel/misc_32.S:299:7: warning: "CONFIG_FSL_BOOKE" is not defined [-Wundef] + +This problem is evident after commit 989cea5c14be ("kbuild: prevent +lib-ksyms.o rebuilds"); however, this change in kbuild only exposes an +error that has been in the code since 2005 when this source file was +created. That was with commit 9994a33865f4 ("powerpc: Introduce +entry_{32,64}.S, misc_{32,64}.S, systbl.S"). + +The offending line does not make a lot of sense. This error does not +seem to cause any errors in the executable, thus I am not recommending +that it be applied to any stable versions. + +Thanks to Nicholas Piggin for suggesting this solution. + +Fixes: 9994a33865f4 ("powerpc: Introduce entry_{32,64}.S, misc_{32,64}.S, systbl.S") +Signed-off-by: Larry Finger +Cc: Nicholas Piggin +Cc: Benjamin Herrenschmidt +Cc: Paul Mackerras +Cc: Michael Ellerman +Cc: linuxppc-dev@lists.ozlabs.org +Signed-off-by: Linus Torvalds +Signed-off-by: Greg Kroah-Hartman + +--- + arch/powerpc/kernel/misc_32.S | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +--- a/arch/powerpc/kernel/misc_32.S ++++ b/arch/powerpc/kernel/misc_32.S +@@ -313,7 +313,7 @@ _GLOBAL(flush_instruction_cache) + lis r3, KERNELBASE@h + iccci 0,r3 + #endif +-#elif CONFIG_FSL_BOOKE ++#elif defined(CONFIG_FSL_BOOKE) + BEGIN_FTR_SECTION + mfspr r3,SPRN_L1CSR0 + ori r3,r3,L1CSR0_CFI|L1CSR0_CLFC diff --git a/queue-4.4/series b/queue-4.4/series index c9d69b8d98d..2813fdf7785 100644 --- a/queue-4.4/series +++ b/queue-4.4/series @@ -17,3 +17,9 @@ gro-use-min_t-in-skb_gro_reset_offset.patch gro-disable-frag0-optimization-on-ipv6-ext-headers.patch net-ipv4-fix-multipath-selection-with-vrf.patch net-vrf-do-not-allow-table-id-0.patch +hid-hid-cypress-validate-length-of-report.patch +alsa-firewire-tascam-fix-to-handle-error-from-initialization-of-stream-data.patch +powerpc-fix-build-warning-on-32-bit-ppc.patch +arm-zynq-reserve-correct-amount-of-non-dma-ram.patch +arm-omap4-fix-bad-fallthrough-for-cpuidle.patch +spi-mvebu-fix-baudrate-calculation-for-armada-variant.patch diff --git a/queue-4.4/spi-mvebu-fix-baudrate-calculation-for-armada-variant.patch b/queue-4.4/spi-mvebu-fix-baudrate-calculation-for-armada-variant.patch new file mode 100644 index 00000000000..990b950af7a --- /dev/null +++ b/queue-4.4/spi-mvebu-fix-baudrate-calculation-for-armada-variant.patch @@ -0,0 +1,124 @@ +From 7243e0b20729d372e97763617a7a9c89f29b33e1 Mon Sep 17 00:00:00 2001 +From: =?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?= +Date: Thu, 8 Dec 2016 17:37:08 +0100 +Subject: spi: mvebu: fix baudrate calculation for armada variant +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +From: Uwe Kleine-König + +commit 7243e0b20729d372e97763617a7a9c89f29b33e1 upstream. + +The calculation of SPR and SPPR doesn't round correctly at several +places which might result in baud rates that are too big. For example +with tclk_hz = 250000001 and target rate 25000000 it determined a +divider of 10 which is wrong. + +Instead of fixing all the corner cases replace the calculation by an +algorithm without a loop which should even be quicker to execute apart +from being correct. + +Fixes: df59fa7f4bca ("spi: orion: support armada extended baud rates") +Signed-off-by: Uwe Kleine-König +Signed-off-by: Mark Brown +Signed-off-by: Greg Kroah-Hartman + +--- + drivers/spi/spi-orion.c | 83 +++++++++++++++++++++++++++++++----------------- + 1 file changed, 54 insertions(+), 29 deletions(-) + +--- a/drivers/spi/spi-orion.c ++++ b/drivers/spi/spi-orion.c +@@ -127,37 +127,62 @@ static int orion_spi_baudrate_set(struct + tclk_hz = clk_get_rate(orion_spi->clk); + + if (devdata->typ == ARMADA_SPI) { +- unsigned int clk, spr, sppr, sppr2, err; +- unsigned int best_spr, best_sppr, best_err; +- +- best_err = speed; +- best_spr = 0; +- best_sppr = 0; +- +- /* Iterate over the valid range looking for best fit */ +- for (sppr = 0; sppr < 8; sppr++) { +- sppr2 = 0x1 << sppr; +- +- spr = tclk_hz / sppr2; +- spr = DIV_ROUND_UP(spr, speed); +- if ((spr == 0) || (spr > 15)) +- continue; +- +- clk = tclk_hz / (spr * sppr2); +- err = speed - clk; +- +- if (err < best_err) { +- best_spr = spr; +- best_sppr = sppr; +- best_err = err; +- } ++ /* ++ * Given the core_clk (tclk_hz) and the target rate (speed) we ++ * determine the best values for SPR (in [0 .. 15]) and SPPR (in ++ * [0..7]) such that ++ * ++ * core_clk / (SPR * 2 ** SPPR) ++ * ++ * is as big as possible but not bigger than speed. ++ */ ++ ++ /* best integer divider: */ ++ unsigned divider = DIV_ROUND_UP(tclk_hz, speed); ++ unsigned spr, sppr; ++ ++ if (divider < 16) { ++ /* This is the easy case, divider is less than 16 */ ++ spr = divider; ++ sppr = 0; ++ ++ } else { ++ unsigned two_pow_sppr; ++ /* ++ * Find the highest bit set in divider. This and the ++ * three next bits define SPR (apart from rounding). ++ * SPPR is then the number of zero bits that must be ++ * appended: ++ */ ++ sppr = fls(divider) - 4; ++ ++ /* ++ * As SPR only has 4 bits, we have to round divider up ++ * to the next multiple of 2 ** sppr. ++ */ ++ two_pow_sppr = 1 << sppr; ++ divider = (divider + two_pow_sppr - 1) & -two_pow_sppr; ++ ++ /* ++ * recalculate sppr as rounding up divider might have ++ * increased it enough to change the position of the ++ * highest set bit. In this case the bit that now ++ * doesn't make it into SPR is 0, so there is no need to ++ * round again. ++ */ ++ sppr = fls(divider) - 4; ++ spr = divider >> sppr; ++ ++ /* ++ * Now do range checking. SPR is constructed to have a ++ * width of 4 bits, so this is fine for sure. So we ++ * still need to check for sppr to fit into 3 bits: ++ */ ++ if (sppr > 7) ++ return -EINVAL; + } + +- if ((best_sppr == 0) && (best_spr == 0)) +- return -EINVAL; +- +- prescale = ((best_sppr & 0x6) << 5) | +- ((best_sppr & 0x1) << 4) | best_spr; ++ prescale = ((sppr & 0x6) << 5) | ((sppr & 0x1) << 4) | spr; + } else { + /* + * the supported rates are: 4,6,8...30