From: Greg Kroah-Hartman Date: Tue, 26 Mar 2019 02:30:16 +0000 (+0900) Subject: 4.14-stable patches X-Git-Tag: v4.9.166~6 X-Git-Url: http://git.ipfire.org/?a=commitdiff_plain;h=9e958b0beea9dcc67bb199e5363238fb2b353000;p=thirdparty%2Fkernel%2Fstable-queue.git 4.14-stable patches added patches: pci-designware-ep-dw_pcie_ep_set_msi-should-only-set-mmc-bits.patch pci-designware-ep-read-only-registers-need-dbi_ro_wr_en-to-be-writable.patch pci-endpoint-use-epc-s-device-in-dma_alloc_coherent-dma_free_coherent.patch power-supply-charger-manager-fix-incorrect-return-value.patch pwm-backlight-enable-disable-the-pwm-before-after-lcd-enable-toggle.patch rtc-fix-overflow-when-converting-time64_t-to-rtc_time.patch sched-cpufreq-schedutil-fix-error-path-mutex-unlock.patch scsi-ufs-fix-wrong-command-type-of-utrd-for-ufshci-v2.1.patch --- diff --git a/queue-4.14/pci-designware-ep-dw_pcie_ep_set_msi-should-only-set-mmc-bits.patch b/queue-4.14/pci-designware-ep-dw_pcie_ep_set_msi-should-only-set-mmc-bits.patch new file mode 100644 index 00000000000..63c2300294c --- /dev/null +++ b/queue-4.14/pci-designware-ep-dw_pcie_ep_set_msi-should-only-set-mmc-bits.patch @@ -0,0 +1,50 @@ +From 099a95f3591ade29da52131895a3ba9f92a0e82c Mon Sep 17 00:00:00 2001 +From: Niklas Cassel +Date: Wed, 20 Dec 2017 00:29:23 +0100 +Subject: PCI: designware-ep: dw_pcie_ep_set_msi() should only set MMC bits + +From: Niklas Cassel + +commit 099a95f3591ade29da52131895a3ba9f92a0e82c upstream. + +Previously, dw_pcie_ep_set_msi() wrote all bits in the Message Control +register, thus overwriting the PCI_MSI_FLAGS_64BIT bit. +By clearing the PCI_MSI_FLAGS_64BIT bit, we break MSI +on systems where the RC has set a 64 bit MSI address. +Fix dw_pcie_ep_set_msi() so that it only sets MMC bits. + +Tested-by: Gustavo Pimentel +Signed-off-by: Niklas Cassel +Signed-off-by: Lorenzo Pieralisi +Acked-by: Joao Pinto +Signed-off-by: Arnd Bergmann +Signed-off-by: Greg Kroah-Hartman + +--- + drivers/pci/dwc/pcie-designware-ep.c | 4 +++- + drivers/pci/dwc/pcie-designware.h | 1 + + 2 files changed, 4 insertions(+), 1 deletion(-) + +--- a/drivers/pci/dwc/pcie-designware-ep.c ++++ b/drivers/pci/dwc/pcie-designware-ep.c +@@ -214,7 +214,9 @@ static int dw_pcie_ep_set_msi(struct pci + struct dw_pcie_ep *ep = epc_get_drvdata(epc); + struct dw_pcie *pci = to_dw_pcie_from_ep(ep); + +- val = (encode_int << MSI_CAP_MMC_SHIFT); ++ val = dw_pcie_readw_dbi(pci, MSI_MESSAGE_CONTROL); ++ val &= ~MSI_CAP_MMC_MASK; ++ val |= (encode_int << MSI_CAP_MMC_SHIFT) & MSI_CAP_MMC_MASK; + dw_pcie_writew_dbi(pci, MSI_MESSAGE_CONTROL, val); + + return 0; +--- a/drivers/pci/dwc/pcie-designware.h ++++ b/drivers/pci/dwc/pcie-designware.h +@@ -99,6 +99,7 @@ + + #define MSI_MESSAGE_CONTROL 0x52 + #define MSI_CAP_MMC_SHIFT 1 ++#define MSI_CAP_MMC_MASK (7 << MSI_CAP_MMC_SHIFT) + #define MSI_CAP_MME_SHIFT 4 + #define MSI_CAP_MSI_EN_MASK 0x1 + #define MSI_CAP_MME_MASK (7 << MSI_CAP_MME_SHIFT) diff --git a/queue-4.14/pci-designware-ep-read-only-registers-need-dbi_ro_wr_en-to-be-writable.patch b/queue-4.14/pci-designware-ep-read-only-registers-need-dbi_ro_wr_en-to-be-writable.patch new file mode 100644 index 00000000000..baff45ec59b --- /dev/null +++ b/queue-4.14/pci-designware-ep-read-only-registers-need-dbi_ro_wr_en-to-be-writable.patch @@ -0,0 +1,75 @@ +From 1cab826b30c6275d479a6ab1dea1067e15dbec62 Mon Sep 17 00:00:00 2001 +From: Niklas Cassel +Date: Wed, 20 Dec 2017 00:29:24 +0100 +Subject: PCI: designware-ep: Read-only registers need DBI_RO_WR_EN to be writable + +From: Niklas Cassel + +commit 1cab826b30c6275d479a6ab1dea1067e15dbec62 upstream. + +Certain registers that pcie-designware-ep tries to write to are read-only +registers. However, these registers can become read/write if we first +enable the DBI_RO_WR_EN bit. Set/unset the DBI_RO_WR_EN bit before/after +writing these registers. + +Tested-by: Gustavo Pimentel +Signed-off-by: Niklas Cassel +Signed-off-by: Lorenzo Pieralisi +Acked-by: Joao Pinto +Signed-off-by: Arnd Bergmann +Signed-off-by: Greg Kroah-Hartman + +--- + drivers/pci/dwc/pcie-designware-ep.c | 8 ++++++++ + 1 file changed, 8 insertions(+) + +--- a/drivers/pci/dwc/pcie-designware-ep.c ++++ b/drivers/pci/dwc/pcie-designware-ep.c +@@ -35,8 +35,10 @@ static void dw_pcie_ep_reset_bar(struct + u32 reg; + + reg = PCI_BASE_ADDRESS_0 + (4 * bar); ++ dw_pcie_dbi_ro_wr_en(pci); + dw_pcie_writel_dbi2(pci, reg, 0x0); + dw_pcie_writel_dbi(pci, reg, 0x0); ++ dw_pcie_dbi_ro_wr_dis(pci); + } + + static int dw_pcie_ep_write_header(struct pci_epc *epc, +@@ -45,6 +47,7 @@ static int dw_pcie_ep_write_header(struc + struct dw_pcie_ep *ep = epc_get_drvdata(epc); + struct dw_pcie *pci = to_dw_pcie_from_ep(ep); + ++ dw_pcie_dbi_ro_wr_en(pci); + dw_pcie_writew_dbi(pci, PCI_VENDOR_ID, hdr->vendorid); + dw_pcie_writew_dbi(pci, PCI_DEVICE_ID, hdr->deviceid); + dw_pcie_writeb_dbi(pci, PCI_REVISION_ID, hdr->revid); +@@ -58,6 +61,7 @@ static int dw_pcie_ep_write_header(struc + dw_pcie_writew_dbi(pci, PCI_SUBSYSTEM_ID, hdr->subsys_id); + dw_pcie_writeb_dbi(pci, PCI_INTERRUPT_PIN, + hdr->interrupt_pin); ++ dw_pcie_dbi_ro_wr_dis(pci); + + return 0; + } +@@ -142,8 +146,10 @@ static int dw_pcie_ep_set_bar(struct pci + if (ret) + return ret; + ++ dw_pcie_dbi_ro_wr_en(pci); + dw_pcie_writel_dbi2(pci, reg, size - 1); + dw_pcie_writel_dbi(pci, reg, flags); ++ dw_pcie_dbi_ro_wr_dis(pci); + + return 0; + } +@@ -217,7 +223,9 @@ static int dw_pcie_ep_set_msi(struct pci + val = dw_pcie_readw_dbi(pci, MSI_MESSAGE_CONTROL); + val &= ~MSI_CAP_MMC_MASK; + val |= (encode_int << MSI_CAP_MMC_SHIFT) & MSI_CAP_MMC_MASK; ++ dw_pcie_dbi_ro_wr_en(pci); + dw_pcie_writew_dbi(pci, MSI_MESSAGE_CONTROL, val); ++ dw_pcie_dbi_ro_wr_dis(pci); + + return 0; + } diff --git a/queue-4.14/pci-endpoint-use-epc-s-device-in-dma_alloc_coherent-dma_free_coherent.patch b/queue-4.14/pci-endpoint-use-epc-s-device-in-dma_alloc_coherent-dma_free_coherent.patch new file mode 100644 index 00000000000..e51c309c2f8 --- /dev/null +++ b/queue-4.14/pci-endpoint-use-epc-s-device-in-dma_alloc_coherent-dma_free_coherent.patch @@ -0,0 +1,97 @@ +From b330104fa76df3eae6e199a23791fed5d35f06b4 Mon Sep 17 00:00:00 2001 +From: Kishon Vijay Abraham I +Date: Thu, 11 Jan 2018 14:00:57 +0530 +Subject: PCI: endpoint: Use EPC's device in dma_alloc_coherent()/dma_free_coherent() + +From: Kishon Vijay Abraham I + +commit b330104fa76df3eae6e199a23791fed5d35f06b4 upstream. + +After commit 723288836628 ("of: restrict DMA configuration"), +of_dma_configure() doesn't configure the coherent_dma_mask/dma_mask +of endpoint function device (since it doesn't have a DT node associated +with and hence no dma-ranges property), resulting in +dma_alloc_coherent() (used in pci_epf_alloc_space()) to fail. + +Fix it by making dma_alloc_coherent() use EPC's device for allocating +memory address. + +Link: http://lkml.kernel.org/r/64d63468-d28f-8fcd-a6f3-cf2a6401c8cb@ti.com +Signed-off-by: Kishon Vijay Abraham I +[lorenzo.pieralisi@arm.com: tweaked commit log] +Signed-off-by: Lorenzo Pieralisi +Cc: Robin Murphy +Cc: Rob Herring +Cc: Christoph Hellwig +Tested-by: Cyrille Pitchen +Tested-by: Niklas Cassel +Reviewed-by: Robin Murphy +Signed-off-by: Arnd Bergmann +Signed-off-by: Greg Kroah-Hartman + +--- + drivers/pci/endpoint/pci-epc-core.c | 10 ---------- + drivers/pci/endpoint/pci-epf-core.c | 4 ++-- + 2 files changed, 2 insertions(+), 12 deletions(-) + +--- a/drivers/pci/endpoint/pci-epc-core.c ++++ b/drivers/pci/endpoint/pci-epc-core.c +@@ -18,7 +18,6 @@ + */ + + #include +-#include + #include + #include + #include +@@ -371,7 +370,6 @@ EXPORT_SYMBOL_GPL(pci_epc_write_header); + int pci_epc_add_epf(struct pci_epc *epc, struct pci_epf *epf) + { + unsigned long flags; +- struct device *dev = epc->dev.parent; + + if (epf->epc) + return -EBUSY; +@@ -383,12 +381,6 @@ int pci_epc_add_epf(struct pci_epc *epc, + return -EINVAL; + + epf->epc = epc; +- if (dev->of_node) { +- of_dma_configure(&epf->dev, dev->of_node); +- } else { +- dma_set_coherent_mask(&epf->dev, epc->dev.coherent_dma_mask); +- epf->dev.dma_mask = epc->dev.dma_mask; +- } + + spin_lock_irqsave(&epc->lock, flags); + list_add_tail(&epf->list, &epc->pci_epf); +@@ -503,9 +495,7 @@ __pci_epc_create(struct device *dev, con + INIT_LIST_HEAD(&epc->pci_epf); + + device_initialize(&epc->dev); +- dma_set_coherent_mask(&epc->dev, dev->coherent_dma_mask); + epc->dev.class = pci_epc_class; +- epc->dev.dma_mask = dev->dma_mask; + epc->dev.parent = dev; + epc->ops = ops; + +--- a/drivers/pci/endpoint/pci-epf-core.c ++++ b/drivers/pci/endpoint/pci-epf-core.c +@@ -99,7 +99,7 @@ EXPORT_SYMBOL_GPL(pci_epf_bind); + */ + void pci_epf_free_space(struct pci_epf *epf, void *addr, enum pci_barno bar) + { +- struct device *dev = &epf->dev; ++ struct device *dev = epf->epc->dev.parent; + + if (!addr) + return; +@@ -122,7 +122,7 @@ EXPORT_SYMBOL_GPL(pci_epf_free_space); + void *pci_epf_alloc_space(struct pci_epf *epf, size_t size, enum pci_barno bar) + { + void *space; +- struct device *dev = &epf->dev; ++ struct device *dev = epf->epc->dev.parent; + dma_addr_t phys_addr; + + if (size < 128) diff --git a/queue-4.14/power-supply-charger-manager-fix-incorrect-return-value.patch b/queue-4.14/power-supply-charger-manager-fix-incorrect-return-value.patch new file mode 100644 index 00000000000..82678252108 --- /dev/null +++ b/queue-4.14/power-supply-charger-manager-fix-incorrect-return-value.patch @@ -0,0 +1,38 @@ +From f25a646fbe2051527ad9721853e892d13a99199e Mon Sep 17 00:00:00 2001 +From: Baolin Wang +Date: Fri, 16 Nov 2018 19:01:10 +0800 +Subject: power: supply: charger-manager: Fix incorrect return value + +From: Baolin Wang + +commit f25a646fbe2051527ad9721853e892d13a99199e upstream. + +Fix incorrect return value. + +Signed-off-by: Baolin Wang +Signed-off-by: Sebastian Reichel +Signed-off-by: Greg Kroah-Hartman + +--- + drivers/power/supply/charger-manager.c | 3 +-- + 1 file changed, 1 insertion(+), 2 deletions(-) + +--- a/drivers/power/supply/charger-manager.c ++++ b/drivers/power/supply/charger-manager.c +@@ -1212,7 +1212,6 @@ static int charger_extcon_init(struct ch + if (ret < 0) { + pr_info("Cannot register extcon_dev for %s(cable: %s)\n", + cable->extcon_name, cable->name); +- ret = -EINVAL; + } + + return ret; +@@ -1629,7 +1628,7 @@ static int charger_manager_probe(struct + + if (IS_ERR(desc)) { + dev_err(&pdev->dev, "No platform data (desc) found\n"); +- return -ENODEV; ++ return PTR_ERR(desc); + } + + cm = devm_kzalloc(&pdev->dev, sizeof(*cm), GFP_KERNEL); diff --git a/queue-4.14/pwm-backlight-enable-disable-the-pwm-before-after-lcd-enable-toggle.patch b/queue-4.14/pwm-backlight-enable-disable-the-pwm-before-after-lcd-enable-toggle.patch new file mode 100644 index 00000000000..a68336ca35a --- /dev/null +++ b/queue-4.14/pwm-backlight-enable-disable-the-pwm-before-after-lcd-enable-toggle.patch @@ -0,0 +1,66 @@ +From 5fb5caee92ba35a4a3baa61d45a78eb057e2c031 Mon Sep 17 00:00:00 2001 +From: Enric Balletbo i Serra +Date: Wed, 28 Mar 2018 19:03:23 +0200 +Subject: pwm-backlight: Enable/disable the PWM before/after LCD enable toggle. + +From: Enric Balletbo i Serra + +commit 5fb5caee92ba35a4a3baa61d45a78eb057e2c031 upstream. + +Before this patch the enable signal was set before the PWM signal and +vice-versa on power off. This sequence is wrong, at least, it is on +the different panels datasheets that I checked, so I inverted the sequence +to follow the specs. + +For reference the following panels have the mentioned sequence: + - N133HSE-EA1 (Innolux) + - N116BGE (Innolux) + - N156BGE-L21 (Innolux) + - B101EAN0 (Auo) + - B101AW03 (Auo) + - LTN101NT05 (Samsung) + - CLAA101WA01A (Chunghwa) + +Signed-off-by: Enric Balletbo i Serra +Acked-by: Daniel Thompson +Acked-by: Jingoo Han +Acked-by: Thierry Reding +Signed-off-by: Lee Jones +Signed-off-by: Arnd Bergmann +Signed-off-by: Greg Kroah-Hartman + +--- + drivers/video/backlight/pwm_bl.c | 9 +++++---- + 1 file changed, 5 insertions(+), 4 deletions(-) + +--- a/drivers/video/backlight/pwm_bl.c ++++ b/drivers/video/backlight/pwm_bl.c +@@ -54,10 +54,11 @@ static void pwm_backlight_power_on(struc + if (err < 0) + dev_err(pb->dev, "failed to enable power supply\n"); + ++ pwm_enable(pb->pwm); ++ + if (pb->enable_gpio) + gpiod_set_value_cansleep(pb->enable_gpio, 1); + +- pwm_enable(pb->pwm); + pb->enabled = true; + } + +@@ -66,12 +67,12 @@ static void pwm_backlight_power_off(stru + if (!pb->enabled) + return; + +- pwm_config(pb->pwm, 0, pb->period); +- pwm_disable(pb->pwm); +- + if (pb->enable_gpio) + gpiod_set_value_cansleep(pb->enable_gpio, 0); + ++ pwm_config(pb->pwm, 0, pb->period); ++ pwm_disable(pb->pwm); ++ + regulator_disable(pb->power_supply); + pb->enabled = false; + } diff --git a/queue-4.14/rtc-fix-overflow-when-converting-time64_t-to-rtc_time.patch b/queue-4.14/rtc-fix-overflow-when-converting-time64_t-to-rtc_time.patch new file mode 100644 index 00000000000..6b99e7cc1f6 --- /dev/null +++ b/queue-4.14/rtc-fix-overflow-when-converting-time64_t-to-rtc_time.patch @@ -0,0 +1,42 @@ +From 36d46cdb43efea74043e29e2a62b13e9aca31452 Mon Sep 17 00:00:00 2001 +From: Baolin Wang +Date: Mon, 25 Dec 2017 19:10:37 +0800 +Subject: rtc: Fix overflow when converting time64_t to rtc_time + +From: Baolin Wang + +commit 36d46cdb43efea74043e29e2a62b13e9aca31452 upstream. + +If we convert one large time values to rtc_time, in the original formula +'days * 86400' can be overflowed in 'unsigned int' type to make the formula +get one incorrect remain seconds value. Thus we can use div_s64_rem() +function to avoid this situation. + +Signed-off-by: Baolin Wang +Acked-by: Arnd Bergmann +Signed-off-by: Alexandre Belloni +Signed-off-by: Arnd Bergmann +Signed-off-by: Greg Kroah-Hartman + +--- + drivers/rtc/rtc-lib.c | 6 ++---- + 1 file changed, 2 insertions(+), 4 deletions(-) + +--- a/drivers/rtc/rtc-lib.c ++++ b/drivers/rtc/rtc-lib.c +@@ -52,13 +52,11 @@ EXPORT_SYMBOL(rtc_year_days); + */ + void rtc_time64_to_tm(time64_t time, struct rtc_time *tm) + { +- unsigned int month, year; +- unsigned long secs; ++ unsigned int month, year, secs; + int days; + + /* time must be positive */ +- days = div_s64(time, 86400); +- secs = time - (unsigned int) days * 86400; ++ days = div_s64_rem(time, 86400, &secs); + + /* day of the week, 1970-01-01 was a Thursday */ + tm->tm_wday = (days + 4) % 7; diff --git a/queue-4.14/sched-cpufreq-schedutil-fix-error-path-mutex-unlock.patch b/queue-4.14/sched-cpufreq-schedutil-fix-error-path-mutex-unlock.patch new file mode 100644 index 00000000000..2dea6271980 --- /dev/null +++ b/queue-4.14/sched-cpufreq-schedutil-fix-error-path-mutex-unlock.patch @@ -0,0 +1,47 @@ +From 1b5d43cfb69759d8ef8d30469cea31d0c037aed5 Mon Sep 17 00:00:00 2001 +From: Jules Maselbas +Date: Thu, 29 Mar 2018 15:43:01 +0100 +Subject: sched/cpufreq/schedutil: Fix error path mutex unlock + +From: Jules Maselbas + +commit 1b5d43cfb69759d8ef8d30469cea31d0c037aed5 upstream. + +This patch prevents the 'global_tunables_lock' mutex from being +unlocked before being locked. This mutex is not locked if the +sugov_kthread_create() function fails. + +Signed-off-by: Jules Maselbas +Acked-by: Peter Zijlstra +Cc: Chris Redpath +Cc: Dietmar Eggermann +Cc: Linus Torvalds +Cc: Mike Galbraith +Cc: Patrick Bellasi +Cc: Stephen Kyle +Cc: Thomas Gleixner +Cc: linux-kernel@vger.kernel.org +Cc: nd@arm.com +Link: http://lkml.kernel.org/r/20180329144301.38419-1-jules.maselbas@arm.com +Signed-off-by: Ingo Molnar +Signed-off-by: Arnd Bergmann +Signed-off-by: Greg Kroah-Hartman + +--- + kernel/sched/cpufreq_schedutil.c | 3 +-- + 1 file changed, 1 insertion(+), 2 deletions(-) + +--- a/kernel/sched/cpufreq_schedutil.c ++++ b/kernel/sched/cpufreq_schedutil.c +@@ -605,10 +605,9 @@ fail: + + stop_kthread: + sugov_kthread_stop(sg_policy); +- +-free_sg_policy: + mutex_unlock(&global_tunables_lock); + ++free_sg_policy: + sugov_policy_free(sg_policy); + + disable_fast_switch: diff --git a/queue-4.14/scsi-ufs-fix-wrong-command-type-of-utrd-for-ufshci-v2.1.patch b/queue-4.14/scsi-ufs-fix-wrong-command-type-of-utrd-for-ufshci-v2.1.patch new file mode 100644 index 00000000000..51e119ce43d --- /dev/null +++ b/queue-4.14/scsi-ufs-fix-wrong-command-type-of-utrd-for-ufshci-v2.1.patch @@ -0,0 +1,55 @@ +From 83dc7e3dea76b77b6bcc289eb86c5b5c145e8dff Mon Sep 17 00:00:00 2001 +From: kehuanlin +Date: Wed, 6 Sep 2017 17:58:39 +0800 +Subject: scsi: ufs: fix wrong command type of UTRD for UFSHCI v2.1 + +From: kehuanlin + +commit 83dc7e3dea76b77b6bcc289eb86c5b5c145e8dff upstream. + +Since the command type of UTRD in UFS 2.1 specification is the same with +UFS 2.0. And it assumes the future UFS specification will follow the +same definition. + +Signed-off-by: kehuanlin +Reviewed-by: Subhash Jadavani +Signed-off-by: Martin K. Petersen +Signed-off-by: Arnd Bergmann +Signed-off-by: Greg Kroah-Hartman + +--- + drivers/scsi/ufs/ufshcd.c | 14 ++++++++------ + 1 file changed, 8 insertions(+), 6 deletions(-) + +--- a/drivers/scsi/ufs/ufshcd.c ++++ b/drivers/scsi/ufs/ufshcd.c +@@ -2195,10 +2195,11 @@ static int ufshcd_comp_devman_upiu(struc + u32 upiu_flags; + int ret = 0; + +- if (hba->ufs_version == UFSHCI_VERSION_20) +- lrbp->command_type = UTP_CMD_TYPE_UFS_STORAGE; +- else ++ if ((hba->ufs_version == UFSHCI_VERSION_10) || ++ (hba->ufs_version == UFSHCI_VERSION_11)) + lrbp->command_type = UTP_CMD_TYPE_DEV_MANAGE; ++ else ++ lrbp->command_type = UTP_CMD_TYPE_UFS_STORAGE; + + ufshcd_prepare_req_desc_hdr(lrbp, &upiu_flags, DMA_NONE); + if (hba->dev_cmd.type == DEV_CMD_TYPE_QUERY) +@@ -2222,10 +2223,11 @@ static int ufshcd_comp_scsi_upiu(struct + u32 upiu_flags; + int ret = 0; + +- if (hba->ufs_version == UFSHCI_VERSION_20) +- lrbp->command_type = UTP_CMD_TYPE_UFS_STORAGE; +- else ++ if ((hba->ufs_version == UFSHCI_VERSION_10) || ++ (hba->ufs_version == UFSHCI_VERSION_11)) + lrbp->command_type = UTP_CMD_TYPE_SCSI; ++ else ++ lrbp->command_type = UTP_CMD_TYPE_UFS_STORAGE; + + if (likely(lrbp->cmd)) { + ufshcd_prepare_req_desc_hdr(lrbp, &upiu_flags, diff --git a/queue-4.14/series b/queue-4.14/series index 9680f25d1fd..cefe8ab8da8 100644 --- a/queue-4.14/series +++ b/queue-4.14/series @@ -30,3 +30,11 @@ alsa-hda-record-the-current-power-state-before-suspend-resume-calls.patch alsa-hda-enforces-runtime_resume-after-s3-and-s4-for-each-codec.patch lib-int_sqrt-optimize-small-argument.patch usb-core-only-clean-up-what-we-allocated.patch +scsi-ufs-fix-wrong-command-type-of-utrd-for-ufshci-v2.1.patch +pci-designware-ep-dw_pcie_ep_set_msi-should-only-set-mmc-bits.patch +pci-designware-ep-read-only-registers-need-dbi_ro_wr_en-to-be-writable.patch +pci-endpoint-use-epc-s-device-in-dma_alloc_coherent-dma_free_coherent.patch +rtc-fix-overflow-when-converting-time64_t-to-rtc_time.patch +sched-cpufreq-schedutil-fix-error-path-mutex-unlock.patch +pwm-backlight-enable-disable-the-pwm-before-after-lcd-enable-toggle.patch +power-supply-charger-manager-fix-incorrect-return-value.patch