From: Michal Simek <michal.simek@xilinx.com>
Date: Fri, 26 Nov 2021 14:01:25 +0000 (+0100)
Subject: arm64: zynqmp: Add fclk for clock chips
X-Git-Url: http://git.ipfire.org/?a=commitdiff_plain;h=9e9cacbe3300b3a2e6d6477aeb835c13f5247880;p=thirdparty%2Fu-boot.git

arm64: zynqmp: Add fclk for clock chips

fclk driver enables access to clock chip and provide a way to control them.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
---

diff --git a/arch/arm/dts/zynqmp-sc-vpk120-revB.dts b/arch/arm/dts/zynqmp-sc-vpk120-revB.dts
index c0ddb57c7d2..661c0a61b7d 100644
--- a/arch/arm/dts/zynqmp-sc-vpk120-revB.dts
+++ b/arch/arm/dts/zynqmp-sc-vpk120-revB.dts
@@ -12,6 +12,42 @@
 /dts-v1/;
 /plugin/;
 
+
+&{/} {
+	compatible = "xlnx,zynqmp-sc-vpk120-revB", "xlnx,zynqmp-vpk120-revB",
+		     "xlnx,zynqmp-vp120", "xlnx,zynqmp";
+
+	si570_user1_fmc_clk: si570_user1_fmc_clk {
+		status = "okay";
+		compatible = "xlnx,fclk";
+		clocks = <&user_si570_1>;
+	};
+
+	si570_ref_clk: si570_ref_clk {
+		status = "okay";
+		compatible = "xlnx,fclk";
+		clocks = <&ref_clk>;
+	};
+
+	si570_lpddr4_clk3: si570_lpddr4_clk3 {
+		status = "okay";
+		compatible = "xlnx,fclk";
+		clocks = <&lpddr4_clk3>;
+	};
+
+	si570_lpddr4_clk2: si570_lpddr4_clk2 {
+		status = "okay";
+		compatible = "xlnx,fclk";
+		clocks = <&lpddr4_clk2>;
+	};
+
+	si570_lpddr4_clk1: si570_lpddr4_clk1 {
+		status = "okay";
+		compatible = "xlnx,fclk";
+		clocks = <&lpddr4_clk1>;
+	};
+};
+
 &i2c0 {
 	#address-cells = <1>;
 	#size-cells = <0>;