From: Greg Kroah-Hartman Date: Mon, 14 Oct 2019 15:04:58 +0000 (+0200) Subject: 5.3-stable patches X-Git-Tag: v4.4.197~37 X-Git-Url: http://git.ipfire.org/?a=commitdiff_plain;h=9f0df05e3c7bf64092ecfb7afdcf6628bf62d997;p=thirdparty%2Fkernel%2Fstable-queue.git 5.3-stable patches added patches: gpio-eic-sprd-fix-the-incorrect-eic-offset-when-toggling.patch iio-adc-ad799x-fix-probe-error-handling.patch iio-adc-axp288-override-ts-pin-bias-current-for-some-models.patch iio-adc-hx711-fix-bug-in-sampling-of-data.patch iio-adc-stm32-adc-fix-a-race-when-using-several-adcs-with-dma-and-irq.patch iio-adc-stm32-adc-move-registers-definitions.patch staging-bcm2835-audio-fix-draining-behavior-regression.patch staging-fbtft-depend-on-of.patch staging-fbtft-fix-memory-leak-in-fbtft_framebuffer_alloc.patch staging-rtl8188eu-fix-highestrate-check-in-odm_arfbrefresh_8188e.patch staging-vt6655-fix-memory-leak-in-vt6655_probe.patch --- diff --git a/queue-5.3/gpio-eic-sprd-fix-the-incorrect-eic-offset-when-toggling.patch b/queue-5.3/gpio-eic-sprd-fix-the-incorrect-eic-offset-when-toggling.patch new file mode 100644 index 00000000000..90c09372c5f --- /dev/null +++ b/queue-5.3/gpio-eic-sprd-fix-the-incorrect-eic-offset-when-toggling.patch @@ -0,0 +1,42 @@ +From e91aafcb51f3c5001ae76c3ee027beb0b8506447 Mon Sep 17 00:00:00 2001 +From: Bruce Chen +Date: Mon, 16 Sep 2019 17:56:56 +0800 +Subject: gpio: eic: sprd: Fix the incorrect EIC offset when toggling + +From: Bruce Chen + +commit e91aafcb51f3c5001ae76c3ee027beb0b8506447 upstream. + +When toggling the level trigger to emulate the edge trigger, the +EIC offset is incorrect without adding the corresponding bank index, +thus fix it. + +Fixes: 7bf0d7f62282 ("gpio: eic: Add edge trigger emulation for EIC") +Cc: stable@vger.kernel.org +Signed-off-by: Bruce Chen +Signed-off-by: Baolin Wang +Signed-off-by: Bartosz Golaszewski +Signed-off-by: Greg Kroah-Hartman + +--- + drivers/gpio/gpio-eic-sprd.c | 7 ++++--- + 1 file changed, 4 insertions(+), 3 deletions(-) + +--- a/drivers/gpio/gpio-eic-sprd.c ++++ b/drivers/gpio/gpio-eic-sprd.c +@@ -530,11 +530,12 @@ static void sprd_eic_handle_one_type(str + } + + for_each_set_bit(n, ®, SPRD_EIC_PER_BANK_NR) { +- girq = irq_find_mapping(chip->irq.domain, +- bank * SPRD_EIC_PER_BANK_NR + n); ++ u32 offset = bank * SPRD_EIC_PER_BANK_NR + n; ++ ++ girq = irq_find_mapping(chip->irq.domain, offset); + + generic_handle_irq(girq); +- sprd_eic_toggle_trigger(chip, girq, n); ++ sprd_eic_toggle_trigger(chip, girq, offset); + } + } + } diff --git a/queue-5.3/iio-adc-ad799x-fix-probe-error-handling.patch b/queue-5.3/iio-adc-ad799x-fix-probe-error-handling.patch new file mode 100644 index 00000000000..1906bf4d8b0 --- /dev/null +++ b/queue-5.3/iio-adc-ad799x-fix-probe-error-handling.patch @@ -0,0 +1,39 @@ +From c62dd44901cfff12acc5792bf3d2dec20bcaf392 Mon Sep 17 00:00:00 2001 +From: Marco Felsch +Date: Tue, 17 Sep 2019 18:09:23 +0200 +Subject: iio: adc: ad799x: fix probe error handling + +From: Marco Felsch + +commit c62dd44901cfff12acc5792bf3d2dec20bcaf392 upstream. + +Since commit 0f7ddcc1bff1 ("iio:adc:ad799x: Write default config on probe +and reset alert status on probe") the error path is wrong since it +leaves the vref regulator on. Fix this by disabling both regulators. + +Fixes: 0f7ddcc1bff1 ("iio:adc:ad799x: Write default config on probe and reset alert status on probe") +Signed-off-by: Marco Felsch +Reviewed-by: Alexandru Ardelean +Cc: +Signed-off-by: Jonathan Cameron +Signed-off-by: Greg Kroah-Hartman + +--- + drivers/iio/adc/ad799x.c | 4 ++-- + 1 file changed, 2 insertions(+), 2 deletions(-) + +--- a/drivers/iio/adc/ad799x.c ++++ b/drivers/iio/adc/ad799x.c +@@ -810,10 +810,10 @@ static int ad799x_probe(struct i2c_clien + + ret = ad799x_write_config(st, st->chip_config->default_config); + if (ret < 0) +- goto error_disable_reg; ++ goto error_disable_vref; + ret = ad799x_read_config(st); + if (ret < 0) +- goto error_disable_reg; ++ goto error_disable_vref; + st->config = ret; + + ret = iio_triggered_buffer_setup(indio_dev, NULL, diff --git a/queue-5.3/iio-adc-axp288-override-ts-pin-bias-current-for-some-models.patch b/queue-5.3/iio-adc-axp288-override-ts-pin-bias-current-for-some-models.patch new file mode 100644 index 00000000000..98ef382bb72 --- /dev/null +++ b/queue-5.3/iio-adc-axp288-override-ts-pin-bias-current-for-some-models.patch @@ -0,0 +1,92 @@ +From 972917419a0ba25afbf69d5d8c9fa644d676f887 Mon Sep 17 00:00:00 2001 +From: Hans de Goede +Date: Sun, 15 Sep 2019 20:53:42 +0200 +Subject: iio: adc: axp288: Override TS pin bias current for some models +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +From: Hans de Goede + +commit 972917419a0ba25afbf69d5d8c9fa644d676f887 upstream. + +Since commit 9bcf15f75cac ("iio: adc: axp288: Fix TS-pin handling") we +preserve the bias current set by the firmware at boot. This fixes issues +we were seeing on various models, but it seems our old hardcoded 80ųA bias +current was working around a firmware bug on at least one model laptop. + +In order to both have our cake and eat it, this commit adds a dmi based +list of models where we need to override the firmware set bias current and +adds the one model we now know needs this to it: The Lenovo Ideapad 100S +(11 inch version). + +Fixes: 9bcf15f75cac ("iio: adc: axp288: Fix TS-pin handling") +BugLink: https://bugzilla.kernel.org/show_bug.cgi?id=203829 +Signed-off-by: Hans de Goede +Cc: +Signed-off-by: Jonathan Cameron +Signed-off-by: Greg Kroah-Hartman + +--- + drivers/iio/adc/axp288_adc.c | 32 ++++++++++++++++++++++++++++++++ + 1 file changed, 32 insertions(+) + +--- a/drivers/iio/adc/axp288_adc.c ++++ b/drivers/iio/adc/axp288_adc.c +@@ -7,6 +7,7 @@ + * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + */ + ++#include + #include + #include + #include +@@ -25,6 +26,11 @@ + #define AXP288_ADC_EN_MASK 0xF0 + #define AXP288_ADC_TS_ENABLE 0x01 + ++#define AXP288_ADC_TS_BIAS_MASK GENMASK(5, 4) ++#define AXP288_ADC_TS_BIAS_20UA (0 << 4) ++#define AXP288_ADC_TS_BIAS_40UA (1 << 4) ++#define AXP288_ADC_TS_BIAS_60UA (2 << 4) ++#define AXP288_ADC_TS_BIAS_80UA (3 << 4) + #define AXP288_ADC_TS_CURRENT_ON_OFF_MASK GENMASK(1, 0) + #define AXP288_ADC_TS_CURRENT_OFF (0 << 0) + #define AXP288_ADC_TS_CURRENT_ON_WHEN_CHARGING (1 << 0) +@@ -177,10 +183,36 @@ static int axp288_adc_read_raw(struct ii + return ret; + } + ++/* ++ * We rely on the machine's firmware to correctly setup the TS pin bias current ++ * at boot. This lists systems with broken fw where we need to set it ourselves. ++ */ ++static const struct dmi_system_id axp288_adc_ts_bias_override[] = { ++ { ++ /* Lenovo Ideapad 100S (11 inch) */ ++ .matches = { ++ DMI_MATCH(DMI_SYS_VENDOR, "LENOVO"), ++ DMI_MATCH(DMI_PRODUCT_VERSION, "Lenovo ideapad 100S-11IBY"), ++ }, ++ .driver_data = (void *)(uintptr_t)AXP288_ADC_TS_BIAS_80UA, ++ }, ++ {} ++}; ++ + static int axp288_adc_initialize(struct axp288_adc_info *info) + { ++ const struct dmi_system_id *bias_override; + int ret, adc_enable_val; + ++ bias_override = dmi_first_match(axp288_adc_ts_bias_override); ++ if (bias_override) { ++ ret = regmap_update_bits(info->regmap, AXP288_ADC_TS_PIN_CTRL, ++ AXP288_ADC_TS_BIAS_MASK, ++ (uintptr_t)bias_override->driver_data); ++ if (ret) ++ return ret; ++ } ++ + /* + * Determine if the TS pin is enabled and set the TS current-source + * accordingly. diff --git a/queue-5.3/iio-adc-hx711-fix-bug-in-sampling-of-data.patch b/queue-5.3/iio-adc-hx711-fix-bug-in-sampling-of-data.patch new file mode 100644 index 00000000000..62ac933e390 --- /dev/null +++ b/queue-5.3/iio-adc-hx711-fix-bug-in-sampling-of-data.patch @@ -0,0 +1,75 @@ +From 4043ecfb5fc4355a090111e14faf7945ff0fdbd5 Mon Sep 17 00:00:00 2001 +From: Andreas Klinger +Date: Mon, 9 Sep 2019 14:37:21 +0200 +Subject: iio: adc: hx711: fix bug in sampling of data + +From: Andreas Klinger + +commit 4043ecfb5fc4355a090111e14faf7945ff0fdbd5 upstream. + +Fix bug in sampling function hx711_cycle() when interrupt occures while +PD_SCK is high. If PD_SCK is high for at least 60 us power down mode of +the sensor is entered which in turn leads to a wrong measurement. + +Switch off interrupts during a PD_SCK high period and move query of DOUT +to the latest point of time which is at the end of PD_SCK low period. + +This bug exists in the driver since it's initial addition. The more +interrupts on the system the higher is the probability that it happens. + +Fixes: c3b2fdd0ea7e ("iio: adc: hx711: Add IIO driver for AVIA HX711") +Signed-off-by: Andreas Klinger +Cc: +Signed-off-by: Jonathan Cameron +Signed-off-by: Greg Kroah-Hartman + +--- + drivers/iio/adc/hx711.c | 10 +++++----- + 1 file changed, 5 insertions(+), 5 deletions(-) + +--- a/drivers/iio/adc/hx711.c ++++ b/drivers/iio/adc/hx711.c +@@ -100,14 +100,14 @@ struct hx711_data { + + static int hx711_cycle(struct hx711_data *hx711_data) + { +- int val; ++ unsigned long flags; + + /* + * if preempted for more then 60us while PD_SCK is high: + * hx711 is going in reset + * ==> measuring is false + */ +- preempt_disable(); ++ local_irq_save(flags); + gpiod_set_value(hx711_data->gpiod_pd_sck, 1); + + /* +@@ -117,7 +117,6 @@ static int hx711_cycle(struct hx711_data + */ + ndelay(hx711_data->data_ready_delay_ns); + +- val = gpiod_get_value(hx711_data->gpiod_dout); + /* + * here we are not waiting for 0.2 us as suggested by the datasheet, + * because the oscilloscope showed in a test scenario +@@ -125,7 +124,7 @@ static int hx711_cycle(struct hx711_data + * and 0.56 us for PD_SCK low on TI Sitara with 800 MHz + */ + gpiod_set_value(hx711_data->gpiod_pd_sck, 0); +- preempt_enable(); ++ local_irq_restore(flags); + + /* + * make it a square wave for addressing cases with capacitance on +@@ -133,7 +132,8 @@ static int hx711_cycle(struct hx711_data + */ + ndelay(hx711_data->data_ready_delay_ns); + +- return val; ++ /* sample as late as possible */ ++ return gpiod_get_value(hx711_data->gpiod_dout); + } + + static int hx711_read(struct hx711_data *hx711_data) diff --git a/queue-5.3/iio-adc-stm32-adc-fix-a-race-when-using-several-adcs-with-dma-and-irq.patch b/queue-5.3/iio-adc-stm32-adc-fix-a-race-when-using-several-adcs-with-dma-and-irq.patch new file mode 100644 index 00000000000..5db0dfe4ab2 --- /dev/null +++ b/queue-5.3/iio-adc-stm32-adc-fix-a-race-when-using-several-adcs-with-dma-and-irq.patch @@ -0,0 +1,130 @@ +From dcb10920179ab74caf88a6f2afadecfc2743b910 Mon Sep 17 00:00:00 2001 +From: Fabrice Gasnier +Date: Tue, 17 Sep 2019 14:38:16 +0200 +Subject: iio: adc: stm32-adc: fix a race when using several adcs with dma and irq + +From: Fabrice Gasnier + +commit dcb10920179ab74caf88a6f2afadecfc2743b910 upstream. + +End of conversion may be handled by using IRQ or DMA. There may be a +race when two conversions complete at the same time on several ADCs. +EOC can be read as 'set' for several ADCs, with: +- an ADC configured to use IRQs. EOCIE bit is set. The handler is normally + called in this case. +- an ADC configured to use DMA. EOCIE bit isn't set. EOC triggers the DMA + request instead. It's then automatically cleared by DMA read. But the + handler gets called due to status bit is temporarily set (IRQ triggered + by the other ADC). +So both EOC status bit in CSR and EOCIE control bit must be checked +before invoking the interrupt handler (e.g. call ISR only for +IRQ-enabled ADCs). + +Fixes: 2763ea0585c9 ("iio: adc: stm32: add optional dma support") + +Signed-off-by: Fabrice Gasnier +Cc: +Signed-off-by: Jonathan Cameron +Signed-off-by: Greg Kroah-Hartman + +--- + drivers/iio/adc/stm32-adc-core.c | 43 ++++++++++++++++++++++++++++++++++++--- + drivers/iio/adc/stm32-adc-core.h | 1 + 2 files changed, 41 insertions(+), 3 deletions(-) + +--- a/drivers/iio/adc/stm32-adc-core.c ++++ b/drivers/iio/adc/stm32-adc-core.c +@@ -31,6 +31,8 @@ + * @eoc1: adc1 end of conversion flag in @csr + * @eoc2: adc2 end of conversion flag in @csr + * @eoc3: adc3 end of conversion flag in @csr ++ * @ier: interrupt enable register offset for each adc ++ * @eocie_msk: end of conversion interrupt enable mask in @ier + */ + struct stm32_adc_common_regs { + u32 csr; +@@ -38,6 +40,8 @@ struct stm32_adc_common_regs { + u32 eoc1_msk; + u32 eoc2_msk; + u32 eoc3_msk; ++ u32 ier; ++ u32 eocie_msk; + }; + + struct stm32_adc_priv; +@@ -251,6 +255,8 @@ static const struct stm32_adc_common_reg + .eoc1_msk = STM32F4_EOC1, + .eoc2_msk = STM32F4_EOC2, + .eoc3_msk = STM32F4_EOC3, ++ .ier = STM32F4_ADC_CR1, ++ .eocie_msk = STM32F4_EOCIE, + }; + + /* STM32H7 common registers definitions */ +@@ -259,8 +265,24 @@ static const struct stm32_adc_common_reg + .ccr = STM32H7_ADC_CCR, + .eoc1_msk = STM32H7_EOC_MST, + .eoc2_msk = STM32H7_EOC_SLV, ++ .ier = STM32H7_ADC_IER, ++ .eocie_msk = STM32H7_EOCIE, + }; + ++static const unsigned int stm32_adc_offset[STM32_ADC_MAX_ADCS] = { ++ 0, STM32_ADC_OFFSET, STM32_ADC_OFFSET * 2, ++}; ++ ++static unsigned int stm32_adc_eoc_enabled(struct stm32_adc_priv *priv, ++ unsigned int adc) ++{ ++ u32 ier, offset = stm32_adc_offset[adc]; ++ ++ ier = readl_relaxed(priv->common.base + offset + priv->cfg->regs->ier); ++ ++ return ier & priv->cfg->regs->eocie_msk; ++} ++ + /* ADC common interrupt for all instances */ + static void stm32_adc_irq_handler(struct irq_desc *desc) + { +@@ -271,13 +293,28 @@ static void stm32_adc_irq_handler(struct + chained_irq_enter(chip, desc); + status = readl_relaxed(priv->common.base + priv->cfg->regs->csr); + +- if (status & priv->cfg->regs->eoc1_msk) ++ /* ++ * End of conversion may be handled by using IRQ or DMA. There may be a ++ * race here when two conversions complete at the same time on several ++ * ADCs. EOC may be read 'set' for several ADCs, with: ++ * - an ADC configured to use DMA (EOC triggers the DMA request, and ++ * is then automatically cleared by DR read in hardware) ++ * - an ADC configured to use IRQs (EOCIE bit is set. The handler must ++ * be called in this case) ++ * So both EOC status bit in CSR and EOCIE control bit must be checked ++ * before invoking the interrupt handler (e.g. call ISR only for ++ * IRQ-enabled ADCs). ++ */ ++ if (status & priv->cfg->regs->eoc1_msk && ++ stm32_adc_eoc_enabled(priv, 0)) + generic_handle_irq(irq_find_mapping(priv->domain, 0)); + +- if (status & priv->cfg->regs->eoc2_msk) ++ if (status & priv->cfg->regs->eoc2_msk && ++ stm32_adc_eoc_enabled(priv, 1)) + generic_handle_irq(irq_find_mapping(priv->domain, 1)); + +- if (status & priv->cfg->regs->eoc3_msk) ++ if (status & priv->cfg->regs->eoc3_msk && ++ stm32_adc_eoc_enabled(priv, 2)) + generic_handle_irq(irq_find_mapping(priv->domain, 2)); + + chained_irq_exit(chip, desc); +--- a/drivers/iio/adc/stm32-adc-core.h ++++ b/drivers/iio/adc/stm32-adc-core.h +@@ -25,6 +25,7 @@ + * -------------------------------------------------------- + */ + #define STM32_ADC_MAX_ADCS 3 ++#define STM32_ADC_OFFSET 0x100 + #define STM32_ADCX_COMN_OFFSET 0x300 + + /* STM32F4 - Registers for each ADC instance */ diff --git a/queue-5.3/iio-adc-stm32-adc-move-registers-definitions.patch b/queue-5.3/iio-adc-stm32-adc-move-registers-definitions.patch new file mode 100644 index 00000000000..b2732d9b947 --- /dev/null +++ b/queue-5.3/iio-adc-stm32-adc-move-registers-definitions.patch @@ -0,0 +1,328 @@ +From 31922f62bb527d749b99dbc776e514bcba29b7fe Mon Sep 17 00:00:00 2001 +From: Fabrice Gasnier +Date: Tue, 17 Sep 2019 14:38:15 +0200 +Subject: iio: adc: stm32-adc: move registers definitions + +From: Fabrice Gasnier + +commit 31922f62bb527d749b99dbc776e514bcba29b7fe upstream. + +Move STM32 ADC registers definitions to common header. +This is precursor patch to: +- iio: adc: stm32-adc: fix a race when using several adcs with dma and irq + +It keeps registers definitions as a whole block, to ease readability and +allow simple access path to EOC bits (readl) in stm32-adc-core driver. + +Fixes: 2763ea0585c9 ("iio: adc: stm32: add optional dma support") + +Signed-off-by: Fabrice Gasnier +Cc: +Signed-off-by: Jonathan Cameron +Signed-off-by: Greg Kroah-Hartman + +--- + drivers/iio/adc/stm32-adc-core.c | 27 ------- + drivers/iio/adc/stm32-adc-core.h | 136 +++++++++++++++++++++++++++++++++++++++ + drivers/iio/adc/stm32-adc.c | 109 ------------------------------- + 3 files changed, 136 insertions(+), 136 deletions(-) + +--- a/drivers/iio/adc/stm32-adc-core.c ++++ b/drivers/iio/adc/stm32-adc-core.c +@@ -22,33 +22,6 @@ + + #include "stm32-adc-core.h" + +-/* STM32F4 - common registers for all ADC instances: 1, 2 & 3 */ +-#define STM32F4_ADC_CSR (STM32_ADCX_COMN_OFFSET + 0x00) +-#define STM32F4_ADC_CCR (STM32_ADCX_COMN_OFFSET + 0x04) +- +-/* STM32F4_ADC_CSR - bit fields */ +-#define STM32F4_EOC3 BIT(17) +-#define STM32F4_EOC2 BIT(9) +-#define STM32F4_EOC1 BIT(1) +- +-/* STM32F4_ADC_CCR - bit fields */ +-#define STM32F4_ADC_ADCPRE_SHIFT 16 +-#define STM32F4_ADC_ADCPRE_MASK GENMASK(17, 16) +- +-/* STM32H7 - common registers for all ADC instances */ +-#define STM32H7_ADC_CSR (STM32_ADCX_COMN_OFFSET + 0x00) +-#define STM32H7_ADC_CCR (STM32_ADCX_COMN_OFFSET + 0x08) +- +-/* STM32H7_ADC_CSR - bit fields */ +-#define STM32H7_EOC_SLV BIT(18) +-#define STM32H7_EOC_MST BIT(2) +- +-/* STM32H7_ADC_CCR - bit fields */ +-#define STM32H7_PRESC_SHIFT 18 +-#define STM32H7_PRESC_MASK GENMASK(21, 18) +-#define STM32H7_CKMODE_SHIFT 16 +-#define STM32H7_CKMODE_MASK GENMASK(17, 16) +- + #define STM32_ADC_CORE_SLEEP_DELAY_MS 2000 + + /** +--- a/drivers/iio/adc/stm32-adc-core.h ++++ b/drivers/iio/adc/stm32-adc-core.h +@@ -27,6 +27,142 @@ + #define STM32_ADC_MAX_ADCS 3 + #define STM32_ADCX_COMN_OFFSET 0x300 + ++/* STM32F4 - Registers for each ADC instance */ ++#define STM32F4_ADC_SR 0x00 ++#define STM32F4_ADC_CR1 0x04 ++#define STM32F4_ADC_CR2 0x08 ++#define STM32F4_ADC_SMPR1 0x0C ++#define STM32F4_ADC_SMPR2 0x10 ++#define STM32F4_ADC_HTR 0x24 ++#define STM32F4_ADC_LTR 0x28 ++#define STM32F4_ADC_SQR1 0x2C ++#define STM32F4_ADC_SQR2 0x30 ++#define STM32F4_ADC_SQR3 0x34 ++#define STM32F4_ADC_JSQR 0x38 ++#define STM32F4_ADC_JDR1 0x3C ++#define STM32F4_ADC_JDR2 0x40 ++#define STM32F4_ADC_JDR3 0x44 ++#define STM32F4_ADC_JDR4 0x48 ++#define STM32F4_ADC_DR 0x4C ++ ++/* STM32F4 - common registers for all ADC instances: 1, 2 & 3 */ ++#define STM32F4_ADC_CSR (STM32_ADCX_COMN_OFFSET + 0x00) ++#define STM32F4_ADC_CCR (STM32_ADCX_COMN_OFFSET + 0x04) ++ ++/* STM32F4_ADC_SR - bit fields */ ++#define STM32F4_STRT BIT(4) ++#define STM32F4_EOC BIT(1) ++ ++/* STM32F4_ADC_CR1 - bit fields */ ++#define STM32F4_RES_SHIFT 24 ++#define STM32F4_RES_MASK GENMASK(25, 24) ++#define STM32F4_SCAN BIT(8) ++#define STM32F4_EOCIE BIT(5) ++ ++/* STM32F4_ADC_CR2 - bit fields */ ++#define STM32F4_SWSTART BIT(30) ++#define STM32F4_EXTEN_SHIFT 28 ++#define STM32F4_EXTEN_MASK GENMASK(29, 28) ++#define STM32F4_EXTSEL_SHIFT 24 ++#define STM32F4_EXTSEL_MASK GENMASK(27, 24) ++#define STM32F4_EOCS BIT(10) ++#define STM32F4_DDS BIT(9) ++#define STM32F4_DMA BIT(8) ++#define STM32F4_ADON BIT(0) ++ ++/* STM32F4_ADC_CSR - bit fields */ ++#define STM32F4_EOC3 BIT(17) ++#define STM32F4_EOC2 BIT(9) ++#define STM32F4_EOC1 BIT(1) ++ ++/* STM32F4_ADC_CCR - bit fields */ ++#define STM32F4_ADC_ADCPRE_SHIFT 16 ++#define STM32F4_ADC_ADCPRE_MASK GENMASK(17, 16) ++ ++/* STM32H7 - Registers for each ADC instance */ ++#define STM32H7_ADC_ISR 0x00 ++#define STM32H7_ADC_IER 0x04 ++#define STM32H7_ADC_CR 0x08 ++#define STM32H7_ADC_CFGR 0x0C ++#define STM32H7_ADC_SMPR1 0x14 ++#define STM32H7_ADC_SMPR2 0x18 ++#define STM32H7_ADC_PCSEL 0x1C ++#define STM32H7_ADC_SQR1 0x30 ++#define STM32H7_ADC_SQR2 0x34 ++#define STM32H7_ADC_SQR3 0x38 ++#define STM32H7_ADC_SQR4 0x3C ++#define STM32H7_ADC_DR 0x40 ++#define STM32H7_ADC_DIFSEL 0xC0 ++#define STM32H7_ADC_CALFACT 0xC4 ++#define STM32H7_ADC_CALFACT2 0xC8 ++ ++/* STM32H7 - common registers for all ADC instances */ ++#define STM32H7_ADC_CSR (STM32_ADCX_COMN_OFFSET + 0x00) ++#define STM32H7_ADC_CCR (STM32_ADCX_COMN_OFFSET + 0x08) ++ ++/* STM32H7_ADC_ISR - bit fields */ ++#define STM32MP1_VREGREADY BIT(12) ++#define STM32H7_EOC BIT(2) ++#define STM32H7_ADRDY BIT(0) ++ ++/* STM32H7_ADC_IER - bit fields */ ++#define STM32H7_EOCIE STM32H7_EOC ++ ++/* STM32H7_ADC_CR - bit fields */ ++#define STM32H7_ADCAL BIT(31) ++#define STM32H7_ADCALDIF BIT(30) ++#define STM32H7_DEEPPWD BIT(29) ++#define STM32H7_ADVREGEN BIT(28) ++#define STM32H7_LINCALRDYW6 BIT(27) ++#define STM32H7_LINCALRDYW5 BIT(26) ++#define STM32H7_LINCALRDYW4 BIT(25) ++#define STM32H7_LINCALRDYW3 BIT(24) ++#define STM32H7_LINCALRDYW2 BIT(23) ++#define STM32H7_LINCALRDYW1 BIT(22) ++#define STM32H7_ADCALLIN BIT(16) ++#define STM32H7_BOOST BIT(8) ++#define STM32H7_ADSTP BIT(4) ++#define STM32H7_ADSTART BIT(2) ++#define STM32H7_ADDIS BIT(1) ++#define STM32H7_ADEN BIT(0) ++ ++/* STM32H7_ADC_CFGR bit fields */ ++#define STM32H7_EXTEN_SHIFT 10 ++#define STM32H7_EXTEN_MASK GENMASK(11, 10) ++#define STM32H7_EXTSEL_SHIFT 5 ++#define STM32H7_EXTSEL_MASK GENMASK(9, 5) ++#define STM32H7_RES_SHIFT 2 ++#define STM32H7_RES_MASK GENMASK(4, 2) ++#define STM32H7_DMNGT_SHIFT 0 ++#define STM32H7_DMNGT_MASK GENMASK(1, 0) ++ ++enum stm32h7_adc_dmngt { ++ STM32H7_DMNGT_DR_ONLY, /* Regular data in DR only */ ++ STM32H7_DMNGT_DMA_ONESHOT, /* DMA one shot mode */ ++ STM32H7_DMNGT_DFSDM, /* DFSDM mode */ ++ STM32H7_DMNGT_DMA_CIRC, /* DMA circular mode */ ++}; ++ ++/* STM32H7_ADC_CALFACT - bit fields */ ++#define STM32H7_CALFACT_D_SHIFT 16 ++#define STM32H7_CALFACT_D_MASK GENMASK(26, 16) ++#define STM32H7_CALFACT_S_SHIFT 0 ++#define STM32H7_CALFACT_S_MASK GENMASK(10, 0) ++ ++/* STM32H7_ADC_CALFACT2 - bit fields */ ++#define STM32H7_LINCALFACT_SHIFT 0 ++#define STM32H7_LINCALFACT_MASK GENMASK(29, 0) ++ ++/* STM32H7_ADC_CSR - bit fields */ ++#define STM32H7_EOC_SLV BIT(18) ++#define STM32H7_EOC_MST BIT(2) ++ ++/* STM32H7_ADC_CCR - bit fields */ ++#define STM32H7_PRESC_SHIFT 18 ++#define STM32H7_PRESC_MASK GENMASK(21, 18) ++#define STM32H7_CKMODE_SHIFT 16 ++#define STM32H7_CKMODE_MASK GENMASK(17, 16) ++ + /** + * struct stm32_adc_common - stm32 ADC driver common data (for all instances) + * @base: control registers base cpu addr +--- a/drivers/iio/adc/stm32-adc.c ++++ b/drivers/iio/adc/stm32-adc.c +@@ -28,115 +28,6 @@ + + #include "stm32-adc-core.h" + +-/* STM32F4 - Registers for each ADC instance */ +-#define STM32F4_ADC_SR 0x00 +-#define STM32F4_ADC_CR1 0x04 +-#define STM32F4_ADC_CR2 0x08 +-#define STM32F4_ADC_SMPR1 0x0C +-#define STM32F4_ADC_SMPR2 0x10 +-#define STM32F4_ADC_HTR 0x24 +-#define STM32F4_ADC_LTR 0x28 +-#define STM32F4_ADC_SQR1 0x2C +-#define STM32F4_ADC_SQR2 0x30 +-#define STM32F4_ADC_SQR3 0x34 +-#define STM32F4_ADC_JSQR 0x38 +-#define STM32F4_ADC_JDR1 0x3C +-#define STM32F4_ADC_JDR2 0x40 +-#define STM32F4_ADC_JDR3 0x44 +-#define STM32F4_ADC_JDR4 0x48 +-#define STM32F4_ADC_DR 0x4C +- +-/* STM32F4_ADC_SR - bit fields */ +-#define STM32F4_STRT BIT(4) +-#define STM32F4_EOC BIT(1) +- +-/* STM32F4_ADC_CR1 - bit fields */ +-#define STM32F4_RES_SHIFT 24 +-#define STM32F4_RES_MASK GENMASK(25, 24) +-#define STM32F4_SCAN BIT(8) +-#define STM32F4_EOCIE BIT(5) +- +-/* STM32F4_ADC_CR2 - bit fields */ +-#define STM32F4_SWSTART BIT(30) +-#define STM32F4_EXTEN_SHIFT 28 +-#define STM32F4_EXTEN_MASK GENMASK(29, 28) +-#define STM32F4_EXTSEL_SHIFT 24 +-#define STM32F4_EXTSEL_MASK GENMASK(27, 24) +-#define STM32F4_EOCS BIT(10) +-#define STM32F4_DDS BIT(9) +-#define STM32F4_DMA BIT(8) +-#define STM32F4_ADON BIT(0) +- +-/* STM32H7 - Registers for each ADC instance */ +-#define STM32H7_ADC_ISR 0x00 +-#define STM32H7_ADC_IER 0x04 +-#define STM32H7_ADC_CR 0x08 +-#define STM32H7_ADC_CFGR 0x0C +-#define STM32H7_ADC_SMPR1 0x14 +-#define STM32H7_ADC_SMPR2 0x18 +-#define STM32H7_ADC_PCSEL 0x1C +-#define STM32H7_ADC_SQR1 0x30 +-#define STM32H7_ADC_SQR2 0x34 +-#define STM32H7_ADC_SQR3 0x38 +-#define STM32H7_ADC_SQR4 0x3C +-#define STM32H7_ADC_DR 0x40 +-#define STM32H7_ADC_DIFSEL 0xC0 +-#define STM32H7_ADC_CALFACT 0xC4 +-#define STM32H7_ADC_CALFACT2 0xC8 +- +-/* STM32H7_ADC_ISR - bit fields */ +-#define STM32MP1_VREGREADY BIT(12) +-#define STM32H7_EOC BIT(2) +-#define STM32H7_ADRDY BIT(0) +- +-/* STM32H7_ADC_IER - bit fields */ +-#define STM32H7_EOCIE STM32H7_EOC +- +-/* STM32H7_ADC_CR - bit fields */ +-#define STM32H7_ADCAL BIT(31) +-#define STM32H7_ADCALDIF BIT(30) +-#define STM32H7_DEEPPWD BIT(29) +-#define STM32H7_ADVREGEN BIT(28) +-#define STM32H7_LINCALRDYW6 BIT(27) +-#define STM32H7_LINCALRDYW5 BIT(26) +-#define STM32H7_LINCALRDYW4 BIT(25) +-#define STM32H7_LINCALRDYW3 BIT(24) +-#define STM32H7_LINCALRDYW2 BIT(23) +-#define STM32H7_LINCALRDYW1 BIT(22) +-#define STM32H7_ADCALLIN BIT(16) +-#define STM32H7_BOOST BIT(8) +-#define STM32H7_ADSTP BIT(4) +-#define STM32H7_ADSTART BIT(2) +-#define STM32H7_ADDIS BIT(1) +-#define STM32H7_ADEN BIT(0) +- +-/* STM32H7_ADC_CFGR bit fields */ +-#define STM32H7_EXTEN_SHIFT 10 +-#define STM32H7_EXTEN_MASK GENMASK(11, 10) +-#define STM32H7_EXTSEL_SHIFT 5 +-#define STM32H7_EXTSEL_MASK GENMASK(9, 5) +-#define STM32H7_RES_SHIFT 2 +-#define STM32H7_RES_MASK GENMASK(4, 2) +-#define STM32H7_DMNGT_SHIFT 0 +-#define STM32H7_DMNGT_MASK GENMASK(1, 0) +- +-enum stm32h7_adc_dmngt { +- STM32H7_DMNGT_DR_ONLY, /* Regular data in DR only */ +- STM32H7_DMNGT_DMA_ONESHOT, /* DMA one shot mode */ +- STM32H7_DMNGT_DFSDM, /* DFSDM mode */ +- STM32H7_DMNGT_DMA_CIRC, /* DMA circular mode */ +-}; +- +-/* STM32H7_ADC_CALFACT - bit fields */ +-#define STM32H7_CALFACT_D_SHIFT 16 +-#define STM32H7_CALFACT_D_MASK GENMASK(26, 16) +-#define STM32H7_CALFACT_S_SHIFT 0 +-#define STM32H7_CALFACT_S_MASK GENMASK(10, 0) +- +-/* STM32H7_ADC_CALFACT2 - bit fields */ +-#define STM32H7_LINCALFACT_SHIFT 0 +-#define STM32H7_LINCALFACT_MASK GENMASK(29, 0) +- + /* Number of linear calibration shadow registers / LINCALRDYW control bits */ + #define STM32H7_LINCALFACT_NUM 6 + diff --git a/queue-5.3/series b/queue-5.3/series index fcf97672417..bed52f23130 100644 --- a/queue-5.3/series +++ b/queue-5.3/series @@ -43,3 +43,14 @@ usb-legousbtower-fix-open-after-failed-reset-request.patch usb-legousbtower-fix-use-after-free-on-release.patch mei-me-add-comet-point-lake-lp-device-ids.patch mei-avoid-fw-version-request-on-ibex-peak-and-earlier.patch +gpio-eic-sprd-fix-the-incorrect-eic-offset-when-toggling.patch +staging-fbtft-depend-on-of.patch +staging-bcm2835-audio-fix-draining-behavior-regression.patch +staging-fbtft-fix-memory-leak-in-fbtft_framebuffer_alloc.patch +staging-rtl8188eu-fix-highestrate-check-in-odm_arfbrefresh_8188e.patch +staging-vt6655-fix-memory-leak-in-vt6655_probe.patch +iio-adc-hx711-fix-bug-in-sampling-of-data.patch +iio-adc-ad799x-fix-probe-error-handling.patch +iio-adc-axp288-override-ts-pin-bias-current-for-some-models.patch +iio-adc-stm32-adc-move-registers-definitions.patch +iio-adc-stm32-adc-fix-a-race-when-using-several-adcs-with-dma-and-irq.patch diff --git a/queue-5.3/staging-bcm2835-audio-fix-draining-behavior-regression.patch b/queue-5.3/staging-bcm2835-audio-fix-draining-behavior-regression.patch new file mode 100644 index 00000000000..e08d96a39aa --- /dev/null +++ b/queue-5.3/staging-bcm2835-audio-fix-draining-behavior-regression.patch @@ -0,0 +1,63 @@ +From 2eed19b99c8e95ff87afe6c140ed895c3fac5937 Mon Sep 17 00:00:00 2001 +From: Takashi Iwai +Date: Sat, 14 Sep 2019 17:24:05 +0200 +Subject: staging: bcm2835-audio: Fix draining behavior regression + +From: Takashi Iwai + +commit 2eed19b99c8e95ff87afe6c140ed895c3fac5937 upstream. + +The PCM draining behavior got broken since the recent refactoring, and +this turned out to be the incorrect expectation of the firmware +behavior regarding "draining". While I expected the "drain" flag at +the stop operation would do processing the queued samples, it seems +rather dropping the samples. + +As a quick fix, just drop the SNDRV_PCM_INFO_DRAIN_TRIGGER flag, so +that the driver uses the normal PCM draining procedure. Also, put +some caution comment to the function for future readers not to fall +into the same pitfall. + +Fixes: d7ca3a71545b ("staging: bcm2835-audio: Operate non-atomic PCM ops") +BugLink: https://github.com/raspberrypi/linux/issues/2983 +Cc: stable@vger.kernel.org +Signed-off-by: Takashi Iwai +Acked-by: Stefan Wahren +Link: https://lore.kernel.org/r/20190914152405.7416-1-tiwai@suse.de +Signed-off-by: Greg Kroah-Hartman + +--- + drivers/staging/vc04_services/bcm2835-audio/bcm2835-pcm.c | 4 ++-- + drivers/staging/vc04_services/bcm2835-audio/bcm2835-vchiq.c | 1 + + 2 files changed, 3 insertions(+), 2 deletions(-) + +--- a/drivers/staging/vc04_services/bcm2835-audio/bcm2835-pcm.c ++++ b/drivers/staging/vc04_services/bcm2835-audio/bcm2835-pcm.c +@@ -12,7 +12,7 @@ + static const struct snd_pcm_hardware snd_bcm2835_playback_hw = { + .info = (SNDRV_PCM_INFO_INTERLEAVED | SNDRV_PCM_INFO_BLOCK_TRANSFER | + SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_MMAP_VALID | +- SNDRV_PCM_INFO_DRAIN_TRIGGER | SNDRV_PCM_INFO_SYNC_APPLPTR), ++ SNDRV_PCM_INFO_SYNC_APPLPTR), + .formats = SNDRV_PCM_FMTBIT_U8 | SNDRV_PCM_FMTBIT_S16_LE, + .rates = SNDRV_PCM_RATE_CONTINUOUS | SNDRV_PCM_RATE_8000_48000, + .rate_min = 8000, +@@ -29,7 +29,7 @@ static const struct snd_pcm_hardware snd + static const struct snd_pcm_hardware snd_bcm2835_playback_spdif_hw = { + .info = (SNDRV_PCM_INFO_INTERLEAVED | SNDRV_PCM_INFO_BLOCK_TRANSFER | + SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_MMAP_VALID | +- SNDRV_PCM_INFO_DRAIN_TRIGGER | SNDRV_PCM_INFO_SYNC_APPLPTR), ++ SNDRV_PCM_INFO_SYNC_APPLPTR), + .formats = SNDRV_PCM_FMTBIT_S16_LE, + .rates = SNDRV_PCM_RATE_CONTINUOUS | SNDRV_PCM_RATE_44100 | + SNDRV_PCM_RATE_48000, +--- a/drivers/staging/vc04_services/bcm2835-audio/bcm2835-vchiq.c ++++ b/drivers/staging/vc04_services/bcm2835-audio/bcm2835-vchiq.c +@@ -289,6 +289,7 @@ int bcm2835_audio_stop(struct bcm2835_al + VC_AUDIO_MSG_TYPE_STOP, false); + } + ++/* FIXME: this doesn't seem working as expected for "draining" */ + int bcm2835_audio_drain(struct bcm2835_alsa_stream *alsa_stream) + { + struct vc_audio_msg m = { diff --git a/queue-5.3/staging-fbtft-depend-on-of.patch b/queue-5.3/staging-fbtft-depend-on-of.patch new file mode 100644 index 00000000000..11d3762c4d8 --- /dev/null +++ b/queue-5.3/staging-fbtft-depend-on-of.patch @@ -0,0 +1,40 @@ +From 63f2b1677fba11c5bd02089f25c13421948905f5 Mon Sep 17 00:00:00 2001 +From: =?UTF-8?q?Noralf=20Tr=C3=B8nnes?= +Date: Tue, 17 Sep 2019 19:18:41 +0200 +Subject: staging/fbtft: Depend on OF +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +From: Noralf Trønnes + +commit 63f2b1677fba11c5bd02089f25c13421948905f5 upstream. + +Commit c440eee1a7a1 ("Staging: fbtft: Switch to the gpio descriptor +interface") removed setting gpios via platform data. This means that +fbtft will now only work with Device Tree so set the dependency. + +This also prevents a NULL pointer deref on non-DT platform because +fbtftops.request_gpios is not set in that case anymore. + +Fixes: c440eee1a7a1 ("Staging: fbtft: Switch to the gpio descriptor interface") +Cc: stable +Signed-off-by: Noralf Trønnes +Link: https://lore.kernel.org/r/20190917171843.10334-1-noralf@tronnes.org +Signed-off-by: Greg Kroah-Hartman + +--- + drivers/staging/fbtft/Kconfig | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +--- a/drivers/staging/fbtft/Kconfig ++++ b/drivers/staging/fbtft/Kconfig +@@ -1,7 +1,7 @@ + # SPDX-License-Identifier: GPL-2.0 + menuconfig FB_TFT + tristate "Support for small TFT LCD display modules" +- depends on FB && SPI ++ depends on FB && SPI && OF + depends on GPIOLIB || COMPILE_TEST + select FB_SYS_FILLRECT + select FB_SYS_COPYAREA diff --git a/queue-5.3/staging-fbtft-fix-memory-leak-in-fbtft_framebuffer_alloc.patch b/queue-5.3/staging-fbtft-fix-memory-leak-in-fbtft_framebuffer_alloc.patch new file mode 100644 index 00000000000..a58d581ffec --- /dev/null +++ b/queue-5.3/staging-fbtft-fix-memory-leak-in-fbtft_framebuffer_alloc.patch @@ -0,0 +1,55 @@ +From 5bdea6060618cfcf1459dca137e89aee038ac8b9 Mon Sep 17 00:00:00 2001 +From: Navid Emamdoost +Date: Sun, 29 Sep 2019 22:09:45 -0500 +Subject: Staging: fbtft: fix memory leak in fbtft_framebuffer_alloc + +From: Navid Emamdoost + +commit 5bdea6060618cfcf1459dca137e89aee038ac8b9 upstream. + +In fbtft_framebuffer_alloc the error handling path should take care of +releasing frame buffer after it is allocated via framebuffer_alloc, too. +Therefore, in two failure cases the goto destination is changed to +address this issue. + +Fixes: c296d5f9957c ("staging: fbtft: core support") +Signed-off-by: Navid Emamdoost +Reviewed-by: Dan Carpenter +Cc: stable +Link: https://lore.kernel.org/r/20190930030949.28615-1-navid.emamdoost@gmail.com +Signed-off-by: Greg Kroah-Hartman + +--- + drivers/staging/fbtft/fbtft-core.c | 7 +++++-- + 1 file changed, 5 insertions(+), 2 deletions(-) + +--- a/drivers/staging/fbtft/fbtft-core.c ++++ b/drivers/staging/fbtft/fbtft-core.c +@@ -714,7 +714,7 @@ struct fb_info *fbtft_framebuffer_alloc( + if (par->gamma.curves && gamma) { + if (fbtft_gamma_parse_str(par, par->gamma.curves, gamma, + strlen(gamma))) +- goto alloc_fail; ++ goto release_framebuf; + } + + /* Transmit buffer */ +@@ -731,7 +731,7 @@ struct fb_info *fbtft_framebuffer_alloc( + if (txbuflen > 0) { + txbuf = devm_kzalloc(par->info->device, txbuflen, GFP_KERNEL); + if (!txbuf) +- goto alloc_fail; ++ goto release_framebuf; + par->txbuf.buf = txbuf; + par->txbuf.len = txbuflen; + } +@@ -753,6 +753,9 @@ struct fb_info *fbtft_framebuffer_alloc( + + return info; + ++release_framebuf: ++ framebuffer_release(info); ++ + alloc_fail: + vfree(vmem); + diff --git a/queue-5.3/staging-rtl8188eu-fix-highestrate-check-in-odm_arfbrefresh_8188e.patch b/queue-5.3/staging-rtl8188eu-fix-highestrate-check-in-odm_arfbrefresh_8188e.patch new file mode 100644 index 00000000000..1d399e7e893 --- /dev/null +++ b/queue-5.3/staging-rtl8188eu-fix-highestrate-check-in-odm_arfbrefresh_8188e.patch @@ -0,0 +1,36 @@ +From 22d67a01d8d89552b989c9651419824bb4111200 Mon Sep 17 00:00:00 2001 +From: Denis Efremov +Date: Thu, 26 Sep 2019 10:31:38 +0300 +Subject: staging: rtl8188eu: fix HighestRate check in odm_ARFBRefresh_8188E() + +From: Denis Efremov + +commit 22d67a01d8d89552b989c9651419824bb4111200 upstream. + +It's incorrect to compare HighestRate with 0x0b twice in the following +manner "if (HighestRate > 0x0b) ... else if (HighestRate > 0x0b) ...". The +"else if" branch is constantly false. The second comparision should be +with 0x03 according to the max_rate_idx in ODM_RAInfo_Init(). + +Cc: Michael Straube +Cc: stable@vger.kernel.org +Signed-off-by: Denis Efremov +Acked-by: Larry Finger +Link: https://lore.kernel.org/r/20190926073138.12109-1-efremov@linux.com +Signed-off-by: Greg Kroah-Hartman + +--- + drivers/staging/rtl8188eu/hal/hal8188e_rate_adaptive.c | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +--- a/drivers/staging/rtl8188eu/hal/hal8188e_rate_adaptive.c ++++ b/drivers/staging/rtl8188eu/hal/hal8188e_rate_adaptive.c +@@ -409,7 +409,7 @@ static int odm_ARFBRefresh_8188E(struct + pRaInfo->PTModeSS = 3; + else if (pRaInfo->HighestRate > 0x0b) + pRaInfo->PTModeSS = 2; +- else if (pRaInfo->HighestRate > 0x0b) ++ else if (pRaInfo->HighestRate > 0x03) + pRaInfo->PTModeSS = 1; + else + pRaInfo->PTModeSS = 0; diff --git a/queue-5.3/staging-vt6655-fix-memory-leak-in-vt6655_probe.patch b/queue-5.3/staging-vt6655-fix-memory-leak-in-vt6655_probe.patch new file mode 100644 index 00000000000..9d34d8dbf53 --- /dev/null +++ b/queue-5.3/staging-vt6655-fix-memory-leak-in-vt6655_probe.patch @@ -0,0 +1,37 @@ +From 80b15db5e1e9c3300de299b2d43d1aafb593e6ac Mon Sep 17 00:00:00 2001 +From: Navid Emamdoost +Date: Fri, 4 Oct 2019 15:03:15 -0500 +Subject: staging: vt6655: Fix memory leak in vt6655_probe + +From: Navid Emamdoost + +commit 80b15db5e1e9c3300de299b2d43d1aafb593e6ac upstream. + +In vt6655_probe, if vnt_init() fails the cleanup code needs to be called +like other error handling cases. The call to device_free_info() is +added. + +Fixes: 67013f2c0e58 ("staging: vt6655: mac80211 conversion add main mac80211 functions") +Signed-off-by: Navid Emamdoost +Cc: stable +Link: https://lore.kernel.org/r/20191004200319.22394-1-navid.emamdoost@gmail.com +Signed-off-by: Greg Kroah-Hartman + +--- + drivers/staging/vt6655/device_main.c | 4 +++- + 1 file changed, 3 insertions(+), 1 deletion(-) + +--- a/drivers/staging/vt6655/device_main.c ++++ b/drivers/staging/vt6655/device_main.c +@@ -1748,8 +1748,10 @@ vt6655_probe(struct pci_dev *pcid, const + + priv->hw->max_signal = 100; + +- if (vnt_init(priv)) ++ if (vnt_init(priv)) { ++ device_free_info(priv); + return -ENODEV; ++ } + + device_print_info(priv); + pci_set_drvdata(pcid, priv);