From: Philippe Mathieu-Daudé Date: Sun, 14 Feb 2021 17:58:33 +0000 (+0100) Subject: target/mips: Make cpu_HI/LO registers public X-Git-Tag: v6.0.0-rc0~71^2~20 X-Git-Url: http://git.ipfire.org/?a=commitdiff_plain;h=9f5f7691dee18b0a0d6e0d8e291b7c12da85de17;p=thirdparty%2Fqemu.git target/mips: Make cpu_HI/LO registers public We will access the cpu_HI/LO registers outside of translate.c. Make them publicly accessible. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson Message-Id: <20210214175912.732946-4-f4bug@amsat.org> Signed-off-by: Philippe Mathieu-Daudé --- diff --git a/target/mips/translate.c b/target/mips/translate.c index a6e835809aa..c20f630b7e7 100644 --- a/target/mips/translate.c +++ b/target/mips/translate.c @@ -2179,7 +2179,7 @@ enum { /* global register indices */ TCGv cpu_gpr[32], cpu_PC; -static TCGv cpu_HI[MIPS_DSP_ACC], cpu_LO[MIPS_DSP_ACC]; +TCGv cpu_HI[MIPS_DSP_ACC], cpu_LO[MIPS_DSP_ACC]; static TCGv cpu_dspctrl, btarget; TCGv bcond; static TCGv cpu_lladdr, cpu_llval; diff --git a/target/mips/translate.h b/target/mips/translate.h index f47b5f2c8d0..2a1d8f570bb 100644 --- a/target/mips/translate.h +++ b/target/mips/translate.h @@ -145,6 +145,7 @@ bool gen_lsa(DisasContext *ctx, int rd, int rt, int rs, int sa); bool gen_dlsa(DisasContext *ctx, int rd, int rt, int rs, int sa); extern TCGv cpu_gpr[32], cpu_PC; +extern TCGv cpu_HI[MIPS_DSP_ACC], cpu_LO[MIPS_DSP_ACC]; extern TCGv_i32 fpu_fcr0, fpu_fcr31; extern TCGv_i64 fpu_f64[32]; extern TCGv bcond;