From: Greg Kroah-Hartman Date: Sun, 14 Feb 2021 08:18:36 +0000 (+0100) Subject: 5.4-stable patches X-Git-Tag: v5.4.99~43 X-Git-Url: http://git.ipfire.org/?a=commitdiff_plain;h=a00c30a6364c88a6b00b19e2684b1403edebdbc5;p=thirdparty%2Fkernel%2Fstable-queue.git 5.4-stable patches added patches: arm-xen-don-t-probe-xenbus-as-part-of-an-early-initcall.patch cgroup-fix-psi-monitor-for-root-cgroup.patch gpio-ep93xx-fix-bug_on-port-f-usage.patch gpio-ep93xx-fix-single-irqchip-with-multi-gpiochips.patch tracing-check-length-before-giving-out-the-filter-buffer.patch tracing-do-not-count-ftrace-events-in-top-level-enable-output.patch --- diff --git a/queue-5.4/arm-xen-don-t-probe-xenbus-as-part-of-an-early-initcall.patch b/queue-5.4/arm-xen-don-t-probe-xenbus-as-part-of-an-early-initcall.patch new file mode 100644 index 00000000000..7bf98d7b1de --- /dev/null +++ b/queue-5.4/arm-xen-don-t-probe-xenbus-as-part-of-an-early-initcall.patch @@ -0,0 +1,82 @@ +From c4295ab0b485b8bc50d2264bcae2acd06f25caaf Mon Sep 17 00:00:00 2001 +From: Julien Grall +Date: Wed, 10 Feb 2021 17:06:54 +0000 +Subject: arm/xen: Don't probe xenbus as part of an early initcall + +From: Julien Grall + +commit c4295ab0b485b8bc50d2264bcae2acd06f25caaf upstream. + +After Commit 3499ba8198cad ("xen: Fix event channel callback via +INTX/GSI"), xenbus_probe() will be called too early on Arm. This will +recent to a guest hang during boot. + +If the hang wasn't there, we would have ended up to call +xenbus_probe() twice (the second time is in xenbus_probe_initcall()). + +We don't need to initialize xenbus_probe() early for Arm guest. +Therefore, the call in xen_guest_init() is now removed. + +After this change, there is no more external caller for xenbus_probe(). +So the function is turned to a static one. Interestingly there were two +prototypes for it. + +Cc: stable@vger.kernel.org +Fixes: 3499ba8198cad ("xen: Fix event channel callback via INTX/GSI") +Reported-by: Ian Jackson +Signed-off-by: Julien Grall +Reviewed-by: David Woodhouse +Reviewed-by: Stefano Stabellini +Link: https://lore.kernel.org/r/20210210170654.5377-1-julien@xen.org +Signed-off-by: Juergen Gross +Signed-off-by: Greg Kroah-Hartman +--- + arch/arm/xen/enlighten.c | 2 -- + drivers/xen/xenbus/xenbus.h | 1 - + drivers/xen/xenbus/xenbus_probe.c | 2 +- + include/xen/xenbus.h | 2 -- + 4 files changed, 1 insertion(+), 6 deletions(-) + +--- a/arch/arm/xen/enlighten.c ++++ b/arch/arm/xen/enlighten.c +@@ -370,8 +370,6 @@ static int __init xen_guest_init(void) + return -ENOMEM; + } + gnttab_init(); +- if (!xen_initial_domain()) +- xenbus_probe(); + + /* + * Making sure board specific code will not set up ops for +--- a/drivers/xen/xenbus/xenbus.h ++++ b/drivers/xen/xenbus/xenbus.h +@@ -115,7 +115,6 @@ int xenbus_probe_node(struct xen_bus_typ + const char *type, + const char *nodename); + int xenbus_probe_devices(struct xen_bus_type *bus); +-void xenbus_probe(void); + + void xenbus_dev_changed(const char *node, struct xen_bus_type *bus); + +--- a/drivers/xen/xenbus/xenbus_probe.c ++++ b/drivers/xen/xenbus/xenbus_probe.c +@@ -683,7 +683,7 @@ void unregister_xenstore_notifier(struct + } + EXPORT_SYMBOL_GPL(unregister_xenstore_notifier); + +-void xenbus_probe(void) ++static void xenbus_probe(void) + { + xenstored_ready = 1; + +--- a/include/xen/xenbus.h ++++ b/include/xen/xenbus.h +@@ -187,8 +187,6 @@ void xs_suspend_cancel(void); + + struct work_struct; + +-void xenbus_probe(void); +- + #define XENBUS_IS_ERR_READ(str) ({ \ + if (!IS_ERR(str) && strlen(str) == 0) { \ + kfree(str); \ diff --git a/queue-5.4/cgroup-fix-psi-monitor-for-root-cgroup.patch b/queue-5.4/cgroup-fix-psi-monitor-for-root-cgroup.patch new file mode 100644 index 00000000000..478f33b5628 --- /dev/null +++ b/queue-5.4/cgroup-fix-psi-monitor-for-root-cgroup.patch @@ -0,0 +1,51 @@ +From 385aac1519417b89cb91b77c22e4ca21db563cd0 Mon Sep 17 00:00:00 2001 +From: Odin Ugedal +Date: Sat, 16 Jan 2021 18:36:33 +0100 +Subject: cgroup: fix psi monitor for root cgroup + +From: Odin Ugedal + +commit 385aac1519417b89cb91b77c22e4ca21db563cd0 upstream. + +Fix NULL pointer dereference when adding new psi monitor to the root +cgroup. PSI files for root cgroup was introduced in df5ba5be742 by using +system wide psi struct when reading, but file write/monitor was not +properly fixed. Since the PSI config for the root cgroup isn't +initialized, the current implementation tries to lock a NULL ptr, +resulting in a crash. + +Can be triggered by running this as root: +$ tee /sys/fs/cgroup/cpu.pressure <<< "some 10000 1000000" + +Signed-off-by: Odin Ugedal +Reviewed-by: Suren Baghdasaryan +Acked-by: Dan Schatzberg +Fixes: df5ba5be7425 ("kernel/sched/psi.c: expose pressure metrics on root cgroup") +Acked-by: Johannes Weiner +Cc: stable@vger.kernel.org # 5.2+ +Signed-off-by: Tejun Heo +Signed-off-by: Greg Kroah-Hartman +--- + kernel/cgroup/cgroup.c | 4 +++- + 1 file changed, 3 insertions(+), 1 deletion(-) + +--- a/kernel/cgroup/cgroup.c ++++ b/kernel/cgroup/cgroup.c +@@ -3627,6 +3627,7 @@ static ssize_t cgroup_pressure_write(str + { + struct psi_trigger *new; + struct cgroup *cgrp; ++ struct psi_group *psi; + + cgrp = cgroup_kn_lock_live(of->kn, false); + if (!cgrp) +@@ -3635,7 +3636,8 @@ static ssize_t cgroup_pressure_write(str + cgroup_get(cgrp); + cgroup_kn_unlock(of->kn); + +- new = psi_trigger_create(&cgrp->psi, buf, nbytes, res); ++ psi = cgroup_ino(cgrp) == 1 ? &psi_system : &cgrp->psi; ++ new = psi_trigger_create(psi, buf, nbytes, res); + if (IS_ERR(new)) { + cgroup_put(cgrp); + return PTR_ERR(new); diff --git a/queue-5.4/gpio-ep93xx-fix-bug_on-port-f-usage.patch b/queue-5.4/gpio-ep93xx-fix-bug_on-port-f-usage.patch new file mode 100644 index 00000000000..72cd4fc2b49 --- /dev/null +++ b/queue-5.4/gpio-ep93xx-fix-bug_on-port-f-usage.patch @@ -0,0 +1,399 @@ +From 8b81a7ab8055d01d827ef66374b126eeac3bd108 Mon Sep 17 00:00:00 2001 +From: Nikita Shubin +Date: Tue, 9 Feb 2021 16:31:04 +0300 +Subject: gpio: ep93xx: fix BUG_ON port F usage + +From: Nikita Shubin + +commit 8b81a7ab8055d01d827ef66374b126eeac3bd108 upstream. + +Two index spaces and ep93xx_gpio_port are confusing. + +Instead add a separate struct to store necessary data and remove +ep93xx_gpio_port. + +- add struct to store IRQ related data for each IRQ capable chip +- replace offset array with defined offsets +- add IRQ registers offset for each IRQ capable chip into + ep93xx_gpio_banks + +------------[ cut here ]------------ +kernel BUG at drivers/gpio/gpio-ep93xx.c:64! +---[ end trace 3f6544e133e9f5ae ]--- + +Fixes: fd935fc421e74 ("gpio: ep93xx: Do not pingpong irq numbers") +Cc: +Reviewed-by: Alexander Sverdlin +Tested-by: Alexander Sverdlin +Signed-off-by: Nikita Shubin +Signed-off-by: Bartosz Golaszewski +Signed-off-by: Greg Kroah-Hartman +--- + drivers/gpio/gpio-ep93xx.c | 186 +++++++++++++++++++++++---------------------- + 1 file changed, 99 insertions(+), 87 deletions(-) + +--- a/drivers/gpio/gpio-ep93xx.c ++++ b/drivers/gpio/gpio-ep93xx.c +@@ -25,6 +25,9 @@ + /* Maximum value for gpio line identifiers */ + #define EP93XX_GPIO_LINE_MAX 63 + ++/* Number of GPIO chips in EP93XX */ ++#define EP93XX_GPIO_CHIP_NUM 8 ++ + /* Maximum value for irq capable line identifiers */ + #define EP93XX_GPIO_LINE_MAX_IRQ 23 + +@@ -34,74 +37,74 @@ + */ + #define EP93XX_GPIO_F_IRQ_BASE 80 + ++struct ep93xx_gpio_irq_chip { ++ u8 irq_offset; ++ u8 int_unmasked; ++ u8 int_enabled; ++ u8 int_type1; ++ u8 int_type2; ++ u8 int_debounce; ++}; ++ ++struct ep93xx_gpio_chip { ++ struct gpio_chip gc; ++ struct ep93xx_gpio_irq_chip *eic; ++}; ++ + struct ep93xx_gpio { + void __iomem *base; +- struct gpio_chip gc[8]; ++ struct ep93xx_gpio_chip gc[EP93XX_GPIO_CHIP_NUM]; + }; + +-/************************************************************************* +- * Interrupt handling for EP93xx on-chip GPIOs +- *************************************************************************/ +-static unsigned char gpio_int_unmasked[3]; +-static unsigned char gpio_int_enabled[3]; +-static unsigned char gpio_int_type1[3]; +-static unsigned char gpio_int_type2[3]; +-static unsigned char gpio_int_debounce[3]; ++#define to_ep93xx_gpio_chip(x) container_of(x, struct ep93xx_gpio_chip, gc) + +-/* Port ordering is: A B F */ +-static const u8 int_type1_register_offset[3] = { 0x90, 0xac, 0x4c }; +-static const u8 int_type2_register_offset[3] = { 0x94, 0xb0, 0x50 }; +-static const u8 eoi_register_offset[3] = { 0x98, 0xb4, 0x54 }; +-static const u8 int_en_register_offset[3] = { 0x9c, 0xb8, 0x58 }; +-static const u8 int_debounce_register_offset[3] = { 0xa8, 0xc4, 0x64 }; +- +-static void ep93xx_gpio_update_int_params(struct ep93xx_gpio *epg, unsigned port) ++static struct ep93xx_gpio_irq_chip *to_ep93xx_gpio_irq_chip(struct gpio_chip *gc) + { +- BUG_ON(port > 2); +- +- writeb_relaxed(0, epg->base + int_en_register_offset[port]); ++ struct ep93xx_gpio_chip *egc = to_ep93xx_gpio_chip(gc); + +- writeb_relaxed(gpio_int_type2[port], +- epg->base + int_type2_register_offset[port]); +- +- writeb_relaxed(gpio_int_type1[port], +- epg->base + int_type1_register_offset[port]); +- +- writeb(gpio_int_unmasked[port] & gpio_int_enabled[port], +- epg->base + int_en_register_offset[port]); ++ return egc->eic; + } + +-static int ep93xx_gpio_port(struct gpio_chip *gc) +-{ +- struct ep93xx_gpio *epg = gpiochip_get_data(gc); +- int port = 0; ++/************************************************************************* ++ * Interrupt handling for EP93xx on-chip GPIOs ++ *************************************************************************/ ++#define EP93XX_INT_TYPE1_OFFSET 0x00 ++#define EP93XX_INT_TYPE2_OFFSET 0x04 ++#define EP93XX_INT_EOI_OFFSET 0x08 ++#define EP93XX_INT_EN_OFFSET 0x0c ++#define EP93XX_INT_STATUS_OFFSET 0x10 ++#define EP93XX_INT_RAW_STATUS_OFFSET 0x14 ++#define EP93XX_INT_DEBOUNCE_OFFSET 0x18 ++ ++static void ep93xx_gpio_update_int_params(struct ep93xx_gpio *epg, ++ struct ep93xx_gpio_irq_chip *eic) ++{ ++ writeb_relaxed(0, epg->base + eic->irq_offset + EP93XX_INT_EN_OFFSET); + +- while (port < ARRAY_SIZE(epg->gc) && gc != &epg->gc[port]) +- port++; ++ writeb_relaxed(eic->int_type2, ++ epg->base + eic->irq_offset + EP93XX_INT_TYPE2_OFFSET); + +- /* This should not happen but is there as a last safeguard */ +- if (port == ARRAY_SIZE(epg->gc)) { +- pr_crit("can't find the GPIO port\n"); +- return 0; +- } ++ writeb_relaxed(eic->int_type1, ++ epg->base + eic->irq_offset + EP93XX_INT_TYPE1_OFFSET); + +- return port; ++ writeb_relaxed(eic->int_unmasked & eic->int_enabled, ++ epg->base + eic->irq_offset + EP93XX_INT_EN_OFFSET); + } + + static void ep93xx_gpio_int_debounce(struct gpio_chip *gc, + unsigned int offset, bool enable) + { + struct ep93xx_gpio *epg = gpiochip_get_data(gc); +- int port = ep93xx_gpio_port(gc); ++ struct ep93xx_gpio_irq_chip *eic = to_ep93xx_gpio_irq_chip(gc); + int port_mask = BIT(offset); + + if (enable) +- gpio_int_debounce[port] |= port_mask; ++ eic->int_debounce |= port_mask; + else +- gpio_int_debounce[port] &= ~port_mask; ++ eic->int_debounce &= ~port_mask; + +- writeb(gpio_int_debounce[port], +- epg->base + int_debounce_register_offset[port]); ++ writeb(eic->int_debounce, ++ epg->base + eic->irq_offset + EP93XX_INT_DEBOUNCE_OFFSET); + } + + static void ep93xx_gpio_ab_irq_handler(struct irq_desc *desc) +@@ -122,12 +125,12 @@ static void ep93xx_gpio_ab_irq_handler(s + */ + stat = readb(epg->base + EP93XX_GPIO_A_INT_STATUS); + for_each_set_bit(offset, &stat, 8) +- generic_handle_irq(irq_find_mapping(epg->gc[0].irq.domain, ++ generic_handle_irq(irq_find_mapping(epg->gc[0].gc.irq.domain, + offset)); + + stat = readb(epg->base + EP93XX_GPIO_B_INT_STATUS); + for_each_set_bit(offset, &stat, 8) +- generic_handle_irq(irq_find_mapping(epg->gc[1].irq.domain, ++ generic_handle_irq(irq_find_mapping(epg->gc[1].gc.irq.domain, + offset)); + + chained_irq_exit(irqchip, desc); +@@ -153,52 +156,52 @@ static void ep93xx_gpio_f_irq_handler(st + static void ep93xx_gpio_irq_ack(struct irq_data *d) + { + struct gpio_chip *gc = irq_data_get_irq_chip_data(d); ++ struct ep93xx_gpio_irq_chip *eic = to_ep93xx_gpio_irq_chip(gc); + struct ep93xx_gpio *epg = gpiochip_get_data(gc); +- int port = ep93xx_gpio_port(gc); + int port_mask = BIT(d->irq & 7); + + if (irqd_get_trigger_type(d) == IRQ_TYPE_EDGE_BOTH) { +- gpio_int_type2[port] ^= port_mask; /* switch edge direction */ +- ep93xx_gpio_update_int_params(epg, port); ++ eic->int_type2 ^= port_mask; /* switch edge direction */ ++ ep93xx_gpio_update_int_params(epg, eic); + } + +- writeb(port_mask, epg->base + eoi_register_offset[port]); ++ writeb(port_mask, epg->base + eic->irq_offset + EP93XX_INT_EOI_OFFSET); + } + + static void ep93xx_gpio_irq_mask_ack(struct irq_data *d) + { + struct gpio_chip *gc = irq_data_get_irq_chip_data(d); ++ struct ep93xx_gpio_irq_chip *eic = to_ep93xx_gpio_irq_chip(gc); + struct ep93xx_gpio *epg = gpiochip_get_data(gc); +- int port = ep93xx_gpio_port(gc); + int port_mask = BIT(d->irq & 7); + + if (irqd_get_trigger_type(d) == IRQ_TYPE_EDGE_BOTH) +- gpio_int_type2[port] ^= port_mask; /* switch edge direction */ ++ eic->int_type2 ^= port_mask; /* switch edge direction */ + +- gpio_int_unmasked[port] &= ~port_mask; +- ep93xx_gpio_update_int_params(epg, port); ++ eic->int_unmasked &= ~port_mask; ++ ep93xx_gpio_update_int_params(epg, eic); + +- writeb(port_mask, epg->base + eoi_register_offset[port]); ++ writeb(port_mask, epg->base + eic->irq_offset + EP93XX_INT_EOI_OFFSET); + } + + static void ep93xx_gpio_irq_mask(struct irq_data *d) + { + struct gpio_chip *gc = irq_data_get_irq_chip_data(d); ++ struct ep93xx_gpio_irq_chip *eic = to_ep93xx_gpio_irq_chip(gc); + struct ep93xx_gpio *epg = gpiochip_get_data(gc); +- int port = ep93xx_gpio_port(gc); + +- gpio_int_unmasked[port] &= ~BIT(d->irq & 7); +- ep93xx_gpio_update_int_params(epg, port); ++ eic->int_unmasked &= ~BIT(d->irq & 7); ++ ep93xx_gpio_update_int_params(epg, eic); + } + + static void ep93xx_gpio_irq_unmask(struct irq_data *d) + { + struct gpio_chip *gc = irq_data_get_irq_chip_data(d); ++ struct ep93xx_gpio_irq_chip *eic = to_ep93xx_gpio_irq_chip(gc); + struct ep93xx_gpio *epg = gpiochip_get_data(gc); +- int port = ep93xx_gpio_port(gc); + +- gpio_int_unmasked[port] |= BIT(d->irq & 7); +- ep93xx_gpio_update_int_params(epg, port); ++ eic->int_unmasked |= BIT(d->irq & 7); ++ ep93xx_gpio_update_int_params(epg, eic); + } + + /* +@@ -209,8 +212,8 @@ static void ep93xx_gpio_irq_unmask(struc + static int ep93xx_gpio_irq_type(struct irq_data *d, unsigned int type) + { + struct gpio_chip *gc = irq_data_get_irq_chip_data(d); ++ struct ep93xx_gpio_irq_chip *eic = to_ep93xx_gpio_irq_chip(gc); + struct ep93xx_gpio *epg = gpiochip_get_data(gc); +- int port = ep93xx_gpio_port(gc); + int offset = d->irq & 7; + int port_mask = BIT(offset); + irq_flow_handler_t handler; +@@ -219,32 +222,32 @@ static int ep93xx_gpio_irq_type(struct i + + switch (type) { + case IRQ_TYPE_EDGE_RISING: +- gpio_int_type1[port] |= port_mask; +- gpio_int_type2[port] |= port_mask; ++ eic->int_type1 |= port_mask; ++ eic->int_type2 |= port_mask; + handler = handle_edge_irq; + break; + case IRQ_TYPE_EDGE_FALLING: +- gpio_int_type1[port] |= port_mask; +- gpio_int_type2[port] &= ~port_mask; ++ eic->int_type1 |= port_mask; ++ eic->int_type2 &= ~port_mask; + handler = handle_edge_irq; + break; + case IRQ_TYPE_LEVEL_HIGH: +- gpio_int_type1[port] &= ~port_mask; +- gpio_int_type2[port] |= port_mask; ++ eic->int_type1 &= ~port_mask; ++ eic->int_type2 |= port_mask; + handler = handle_level_irq; + break; + case IRQ_TYPE_LEVEL_LOW: +- gpio_int_type1[port] &= ~port_mask; +- gpio_int_type2[port] &= ~port_mask; ++ eic->int_type1 &= ~port_mask; ++ eic->int_type2 &= ~port_mask; + handler = handle_level_irq; + break; + case IRQ_TYPE_EDGE_BOTH: +- gpio_int_type1[port] |= port_mask; ++ eic->int_type1 |= port_mask; + /* set initial polarity based on current input level */ + if (gc->get(gc, offset)) +- gpio_int_type2[port] &= ~port_mask; /* falling */ ++ eic->int_type2 &= ~port_mask; /* falling */ + else +- gpio_int_type2[port] |= port_mask; /* rising */ ++ eic->int_type2 |= port_mask; /* rising */ + handler = handle_edge_irq; + break; + default: +@@ -253,9 +256,9 @@ static int ep93xx_gpio_irq_type(struct i + + irq_set_handler_locked(d, handler); + +- gpio_int_enabled[port] |= port_mask; ++ eic->int_enabled |= port_mask; + +- ep93xx_gpio_update_int_params(epg, port); ++ ep93xx_gpio_update_int_params(epg, eic); + + return 0; + } +@@ -276,17 +279,19 @@ struct ep93xx_gpio_bank { + const char *label; + int data; + int dir; ++ int irq; + int base; + bool has_irq; + bool has_hierarchical_irq; + unsigned int irq_base; + }; + +-#define EP93XX_GPIO_BANK(_label, _data, _dir, _base, _has_irq, _has_hier, _irq_base) \ ++#define EP93XX_GPIO_BANK(_label, _data, _dir, _irq, _base, _has_irq, _has_hier, _irq_base) \ + { \ + .label = _label, \ + .data = _data, \ + .dir = _dir, \ ++ .irq = _irq, \ + .base = _base, \ + .has_irq = _has_irq, \ + .has_hierarchical_irq = _has_hier, \ +@@ -295,16 +300,16 @@ struct ep93xx_gpio_bank { + + static struct ep93xx_gpio_bank ep93xx_gpio_banks[] = { + /* Bank A has 8 IRQs */ +- EP93XX_GPIO_BANK("A", 0x00, 0x10, 0, true, false, 64), ++ EP93XX_GPIO_BANK("A", 0x00, 0x10, 0x90, 0, true, false, 64), + /* Bank B has 8 IRQs */ +- EP93XX_GPIO_BANK("B", 0x04, 0x14, 8, true, false, 72), +- EP93XX_GPIO_BANK("C", 0x08, 0x18, 40, false, false, 0), +- EP93XX_GPIO_BANK("D", 0x0c, 0x1c, 24, false, false, 0), +- EP93XX_GPIO_BANK("E", 0x20, 0x24, 32, false, false, 0), ++ EP93XX_GPIO_BANK("B", 0x04, 0x14, 0xac, 8, true, false, 72), ++ EP93XX_GPIO_BANK("C", 0x08, 0x18, 0x00, 40, false, false, 0), ++ EP93XX_GPIO_BANK("D", 0x0c, 0x1c, 0x00, 24, false, false, 0), ++ EP93XX_GPIO_BANK("E", 0x20, 0x24, 0x00, 32, false, false, 0), + /* Bank F has 8 IRQs */ +- EP93XX_GPIO_BANK("F", 0x30, 0x34, 16, false, true, 0), +- EP93XX_GPIO_BANK("G", 0x38, 0x3c, 48, false, false, 0), +- EP93XX_GPIO_BANK("H", 0x40, 0x44, 56, false, false, 0), ++ EP93XX_GPIO_BANK("F", 0x30, 0x34, 0x4c, 16, false, true, 0), ++ EP93XX_GPIO_BANK("G", 0x38, 0x3c, 0x00, 48, false, false, 0), ++ EP93XX_GPIO_BANK("H", 0x40, 0x44, 0x00, 56, false, false, 0), + }; + + static int ep93xx_gpio_set_config(struct gpio_chip *gc, unsigned offset, +@@ -326,13 +331,14 @@ static int ep93xx_gpio_f_to_irq(struct g + return EP93XX_GPIO_F_IRQ_BASE + offset; + } + +-static int ep93xx_gpio_add_bank(struct gpio_chip *gc, ++static int ep93xx_gpio_add_bank(struct ep93xx_gpio_chip *egc, + struct platform_device *pdev, + struct ep93xx_gpio *epg, + struct ep93xx_gpio_bank *bank) + { + void __iomem *data = epg->base + bank->data; + void __iomem *dir = epg->base + bank->dir; ++ struct gpio_chip *gc = &egc->gc; + struct device *dev = &pdev->dev; + struct gpio_irq_chip *girq; + int err; +@@ -347,6 +353,12 @@ static int ep93xx_gpio_add_bank(struct g + girq = &gc->irq; + if (bank->has_irq || bank->has_hierarchical_irq) { + gc->set_config = ep93xx_gpio_set_config; ++ egc->eic = devm_kcalloc(dev, 1, ++ sizeof(*egc->eic), ++ GFP_KERNEL); ++ if (!egc->eic) ++ return -ENOMEM; ++ egc->eic->irq_offset = bank->irq; + girq->chip = &ep93xx_gpio_irq_chip; + } + +@@ -415,7 +427,7 @@ static int ep93xx_gpio_probe(struct plat + return PTR_ERR(epg->base); + + for (i = 0; i < ARRAY_SIZE(ep93xx_gpio_banks); i++) { +- struct gpio_chip *gc = &epg->gc[i]; ++ struct ep93xx_gpio_chip *gc = &epg->gc[i]; + struct ep93xx_gpio_bank *bank = &ep93xx_gpio_banks[i]; + + if (ep93xx_gpio_add_bank(gc, pdev, epg, bank)) diff --git a/queue-5.4/gpio-ep93xx-fix-single-irqchip-with-multi-gpiochips.patch b/queue-5.4/gpio-ep93xx-fix-single-irqchip-with-multi-gpiochips.patch new file mode 100644 index 00000000000..3d927c3a99b --- /dev/null +++ b/queue-5.4/gpio-ep93xx-fix-single-irqchip-with-multi-gpiochips.patch @@ -0,0 +1,102 @@ +From 28dc10eb77a2db7681b08e3b109764bbe469e347 Mon Sep 17 00:00:00 2001 +From: Nikita Shubin +Date: Tue, 9 Feb 2021 16:31:05 +0300 +Subject: gpio: ep93xx: Fix single irqchip with multi gpiochips + +From: Nikita Shubin + +commit 28dc10eb77a2db7681b08e3b109764bbe469e347 upstream. + +Fixes the following warnings which results in interrupts disabled on +port B/F: + +gpio gpiochip1: (B): detected irqchip that is shared with multiple gpiochips: please fix the driver. +gpio gpiochip5: (F): detected irqchip that is shared with multiple gpiochips: please fix the driver. + +- added separate irqchip for each interrupt capable gpiochip +- provided unique names for each irqchip + +Fixes: d2b091961510 ("gpio: ep93xx: Pass irqchip when adding gpiochip") +Cc: +Signed-off-by: Nikita Shubin +Tested-by: Alexander Sverdlin +Signed-off-by: Bartosz Golaszewski +Signed-off-by: Greg Kroah-Hartman +--- + drivers/gpio/gpio-ep93xx.c | 30 +++++++++++++++++++----------- + 1 file changed, 19 insertions(+), 11 deletions(-) + +--- a/drivers/gpio/gpio-ep93xx.c ++++ b/drivers/gpio/gpio-ep93xx.c +@@ -38,6 +38,7 @@ + #define EP93XX_GPIO_F_IRQ_BASE 80 + + struct ep93xx_gpio_irq_chip { ++ struct irq_chip ic; + u8 irq_offset; + u8 int_unmasked; + u8 int_enabled; +@@ -263,15 +264,6 @@ static int ep93xx_gpio_irq_type(struct i + return 0; + } + +-static struct irq_chip ep93xx_gpio_irq_chip = { +- .name = "GPIO", +- .irq_ack = ep93xx_gpio_irq_ack, +- .irq_mask_ack = ep93xx_gpio_irq_mask_ack, +- .irq_mask = ep93xx_gpio_irq_mask, +- .irq_unmask = ep93xx_gpio_irq_unmask, +- .irq_set_type = ep93xx_gpio_irq_type, +-}; +- + /************************************************************************* + * gpiolib interface for EP93xx on-chip GPIOs + *************************************************************************/ +@@ -331,6 +323,15 @@ static int ep93xx_gpio_f_to_irq(struct g + return EP93XX_GPIO_F_IRQ_BASE + offset; + } + ++static void ep93xx_init_irq_chip(struct device *dev, struct irq_chip *ic) ++{ ++ ic->irq_ack = ep93xx_gpio_irq_ack; ++ ic->irq_mask_ack = ep93xx_gpio_irq_mask_ack; ++ ic->irq_mask = ep93xx_gpio_irq_mask; ++ ic->irq_unmask = ep93xx_gpio_irq_unmask; ++ ic->irq_set_type = ep93xx_gpio_irq_type; ++} ++ + static int ep93xx_gpio_add_bank(struct ep93xx_gpio_chip *egc, + struct platform_device *pdev, + struct ep93xx_gpio *epg, +@@ -352,6 +353,8 @@ static int ep93xx_gpio_add_bank(struct e + + girq = &gc->irq; + if (bank->has_irq || bank->has_hierarchical_irq) { ++ struct irq_chip *ic; ++ + gc->set_config = ep93xx_gpio_set_config; + egc->eic = devm_kcalloc(dev, 1, + sizeof(*egc->eic), +@@ -359,7 +362,12 @@ static int ep93xx_gpio_add_bank(struct e + if (!egc->eic) + return -ENOMEM; + egc->eic->irq_offset = bank->irq; +- girq->chip = &ep93xx_gpio_irq_chip; ++ ic = &egc->eic->ic; ++ ic->name = devm_kasprintf(dev, GFP_KERNEL, "gpio-irq-%s", bank->label); ++ if (!ic->name) ++ return -ENOMEM; ++ ep93xx_init_irq_chip(dev, ic); ++ girq->chip = ic; + } + + if (bank->has_irq) { +@@ -401,7 +409,7 @@ static int ep93xx_gpio_add_bank(struct e + gpio_irq = EP93XX_GPIO_F_IRQ_BASE + i; + irq_set_chip_data(gpio_irq, &epg->gc[5]); + irq_set_chip_and_handler(gpio_irq, +- &ep93xx_gpio_irq_chip, ++ girq->chip, + handle_level_irq); + irq_clear_status_flags(gpio_irq, IRQ_NOREQUEST); + } diff --git a/queue-5.4/series b/queue-5.4/series index e69de29bb2d..1359bcb6714 100644 --- a/queue-5.4/series +++ b/queue-5.4/series @@ -0,0 +1,6 @@ +gpio-ep93xx-fix-bug_on-port-f-usage.patch +gpio-ep93xx-fix-single-irqchip-with-multi-gpiochips.patch +tracing-do-not-count-ftrace-events-in-top-level-enable-output.patch +tracing-check-length-before-giving-out-the-filter-buffer.patch +arm-xen-don-t-probe-xenbus-as-part-of-an-early-initcall.patch +cgroup-fix-psi-monitor-for-root-cgroup.patch diff --git a/queue-5.4/tracing-check-length-before-giving-out-the-filter-buffer.patch b/queue-5.4/tracing-check-length-before-giving-out-the-filter-buffer.patch new file mode 100644 index 00000000000..3046284b8fb --- /dev/null +++ b/queue-5.4/tracing-check-length-before-giving-out-the-filter-buffer.patch @@ -0,0 +1,46 @@ +From b220c049d5196dd94d992dd2dc8cba1a5e6123bf Mon Sep 17 00:00:00 2001 +From: "Steven Rostedt (VMware)" +Date: Wed, 10 Feb 2021 11:53:22 -0500 +Subject: tracing: Check length before giving out the filter buffer + +From: Steven Rostedt (VMware) + +commit b220c049d5196dd94d992dd2dc8cba1a5e6123bf upstream. + +When filters are used by trace events, a page is allocated on each CPU and +used to copy the trace event fields to this page before writing to the ring +buffer. The reason to use the filter and not write directly into the ring +buffer is because a filter may discard the event and there's more overhead +on discarding from the ring buffer than the extra copy. + +The problem here is that there is no check against the size being allocated +when using this page. If an event asks for more than a page size while being +filtered, it will get only a page, leading to the caller writing more that +what was allocated. + +Check the length of the request, and if it is more than PAGE_SIZE minus the +header default back to allocating from the ring buffer directly. The ring +buffer may reject the event if its too big anyway, but it wont overflow. + +Link: https://lore.kernel.org/ath10k/1612839593-2308-1-git-send-email-wgong@codeaurora.org/ + +Cc: stable@vger.kernel.org +Fixes: 0fc1b09ff1ff4 ("tracing: Use temp buffer when filtering events") +Reported-by: Wen Gong +Signed-off-by: Steven Rostedt (VMware) +Signed-off-by: Greg Kroah-Hartman +--- + kernel/trace/trace.c | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +--- a/kernel/trace/trace.c ++++ b/kernel/trace/trace.c +@@ -2498,7 +2498,7 @@ trace_event_buffer_lock_reserve(struct r + (entry = this_cpu_read(trace_buffered_event))) { + /* Try to use the per cpu buffer first */ + val = this_cpu_inc_return(trace_buffered_event_cnt); +- if (val == 1) { ++ if ((len < (PAGE_SIZE - sizeof(*entry))) && val == 1) { + trace_event_setup(entry, type, flags, pc); + entry->array[0] = len; + return entry; diff --git a/queue-5.4/tracing-do-not-count-ftrace-events-in-top-level-enable-output.patch b/queue-5.4/tracing-do-not-count-ftrace-events-in-top-level-enable-output.patch new file mode 100644 index 00000000000..6d5332a4616 --- /dev/null +++ b/queue-5.4/tracing-do-not-count-ftrace-events-in-top-level-enable-output.patch @@ -0,0 +1,48 @@ +From 256cfdd6fdf70c6fcf0f7c8ddb0ebd73ce8f3bc9 Mon Sep 17 00:00:00 2001 +From: "Steven Rostedt (VMware)" +Date: Fri, 5 Feb 2021 15:40:04 -0500 +Subject: tracing: Do not count ftrace events in top level enable output + +From: Steven Rostedt (VMware) + +commit 256cfdd6fdf70c6fcf0f7c8ddb0ebd73ce8f3bc9 upstream. + +The file /sys/kernel/tracing/events/enable is used to enable all events by +echoing in "1", or disabling all events when echoing in "0". To know if all +events are enabled, disabled, or some are enabled but not all of them, +cating the file should show either "1" (all enabled), "0" (all disabled), or +"X" (some enabled but not all of them). This works the same as the "enable" +files in the individule system directories (like tracing/events/sched/enable). + +But when all events are enabled, the top level "enable" file shows "X". The +reason is that its checking the "ftrace" events, which are special events +that only exist for their format files. These include the format for the +function tracer events, that are enabled when the function tracer is +enabled, but not by the "enable" file. The check includes these events, +which will always be disabled, and even though all true events are enabled, +the top level "enable" file will show "X" instead of "1". + +To fix this, have the check test the event's flags to see if it has the +"IGNORE_ENABLE" flag set, and if so, not test it. + +Cc: stable@vger.kernel.org +Fixes: 553552ce1796c ("tracing: Combine event filter_active and enable into single flags field") +Reported-by: "Yordan Karadzhov (VMware)" +Signed-off-by: Steven Rostedt (VMware) +Signed-off-by: Greg Kroah-Hartman +--- + kernel/trace/trace_events.c | 3 ++- + 1 file changed, 2 insertions(+), 1 deletion(-) + +--- a/kernel/trace/trace_events.c ++++ b/kernel/trace/trace_events.c +@@ -1107,7 +1107,8 @@ system_enable_read(struct file *filp, ch + mutex_lock(&event_mutex); + list_for_each_entry(file, &tr->events, list) { + call = file->event_call; +- if (!trace_event_name(call) || !call->class || !call->class->reg) ++ if ((call->flags & TRACE_EVENT_FL_IGNORE_ENABLE) || ++ !trace_event_name(call) || !call->class || !call->class->reg) + continue; + + if (system && strcmp(call->class->system, system->name) != 0)