From: Craig Janeczek <jancraig@amazon.com>
Date: Thu, 18 Oct 2018 12:36:57 +0000 (+0200)
Subject: target/mips: Define a bit for MXU in insn_flags
X-Git-Tag: v3.1.0-rc0~26^2~24
X-Git-Url: http://git.ipfire.org/?a=commitdiff_plain;h=a031ac61619294ae473a78d1834e757fad8b59e5;p=thirdparty%2Fqemu.git

target/mips: Define a bit for MXU in insn_flags

Define a bit for MXU in insn_flags. This is the first non-MIPS
(third party) ASE supported in QEMU for MIPS, so it is placed in
the section "bits 56-63: vendor-specific ASEs".

Reviewed-by: Aleksandar Markovic <amarkovic@wavecomp.com>
Signed-off-by: Craig Janeczek <jancraig@amazon.com>
Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
---

diff --git a/target/mips/mips-defs.h b/target/mips/mips-defs.h
index 51776186159..dbdb4b2b2da 100644
--- a/target/mips/mips-defs.h
+++ b/target/mips/mips-defs.h
@@ -69,6 +69,7 @@
  *   bits 56-63: vendor-specific ASEs
  */
 #define ASE_MMI           0x0100000000000000ULL
+#define ASE_MXU           0x0200000000000000ULL
 
 /* MIPS CPU defines. */
 #define		CPU_MIPS1	(ISA_MIPS1)