From: Saurabh Jha Date: Wed, 23 Jul 2025 10:41:53 +0000 (+0000) Subject: gas: aarch64: Add instructions for GICv5 X-Git-Url: http://git.ipfire.org/?a=commitdiff_plain;h=a149def232c6a143651a5943dcdb1aa8aa2f653b;p=thirdparty%2Fbinutils-gdb.git gas: aarch64: Add instructions for GICv5 Add new instructions from the Generic Interrupt Controller, GICv5, extension. These instructions are aliases to system instructions and are the following: * gic , * gicr , * gsb --- diff --git a/gas/config/tc-aarch64.c b/gas/config/tc-aarch64.c index 3687271ff7a..8d7d750e046 100644 --- a/gas/config/tc-aarch64.c +++ b/gas/config/tc-aarch64.c @@ -564,6 +564,9 @@ static htab_t aarch64_barrier_opt_hsh; static htab_t aarch64_nzcv_hsh; static htab_t aarch64_pldop_hsh; static htab_t aarch64_hint_opt_hsh; +static htab_t aarch64_sys_ins_gic_hsh; +static htab_t aarch64_sys_ins_gicr_hsh; +static htab_t aarch64_sys_ins_gsb_hsh; /* Stuff needed to resolve the label ambiguity As: @@ -8079,6 +8082,22 @@ parse_operands (char *str, const aarch64_opcode *opcode) case AARCH64_OPND_SYSREG_TLBIP: inst.base.operands[i].sysins_op = parse_sys_ins_reg (&str, aarch64_sys_regs_tlbi_hsh, true); + goto sys_reg_ins; + + case AARCH64_OPND_GIC: + inst.base.operands[i].sysins_op = + parse_sys_ins_reg (&str, aarch64_sys_ins_gic_hsh, false); + goto sys_reg_ins; + + case AARCH64_OPND_GICR: + inst.base.operands[i].sysins_op = + parse_sys_ins_reg (&str, aarch64_sys_ins_gicr_hsh, false); + goto sys_reg_ins; + + case AARCH64_OPND_GSB: + inst.base.operands[i].sysins_op = + parse_sys_ins_reg (&str, aarch64_sys_ins_gsb_hsh, false); + sys_reg_ins: if (inst.base.operands[i].sysins_op == NULL) { @@ -10412,6 +10431,9 @@ md_begin (void) aarch64_nzcv_hsh = str_htab_create (); aarch64_pldop_hsh = str_htab_create (); aarch64_hint_opt_hsh = str_htab_create (); + aarch64_sys_ins_gic_hsh = str_htab_create (); + aarch64_sys_ins_gicr_hsh = str_htab_create (); + aarch64_sys_ins_gsb_hsh = str_htab_create (); fill_instruction_hash_table (); @@ -10535,6 +10557,18 @@ md_begin (void) aarch64_hint_options + i); } + for (i = 0; aarch64_sys_ins_gic[i].name != NULL; i++) + sysreg_hash_insert (aarch64_sys_ins_gic_hsh, aarch64_sys_ins_gic[i].name, + aarch64_sys_ins_gic + i); + + for (i = 0; aarch64_sys_ins_gicr[i].name != NULL; i++) + sysreg_hash_insert (aarch64_sys_ins_gicr_hsh, aarch64_sys_ins_gicr[i].name, + aarch64_sys_ins_gicr + i); + + for (i = 0; aarch64_sys_ins_gsb[i].name != NULL; i++) + sysreg_hash_insert (aarch64_sys_ins_gsb_hsh, aarch64_sys_ins_gsb[i].name, + aarch64_sys_ins_gsb + i); + /* Set the cpu variant based on the command-line options. */ if (!mcpu_cpu_opt) mcpu_cpu_opt = march_cpu_opt; diff --git a/gas/testsuite/gas/aarch64/gcie-bad.d b/gas/testsuite/gas/aarch64/gcie-bad.d new file mode 100644 index 00000000000..9220a31bc8d --- /dev/null +++ b/gas/testsuite/gas/aarch64/gcie-bad.d @@ -0,0 +1,3 @@ +#as: +#source: gcie.s +#error_output: gcie-bad.l diff --git a/gas/testsuite/gas/aarch64/gcie-bad.l b/gas/testsuite/gas/aarch64/gcie-bad.l new file mode 100644 index 00000000000..0695407abc8 --- /dev/null +++ b/gas/testsuite/gas/aarch64/gcie-bad.l @@ -0,0 +1,57 @@ +[^ :]+: Assembler messages: +.*: Error: selected processor does not support `gic cdaff,x0' +.*: Error: selected processor does not support `gic cdaff,xzr' +.*: Error: selected processor does not support `gic cddi,x0' +.*: Error: selected processor does not support `gic cddi,xzr' +.*: Error: selected processor does not support `gic cddis,x0' +.*: Error: selected processor does not support `gic cddis,xzr' +.*: Error: selected processor does not support `gic cden,x0' +.*: Error: selected processor does not support `gic cden,xzr' +.*: Error: selected processor does not support `gic cdeoi,x0' +.*: Error: selected processor does not support `gic cdeoi,xzr' +.*: Error: selected processor does not support `gic cdhm,x0' +.*: Error: selected processor does not support `gic cdhm,xzr' +.*: Error: selected processor does not support `gic cdpend,x0' +.*: Error: selected processor does not support `gic cdpend,xzr' +.*: Error: selected processor does not support `gic cdpri,x0' +.*: Error: selected processor does not support `gic cdpri,xzr' +.*: Error: selected processor does not support `gic cdrcfg,x0' +.*: Error: selected processor does not support `gic cdrcfg,xzr' +.*: Error: selected processor does not support `gicr x0,cdia' +.*: Error: selected processor does not support `gicr xzr,cdia' +.*: Error: selected processor does not support `gicr x0,cdnmia' +.*: Error: selected processor does not support `gicr xzr,cdnmia' +.*: Error: selected processor does not support `gic vdaff,x0' +.*: Error: selected processor does not support `gic vdaff,xzr' +.*: Error: selected processor does not support `gic vddi,x0' +.*: Error: selected processor does not support `gic vddi,xzr' +.*: Error: selected processor does not support `gic vddis,x0' +.*: Error: selected processor does not support `gic vddis,xzr' +.*: Error: selected processor does not support `gic vden,x0' +.*: Error: selected processor does not support `gic vden,xzr' +.*: Error: selected processor does not support `gic vdhm,x0' +.*: Error: selected processor does not support `gic vdhm,xzr' +.*: Error: selected processor does not support `gic vdpend,x0' +.*: Error: selected processor does not support `gic vdpend,xzr' +.*: Error: selected processor does not support `gic vdpri,x0' +.*: Error: selected processor does not support `gic vdpri,xzr' +.*: Error: selected processor does not support `gic vdrcfg,x0' +.*: Error: selected processor does not support `gic vdrcfg,xzr' +.*: Error: selected processor does not support `gic ldaff,x0' +.*: Error: selected processor does not support `gic ldaff,xzr' +.*: Error: selected processor does not support `gic lddi,x0' +.*: Error: selected processor does not support `gic lddi,xzr' +.*: Error: selected processor does not support `gic lddis,x0' +.*: Error: selected processor does not support `gic lddis,xzr' +.*: Error: selected processor does not support `gic lden,x0' +.*: Error: selected processor does not support `gic lden,xzr' +.*: Error: selected processor does not support `gic ldhm,x0' +.*: Error: selected processor does not support `gic ldhm,xzr' +.*: Error: selected processor does not support `gic ldpend,x0' +.*: Error: selected processor does not support `gic ldpend,xzr' +.*: Error: selected processor does not support `gic ldpri,x0' +.*: Error: selected processor does not support `gic ldpri,xzr' +.*: Error: selected processor does not support `gic ldrcfg,x0' +.*: Error: selected processor does not support `gic ldrcfg,xzr' +.*: Error: selected processor does not support `gsb sys' +.*: Error: selected processor does not support `gsb ack' diff --git a/gas/testsuite/gas/aarch64/gcie-illegal.d b/gas/testsuite/gas/aarch64/gcie-illegal.d new file mode 100644 index 00000000000..85a2b99eccf --- /dev/null +++ b/gas/testsuite/gas/aarch64/gcie-illegal.d @@ -0,0 +1,3 @@ +#as: -march=armv8-a+gcie +#source: gcie-illegal.s +#error_output: gcie-illegal.l diff --git a/gas/testsuite/gas/aarch64/gcie-illegal.l b/gas/testsuite/gas/aarch64/gcie-illegal.l new file mode 100644 index 00000000000..48966e6fcea --- /dev/null +++ b/gas/testsuite/gas/aarch64/gcie-illegal.l @@ -0,0 +1,16 @@ +[^ :]+: Assembler messages: +[^ :]+:[0-9]+: Error: comma expected between operands at operand 2 -- `gic cdaff' +[^ :]+:[0-9]+: Error: expected an integer or zero register at operand 2 -- `gic cdaff,' +[^ :]+:[0-9]+: Error: comma expected between operands at operand 2 -- `gicr x0' +[^ :]+:[0-9]+: Error: unknown or missing operation name at operand 2 -- `gicr x0,' +[^ :]+:[0-9]+: Error: unknown or missing operation name at operand 1 -- `gsb' +[^ :]+:[0-9]+: Error: unexpected characters following instruction at operand 2 -- `gic cdaff,x0,x1' +[^ :]+:[0-9]+: Error: unexpected characters following instruction at operand 2 -- `gicr x0,cdia,x1' +[^ :]+:[0-9]+: Error: unexpected characters following instruction at operand 1 -- `gsb ack,x0' +[^ :]+:[0-9]+: Error: unknown or missing operation name at operand 1 -- `gic x0' +[^ :]+:[0-9]+: Error: unknown or missing operation name at operand 1 -- `gic x0,cdaff' +[^ :]+:[0-9]+: Error: expected an integer or zero register at operand 1 -- `gicr cdia' +[^ :]+:[0-9]+: Error: expected an integer or zero register at operand 1 -- `gicr cdia,x0' +[^ :]+:[0-9]+: Error: unknown or missing operation name at operand 1 -- `gic cdwat,x0' +[^ :]+:[0-9]+: Error: unknown or missing operation name at operand 2 -- `gicr x0,cdwat' +[^ :]+:[0-9]+: Error: unknown or missing operation name at operand 1 -- `gsb awt' diff --git a/gas/testsuite/gas/aarch64/gcie-illegal.s b/gas/testsuite/gas/aarch64/gcie-illegal.s new file mode 100644 index 00000000000..18d3d988851 --- /dev/null +++ b/gas/testsuite/gas/aarch64/gcie-illegal.s @@ -0,0 +1,22 @@ + // Less operands + gic cdaff + gic cdaff, + gicr x0 + gicr x0, + gsb + + // More operands + gic cdaff, x0, x1 + gicr x0, cdia, x1 + gsb ack, x0 + + // Incorrect operands + gic x0 + gic x0, cdaff + gicr cdia + gicr cdia, x0 + + // Incorrect operation + gic cdwat, x0 + gicr x0, cdwat + gsb awt diff --git a/gas/testsuite/gas/aarch64/gcie.d b/gas/testsuite/gas/aarch64/gcie.d new file mode 100644 index 00000000000..067683f5b01 --- /dev/null +++ b/gas/testsuite/gas/aarch64/gcie.d @@ -0,0 +1,66 @@ +#objdump: -dr +#as: -march=armv8-a+gcie + +.*: file format .* + +Disassembly of section \.text: + +0+ <.*>: +[^:]+: d508c160 gic cdaff, x0 +[^:]+: d508c17f gic cdaff, xzr +[^:]+: d508c200 gic cddi, x0 +[^:]+: d508c21f gic cddi, xzr +[^:]+: d508c100 gic cddis, x0 +[^:]+: d508c11f gic cddis, xzr +[^:]+: d508c120 gic cden, x0 +[^:]+: d508c13f gic cden, xzr +[^:]+: d508c1e0 gic cdeoi, x0 +[^:]+: d508c1ff gic cdeoi, xzr +[^:]+: d508c220 gic cdhm, x0 +[^:]+: d508c23f gic cdhm, xzr +[^:]+: d508c180 gic cdpend, x0 +[^:]+: d508c19f gic cdpend, xzr +[^:]+: d508c140 gic cdpri, x0 +[^:]+: d508c15f gic cdpri, xzr +[^:]+: d508c1a0 gic cdrcfg, x0 +[^:]+: d508c1bf gic cdrcfg, xzr +[^:]+: d508c300 gicr x0, cdia +[^:]+: d508c31f gicr xzr, cdia +[^:]+: d508c320 gicr x0, cdnmia +[^:]+: d508c33f gicr xzr, cdnmia +[^:]+: d50cc160 gic vdaff, x0 +[^:]+: d50cc17f gic vdaff, xzr +[^:]+: d50cc200 gic vddi, x0 +[^:]+: d50cc21f gic vddi, xzr +[^:]+: d50cc100 gic vddis, x0 +[^:]+: d50cc11f gic vddis, xzr +[^:]+: d50cc120 gic vden, x0 +[^:]+: d50cc13f gic vden, xzr +[^:]+: d50cc220 gic vdhm, x0 +[^:]+: d50cc23f gic vdhm, xzr +[^:]+: d50cc180 gic vdpend, x0 +[^:]+: d50cc19f gic vdpend, xzr +[^:]+: d50cc140 gic vdpri, x0 +[^:]+: d50cc15f gic vdpri, xzr +[^:]+: d50cc1a0 gic vdrcfg, x0 +[^:]+: d50cc1bf gic vdrcfg, xzr +[^:]+: d50ec160 gic ldaff, x0 +[^:]+: d50ec17f gic ldaff, xzr +[^:]+: d50ec200 gic lddi, x0 +[^:]+: d50ec21f gic lddi, xzr +[^:]+: d50ec100 gic lddis, x0 +[^:]+: d50ec11f gic lddis, xzr +[^:]+: d50ec120 gic lden, x0 +[^:]+: d50ec13f gic lden, xzr +[^:]+: d50ec220 gic ldhm, x0 +[^:]+: d50ec23f gic ldhm, xzr +[^:]+: d50ec180 gic ldpend, x0 +[^:]+: d50ec19f gic ldpend, xzr +[^:]+: d50ec140 gic ldpri, x0 +[^:]+: d50ec15f gic ldpri, xzr +[^:]+: d50ec1a0 gic ldrcfg, x0 +[^:]+: d50ec1bf gic ldrcfg, xzr +[^:]+: d508c01f gsb sys +[^:]+: d508c03f gsb ack +[^:]+: d508c000 sys #0, C12, C0, #0, x0 +[^:]+: d508c020 sys #0, C12, C0, #1, x0 diff --git a/gas/testsuite/gas/aarch64/gcie.s b/gas/testsuite/gas/aarch64/gcie.s new file mode 100644 index 00000000000..2e039301dff --- /dev/null +++ b/gas/testsuite/gas/aarch64/gcie.s @@ -0,0 +1,117 @@ + // GIC CDAFF + gic cdaff, x0 + gic cdaff, xzr + + // GIC CDDI + gic cddi, x0 + gic cddi, xzr + + // GIC CDDIS + gic cddis, x0 + gic cddis, xzr + + // GIC CDEN + gic cden, x0 + gic cden, xzr + + // GIC CDEOI + gic cdeoi, x0 + gic cdeoi, xzr + + // GIC CDHM + gic cdhm, x0 + gic cdhm, xzr + + // GIC CDPEND + gic cdpend, x0 + gic cdpend, xzr + + // GIC CDPRI + gic cdpri, x0 + gic cdpri, xzr + + // GIC CDRCFG + gic cdrcfg, x0 + gic cdrcfg, xzr + + // GICR CDIA + gicr x0, cdia + gicr xzr, cdia + + // GICR CDNMIA + gicr x0, cdnmia + gicr xzr, cdnmia + + // GIC VDAFF + gic vdaff, x0 + gic vdaff, xzr + + // GIC VDDI + gic vddi, x0 + gic vddi, xzr + + // GIC VDDIS + gic vddis, x0 + gic vddis, xzr + + // GIC VDEN + gic vden, x0 + gic vden, xzr + + // GIC VDHM + gic vdhm, x0 + gic vdhm, xzr + + // GIC VDPEND + gic vdpend, x0 + gic vdpend, xzr + + // GIC VDPRI + gic vdpri, x0 + gic vdpri, xzr + + // GIC VDRCFG + gic vdrcfg, x0 + gic vdrcfg, xzr + + // GIC LDAFF + gic ldaff, x0 + gic ldaff, xzr + + // GIC LDDI + gic lddi, x0 + gic lddi, xzr + + // GIC LDDIS + gic lddis, x0 + gic lddis, xzr + + // GIC LDEN + gic lden, x0 + gic lden, xzr + + // GIC LDHM + gic ldhm, x0 + gic ldhm, xzr + + // GIC LDPEND + gic ldpend, x0 + gic ldpend, xzr + + // GIC LDPRI + gic ldpri, x0 + gic ldpri, xzr + + // GIC LDRCFG + gic ldrcfg, x0 + gic ldrcfg, xzr + + // GSB SYS + gsb sys + + // GSB ACK + gsb ack + + // Don't disassemble gsb with nonzero Rt + sys #0, c12, c0, #0, x0 + sys #0, c12, c0, #1, x0 diff --git a/include/opcode/aarch64.h b/include/opcode/aarch64.h index 8a771a13012..9408d00dde0 100644 --- a/include/opcode/aarch64.h +++ b/include/opcode/aarch64.h @@ -945,6 +945,9 @@ enum aarch64_opnd AARCH64_OPND_RCPC3_ADDR_POSTIND, /* [], #. */ AARCH64_OPND_RCPC3_ADDR_PREIND_WB, /* [, #]!. */ AARCH64_OPND_RCPC3_ADDR_OFFSET, + AARCH64_OPND_GIC, + AARCH64_OPND_GICR, + AARCH64_OPND_GSB, }; /* Qualifier constrains an operand. It either specifies a variant of an @@ -1629,6 +1632,9 @@ extern const aarch64_sys_ins_reg aarch64_sys_regs_ic []; extern const aarch64_sys_ins_reg aarch64_sys_regs_dc []; extern const aarch64_sys_ins_reg aarch64_sys_regs_at []; extern const aarch64_sys_ins_reg aarch64_sys_regs_tlbi []; +extern const aarch64_sys_ins_reg aarch64_sys_ins_gic []; +extern const aarch64_sys_ins_reg aarch64_sys_ins_gicr []; +extern const aarch64_sys_ins_reg aarch64_sys_ins_gsb []; extern const aarch64_sys_ins_reg aarch64_sys_regs_sr []; /* Shift/extending operator kinds. diff --git a/opcodes/aarch64-asm-2.c b/opcodes/aarch64-asm-2.c index fa3866781e4..ac0bf7a70be 100644 --- a/opcodes/aarch64-asm-2.c +++ b/opcodes/aarch64-asm-2.c @@ -556,6 +556,9 @@ aarch64_find_real_opcode (const aarch64_opcode *opcode) case A64_OPID_d503323f_dsb_BARRIER_DSB_NXS: value = A64_OPID_d503323f_dsb_BARRIER_DSB_NXS; break; + case A64_OPID_d5080000_gsb_GSB: + case A64_OPID_d5080000_gicr_Rd_GICR: + case A64_OPID_d5080000_gic_GIC_Rd: case A64_OPID_d50b72e0_trcit_Rt: case A64_OPID_d5097280_brb_BRBOP_Rt_IN_SYS_ALIASES: case A64_OPID_d50b73c0_cosp_SYSREG_SR_Rt: @@ -1012,6 +1015,9 @@ aarch64_insert_operand (const aarch64_operand *self, case AARCH64_OPND_SYSREG_TLBI: case AARCH64_OPND_SYSREG_TLBIP: case AARCH64_OPND_SYSREG_SR: + case AARCH64_OPND_GIC: + case AARCH64_OPND_GICR: + case AARCH64_OPND_GSB: return aarch64_ins_sysins_op (self, info, code, inst, errors); case AARCH64_OPND_BARRIER: case AARCH64_OPND_BARRIER_ISB: diff --git a/opcodes/aarch64-dis-2.c b/opcodes/aarch64-dis-2.c index 6e66d54885b..275d295d7f9 100644 --- a/opcodes/aarch64-dis-2.c +++ b/opcodes/aarch64-dis-2.c @@ -34859,7 +34859,7 @@ aarch64_find_alias_opcode (const aarch64_opcode *opcode) value = A64_OPID_d503323f_dsb_BARRIER_DSB_NXS; break; case A64_OPID_d5080000_sys_UIMM3_OP1_CRn_CRm_UIMM3_OP2_Rt: - value = A64_OPID_d50b72e0_trcit_Rt; + value = A64_OPID_d5080000_gsb_GSB; break; case A64_OPID_d5480000_sysp_UIMM3_OP1_CRn_CRm_UIMM3_OP2_Rt_PAIRREG_OR_XZR: value = A64_OPID_d5480000_tlbip_SYSREG_TLBIP_Rt_SYS_PAIRREG_OR_XZR; @@ -35508,6 +35508,15 @@ aarch64_find_next_alias_opcode (const aarch64_opcode *opcode) case A64_OPID_d5033c9f_dfb: value = A64_OPID_d503309f_dsb_BARRIER; break; + case A64_OPID_d5080000_gsb_GSB: + value = A64_OPID_d5080000_gicr_Rd_GICR; + break; + case A64_OPID_d5080000_gicr_Rd_GICR: + value = A64_OPID_d5080000_gic_GIC_Rd; + break; + case A64_OPID_d5080000_gic_GIC_Rd: + value = A64_OPID_d50b72e0_trcit_Rt; + break; case A64_OPID_d50b72e0_trcit_Rt: value = A64_OPID_d5097280_brb_BRBOP_Rt_IN_SYS_ALIASES; break; @@ -35946,6 +35955,9 @@ aarch64_extract_operand (const aarch64_operand *self, case AARCH64_OPND_SYSREG_TLBI: case AARCH64_OPND_SYSREG_TLBIP: case AARCH64_OPND_SYSREG_SR: + case AARCH64_OPND_GIC: + case AARCH64_OPND_GICR: + case AARCH64_OPND_GSB: return aarch64_ext_sysins_op (self, info, code, inst, errors); case AARCH64_OPND_BARRIER: case AARCH64_OPND_BARRIER_ISB: diff --git a/opcodes/aarch64-dis.c b/opcodes/aarch64-dis.c index 3ca22bb5c8a..4a4be31c813 100644 --- a/opcodes/aarch64-dis.c +++ b/opcodes/aarch64-dis.c @@ -1428,6 +1428,9 @@ aarch64_ext_sysins_op (const aarch64_operand *self ATTRIBUTE_UNUSED, switch (info->type) { + case AARCH64_OPND_GIC: sysins_ops = aarch64_sys_ins_gic; break; + case AARCH64_OPND_GICR: sysins_ops = aarch64_sys_ins_gicr; break; + case AARCH64_OPND_GSB: sysins_ops = aarch64_sys_ins_gsb; break; case AARCH64_OPND_SYSREG_AT: sysins_ops = aarch64_sys_regs_at; break; case AARCH64_OPND_SYSREG_DC: sysins_ops = aarch64_sys_regs_dc; break; case AARCH64_OPND_SYSREG_IC: sysins_ops = aarch64_sys_regs_ic; break; diff --git a/opcodes/aarch64-opc-2.c b/opcodes/aarch64-opc-2.c index c70824a615d..90cbf8fd0bf 100644 --- a/opcodes/aarch64-opc-2.c +++ b/opcodes/aarch64-opc-2.c @@ -364,6 +364,9 @@ const struct aarch64_operand aarch64_operands[] = {AARCH64_OPND_CLASS_ADDRESS, "RCPC3_ADDR_POSTIND", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {}, "an address with post-incrementing by ammount of loaded bytes"}, {AARCH64_OPND_CLASS_ADDRESS, "RCPC3_ADDR_PREIND_WB", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {}, "an address with pre-incrementing with write-back by ammount of stored bytes"}, {AARCH64_OPND_CLASS_ADDRESS, "RCPC3_ADDR_OFFSET", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rn,FLD_imm9}, "an address with an optional 8-bit signed immediate offset"}, + {AARCH64_OPND_CLASS_SYSTEM, "GIC", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {}, "Generic Interrupt Controller"}, + {AARCH64_OPND_CLASS_SYSTEM, "GICR", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {}, "Generic Interrupt Controller"}, + {AARCH64_OPND_CLASS_SYSTEM, "GSB", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {}, "Generic Interrupt Controller Synchronization Barrier"}, {AARCH64_OPND_CLASS_NIL, "", 0, {0}, "DUMMY"}, }; diff --git a/opcodes/aarch64-opc.c b/opcodes/aarch64-opc.c index 4b173201e92..e01b9f7b09d 100644 --- a/opcodes/aarch64-opc.c +++ b/opcodes/aarch64-opc.c @@ -5019,6 +5019,9 @@ aarch64_print_operand (char *buf, size_t size, bfd_vma pc, style_reg (styler, aarch64_pstatefields[i].name)); break; + case AARCH64_OPND_GIC: + case AARCH64_OPND_GICR: + case AARCH64_OPND_GSB: case AARCH64_OPND_SYSREG_AT: case AARCH64_OPND_SYSREG_DC: case AARCH64_OPND_SYSREG_IC: @@ -5393,6 +5396,50 @@ const aarch64_sys_ins_reg aarch64_sys_regs_tlbi[] = { 0, CPENS(0,0,0,0), 0, AARCH64_NO_FEATURES } }; +const aarch64_sys_ins_reg aarch64_sys_ins_gic[] = +{ + { "cdaff", CPENS (0,C12,C1,3), 0, AARCH64_NO_FEATURES }, + { "cddi", CPENS (0,C12,C2,0), 0, AARCH64_NO_FEATURES }, + { "cddis", CPENS (0,C12,C1,0), 0, AARCH64_NO_FEATURES }, + { "cden", CPENS (0,C12,C1,1), 0, AARCH64_NO_FEATURES }, + { "cdeoi", CPENS (0,C12,C1,7), 0, AARCH64_NO_FEATURES }, + { "cdhm", CPENS (0,C12,C2,1), 0, AARCH64_NO_FEATURES }, + { "cdpend", CPENS (0,C12,C1,4), 0, AARCH64_NO_FEATURES }, + { "cdpri", CPENS (0,C12,C1,2), 0, AARCH64_NO_FEATURES }, + { "cdrcfg", CPENS (0,C12,C1,5), 0, AARCH64_NO_FEATURES }, + { "vdaff", CPENS (4,C12,C1,3), 0, AARCH64_NO_FEATURES }, + { "vddi", CPENS (4,C12,C2,0), 0, AARCH64_NO_FEATURES }, + { "vddis", CPENS (4,C12,C1,0), 0, AARCH64_NO_FEATURES }, + { "vden", CPENS (4,C12,C1,1), 0, AARCH64_NO_FEATURES }, + { "vdhm", CPENS (4,C12,C2,1), 0, AARCH64_NO_FEATURES }, + { "vdpend", CPENS (4,C12,C1,4), 0, AARCH64_NO_FEATURES }, + { "vdpri", CPENS (4,C12,C1,2), 0, AARCH64_NO_FEATURES }, + { "vdrcfg", CPENS (4,C12,C1,5), 0, AARCH64_NO_FEATURES }, + { "ldaff", CPENS (6,C12,C1,3), 0, AARCH64_NO_FEATURES }, + { "lddi", CPENS (6,C12,C2,0), 0, AARCH64_NO_FEATURES }, + { "lddis", CPENS (6,C12,C1,0), 0, AARCH64_NO_FEATURES }, + { "lden", CPENS (6,C12,C1,1), 0, AARCH64_NO_FEATURES }, + { "ldhm", CPENS (6,C12,C2,1), 0, AARCH64_NO_FEATURES }, + { "ldpend", CPENS (6,C12,C1,4), 0, AARCH64_NO_FEATURES }, + { "ldpri", CPENS (6,C12,C1,2), 0, AARCH64_NO_FEATURES }, + { "ldrcfg", CPENS (6,C12,C1,5), 0, AARCH64_NO_FEATURES }, + { 0, CPENS (0,0,0,0), 0, AARCH64_NO_FEATURES } +}; + +const aarch64_sys_ins_reg aarch64_sys_ins_gicr[] = +{ + { "cdia", CPENS (0,C12,C3,0), 0, AARCH64_NO_FEATURES }, + { "cdnmia", CPENS (0,C12,C3,1), 0, AARCH64_NO_FEATURES }, + { 0, CPENS (0,0,0,0), 0, AARCH64_NO_FEATURES } +}; + +const aarch64_sys_ins_reg aarch64_sys_ins_gsb[] = +{ + { "sys", CPENS (0,C12,0,0), 0, AARCH64_NO_FEATURES }, + { "ack", CPENS (0,C12,0,1), 0, AARCH64_NO_FEATURES }, + { 0, CPENS (0,0,0,0), 0, AARCH64_NO_FEATURES } +}; + const aarch64_sys_ins_reg aarch64_sys_regs_sr[] = { /* RCTX is somewhat unique in a way that it has different values diff --git a/opcodes/aarch64-tbl-2.h b/opcodes/aarch64-tbl-2.h index 808a6c5ad5b..01a984dd849 100644 --- a/opcodes/aarch64-tbl-2.h +++ b/opcodes/aarch64-tbl-2.h @@ -3843,5 +3843,8 @@ enum aarch64_opcode_idx A64_OPID_c121e800_fmul_SME_Zdnx4_SME_Znx4_SME_Zm_17, A64_OPID_c120e400_fmul_SME_Zdnx2_SME_Znx2_SME_Zmx2, A64_OPID_c121e400_fmul_SME_Zdnx4_SME_Znx4_SME_Zmx4, + A64_OPID_d5080000_gic_GIC_Rd, + A64_OPID_d5080000_gicr_Rd_GICR, + A64_OPID_d5080000_gsb_GSB, A64_OPID_MAX, }; diff --git a/opcodes/aarch64-tbl.h b/opcodes/aarch64-tbl.h index 34b551eb64c..288134e6adf 100644 --- a/opcodes/aarch64-tbl.h +++ b/opcodes/aarch64-tbl.h @@ -3410,6 +3410,8 @@ static const aarch64_feature_set aarch64_feature_gcie = #define SME2p2_INSN(NAME,OPCODE,MASK,CLASS,OPS,QUALS,FLAGS,TIED) \ { NAME, OPCODE, MASK, CLASS, 0, SME2p2, OPS, QUALS, \ F_STRICT | FLAGS, 0, TIED, NULL } +#define GCIE_INSN(NAME,OPCODE,MASK,OPS,QUALS,FLAGS) \ + { NAME, OPCODE, MASK, ic_system, 0, GCIE, OPS, QUALS, FLAGS, 0, 0, NULL } #define MOPS_CPY_OP1_OP2_PME_INSN(NAME, OPCODE, MASK, FLAGS, CONSTRAINTS) \ MOPS_INSN (NAME, OPCODE, MASK, 0, \ @@ -7480,6 +7482,11 @@ const struct aarch64_opcode aarch64_opcode_table[] = SME2p2_INSN ("fmul", 0xc120e400, 0xff21fc21, sme_size_22_hsd, OP3 (SME_Zdnx2, SME_Znx2, SME_Zmx2), OP_SVE_VVV_HSD, 0, 0), SME2p2_INSN ("fmul", 0xc121e400, 0xff21fc63, sme_size_22_hsd, OP3 (SME_Zdnx4, SME_Znx4, SME_Zmx4), OP_SVE_VVV_HSD, 0, 0), + /* Generalised Interrupt Controller v5 instructions. */ + GCIE_INSN ("gic", 0xd5080000, 0xfff80000, OP2 (GIC, Rd), QL_SRC_X, F_ALIAS), + GCIE_INSN ("gicr", 0xd5080000, 0xfff80000, OP2 (Rd, GICR), QL_DST_X, F_ALIAS), + GCIE_INSN ("gsb", 0xd508001f, 0xfff8001f, OP1 (GSB), QL_IMM_NIL, F_ALIAS), + {0, 0, 0, 0, 0, 0, {}, {}, 0, 0, 0, NULL}, }; @@ -8221,4 +8228,10 @@ const struct aarch64_opcode aarch64_opcode_table[] = "RCPC3_ADDR_PREIND_WB", 0, F(), \ "an address with pre-incrementing with write-back by ammount of stored bytes") \ Y(ADDRESS, rcpc3_addr_offset, "RCPC3_ADDR_OFFSET", 0, F(FLD_Rn,FLD_imm9), \ - "an address with an optional 8-bit signed immediate offset") + "an address with an optional 8-bit signed immediate offset") \ + Y(SYSTEM, sysins_op, "GIC", 0, F(), \ + "Generic Interrupt Controller") \ + Y(SYSTEM, sysins_op, "GICR", 0, F(), \ + "Generic Interrupt Controller") \ + Y(SYSTEM, sysins_op, "GSB", 0, F(), \ + "Generic Interrupt Controller Synchronization Barrier")