From: Dmytro Laktyushkin Date: Mon, 26 Aug 2019 19:04:18 +0000 (-0400) Subject: drm/amd/display: add vtg update after global sync update X-Git-Tag: v5.5-rc1~128^2~26^2~192 X-Git-Url: http://git.ipfire.org/?a=commitdiff_plain;h=a14e9e0292e29939ef078ab7f5a337edcd796ca1;p=thirdparty%2Fkernel%2Flinux.git drm/amd/display: add vtg update after global sync update Global sync update was missing vtg update resulting in underflow if vstartup decreased a significant amount. Signed-off-by: Dmytro Laktyushkin Reviewed-by: Jaehyun Chung Acked-by: Leo Li Signed-off-by: Alex Deucher --- diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c index faaf8841c61ea..4bb5ad19c4cf8 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c +++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c @@ -1361,7 +1361,7 @@ static void dcn20_program_pipe( && !pipe_ctx->top_pipe && !pipe_ctx->prev_odm_pipe) dc->hwss.blank_pixel_data(dc, pipe_ctx, !pipe_ctx->plane_state->visible); - if (pipe_ctx->update_flags.bits.global_sync) + if (pipe_ctx->update_flags.bits.global_sync) { pipe_ctx->stream_res.tg->funcs->program_global_sync( pipe_ctx->stream_res.tg, pipe_ctx->pipe_dlg_param.vready_offset, @@ -1369,6 +1369,10 @@ static void dcn20_program_pipe( pipe_ctx->pipe_dlg_param.vupdate_offset, pipe_ctx->pipe_dlg_param.vupdate_width); + pipe_ctx->stream_res.tg->funcs->set_vtg_params( + pipe_ctx->stream_res.tg, &pipe_ctx->stream->timing); + } + if (pipe_ctx->update_flags.bits.odm) dc->hwss.update_odm(dc, context, pipe_ctx);