From: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
Date: Fri, 5 Mar 2021 13:06:38 +0000 (+0100)
Subject: target/tricore: Fix OPC2_32_RRPW_EXTR for width=0
X-Git-Tag: v6.0.0-rc0~39^2
X-Git-Url: http://git.ipfire.org/?a=commitdiff_plain;h=a21993c7f98862823280d1eb6d3e93cf6267896f;p=thirdparty%2Fqemu.git

target/tricore: Fix OPC2_32_RRPW_EXTR for width=0

if width was 0 we would run into the assertion:

qemu-system-tricore: tcg/tcg-op.c:217: tcg_gen_sari_i32: Assertion `arg2 >= 0 && arg2 < 32' failed.o

The instruction manual specifies undefined behaviour for this case. So
we bring this in line with the golden Infineon simlator 'tsim', which
simply writes 0 to the result in case of width=0.

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
---

diff --git a/target/tricore/translate.c b/target/tricore/translate.c
index 5b7ed70e39a..2a814263de6 100644
--- a/target/tricore/translate.c
+++ b/target/tricore/translate.c
@@ -7000,6 +7000,11 @@ static void decode_rrpw_extract_insert(DisasContext *ctx)
 
     switch (op2) {
     case OPC2_32_RRPW_EXTR:
+        if (width == 0) {
+                tcg_gen_movi_tl(cpu_gpr_d[r3], 0);
+                break;
+        }
+
         if (pos + width <= 32) {
             /* optimize special cases */
             if ((pos == 0) && (width == 8)) {