From: Dave Airlie Date: Thu, 12 Aug 2021 01:20:16 +0000 (+1000) Subject: Merge tag 'drm-intel-next-2021-08-10-1' of git://anongit.freedesktop.org/drm/drm... X-Git-Tag: v5.15-rc1~148^2~9 X-Git-Url: http://git.ipfire.org/?a=commitdiff_plain;h=a22c074fd1dd52a8b41dd6789220409b64093e9c;p=thirdparty%2Flinux.git Merge tag 'drm-intel-next-2021-08-10-1' of git://anongit.freedesktop.org/drm/drm-intel into drm-next drm/i915 changes for v5.15: Features: - Basic DG2 platform enabling (Matt, Animesh, Gwan-gyeong, José) - Add PSF GV point support for display bandwidth calculation (Stan) - Add platform release id version support (Lucas) - Add support for forcing DSC BPP for testing (Vandita, Patnana) Refactoring and cleanups: - Remove CNL support completely (Lucas) - Revid/stepping cleanup (Matt, Anusha) - Make display stepping check upper bounds exclusive (Matt) - Remove old GEN macros (Lucas) - Refactor DG1 interrupt handler (Paulo) - Refactor DMC stepping info (Anusha) Fixes: - Fix XELPD color capability reporting; it's not yet enabled (Uma) - Fix DG1 memory bandwidth computation (Clint) - Fix mux on certain HP laptops (Kai-Heng) - Various display workarounds (José, Matt, Imre) - Fix error state dumps wrt SFC_DONE (Matt) - Fix DG1 and XEPLD audio power domains (Anshuman) - Fix ADL-P and ADL-S ddi buf translation tables (Matt) - Fix DP/HDMI modeset sequences causing issues on ADL-P (José) - PSR2 fixes (José) - Fix DP MST modeset with FEC on TGL+ - Fix MBUS DBOX A credits on ADL-P (José) - Fix DP PHY test training set programming (Khaled) - Fix dgfx pcode uncore init done wait (Badal) - Fix DSC disable fuse check on GLK (Lucas) - Fix shared dpll mismatch for bigjoiner secondary pipe (Manasi) - Fix ADL-P underrun recovery (Matt) - Fix permissions on FEC support debugfs file (Vandita) Misc: - Backmerge drm-next (Rodrigo) - Bump RKL and TGL DMC firmware version (Anusha) Signed-off-by: Dave Airlie # Conflicts: # drivers/gpu/drm/i915/i915_drv.h # drivers/gpu/drm/i915/intel_device_info.h From: Jani Nikula Link: https://patchwork.freedesktop.org/patch/msgid/87a6lpo1a9.fsf@intel.com --- a22c074fd1dd52a8b41dd6789220409b64093e9c diff --cc drivers/gpu/drm/i915/display/intel_dpll_mgr.c index dfc31b6828484,94718c5732832..5c91d125a3371 --- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c +++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c @@@ -2586,88 -2433,8 +2433,8 @@@ static void icl_wrpll_params_populate(s params->dco_fraction = dco & 0x7fff; } - static bool - __cnl_ddi_calculate_wrpll(struct intel_crtc_state *crtc_state, - struct skl_wrpll_params *wrpll_params, - int ref_clock) - { - u32 afe_clock = crtc_state->port_clock * 5; - u32 dco_min = 7998000; - u32 dco_max = 10000000; - u32 dco_mid = (dco_min + dco_max) / 2; - static const int dividers[] = { 2, 4, 6, 8, 10, 12, 14, 16, - 18, 20, 24, 28, 30, 32, 36, 40, - 42, 44, 48, 50, 52, 54, 56, 60, - 64, 66, 68, 70, 72, 76, 78, 80, - 84, 88, 90, 92, 96, 98, 100, 102, - 3, 5, 7, 9, 15, 21 }; - u32 dco, best_dco = 0, dco_centrality = 0; - u32 best_dco_centrality = U32_MAX; /* Spec meaning of 999999 MHz */ - int d, best_div = 0, pdiv = 0, qdiv = 0, kdiv = 0; - - for (d = 0; d < ARRAY_SIZE(dividers); d++) { - dco = afe_clock * dividers[d]; - - if ((dco <= dco_max) && (dco >= dco_min)) { - dco_centrality = abs(dco - dco_mid); - - if (dco_centrality < best_dco_centrality) { - best_dco_centrality = dco_centrality; - best_div = dividers[d]; - best_dco = dco; - } - } - } - - if (best_div == 0) - return false; - - cnl_wrpll_get_multipliers(best_div, &pdiv, &qdiv, &kdiv); - cnl_wrpll_params_populate(wrpll_params, best_dco, ref_clock, - pdiv, qdiv, kdiv); - - return true; - } - - static bool - cnl_ddi_calculate_wrpll(struct intel_crtc_state *crtc_state, - struct skl_wrpll_params *wrpll_params) - { - struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev); - - return __cnl_ddi_calculate_wrpll(crtc_state, wrpll_params, - i915->dpll.ref_clks.nssc); - } - - static bool cnl_ddi_hdmi_pll_dividers(struct intel_crtc_state *crtc_state) - { - u32 cfgcr0, cfgcr1; - struct skl_wrpll_params wrpll_params = { 0, }; - - cfgcr0 = DPLL_CFGCR0_HDMI_MODE; - - if (!cnl_ddi_calculate_wrpll(crtc_state, &wrpll_params)) - return false; - - cfgcr0 |= DPLL_CFGCR0_DCO_FRACTION(wrpll_params.dco_fraction) | - wrpll_params.dco_integer; - - cfgcr1 = DPLL_CFGCR1_QDIV_RATIO(wrpll_params.qdiv_ratio) | - DPLL_CFGCR1_QDIV_MODE(wrpll_params.qdiv_mode) | - DPLL_CFGCR1_KDIV(wrpll_params.kdiv) | - DPLL_CFGCR1_PDIV(wrpll_params.pdiv) | - DPLL_CFGCR1_CENTRAL_FREQ; - - memset(&crtc_state->dpll_hw_state, 0, - sizeof(crtc_state->dpll_hw_state)); - - crtc_state->dpll_hw_state.cfgcr0 = cfgcr0; - crtc_state->dpll_hw_state.cfgcr1 = cfgcr1; - return true; - } - /* - * Display WA #22010492432: ehl, tgl + * Display WA #22010492432: ehl, tgl, adl-p * Program half of the nominal DCO divider fraction value. */ static bool diff --cc drivers/gpu/drm/i915/i915_drv.h index b619f4843b151,6ac90ccbee0b6..005b1cec70075 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h @@@ -1296,8 -1248,10 +1303,8 @@@ static inline struct drm_i915_private * #define INTEL_DEVID(dev_priv) (RUNTIME_INFO(dev_priv)->device_id) - #define IP_VER(ver, rel) ((ver) << 8 | (rel)) + #define IP_VER(ver, rel) ((ver) << 8 | (rel)) -#define IP_VER(ver, rel) ((ver) << 8 | (rel)) - #define GRAPHICS_VER(i915) (INTEL_INFO(i915)->graphics_ver) #define GRAPHICS_VER_FULL(i915) IP_VER(INTEL_INFO(i915)->graphics_ver, \ INTEL_INFO(i915)->graphics_rel) diff --cc drivers/gpu/drm/i915/intel_device_info.h index f88be11a35704,ef1eecd259e0a..d328bb95c49bf --- a/drivers/gpu/drm/i915/intel_device_info.h +++ b/drivers/gpu/drm/i915/intel_device_info.h @@@ -133,8 -131,6 +131,7 @@@ enum intel_ppgtt_type func(has_llc); \ func(has_logical_ring_contexts); \ func(has_logical_ring_elsq); \ - func(has_master_unit_irq); \ + func(has_mslices); \ func(has_pooled_eu); \ func(has_rc6); \ func(has_rc6p); \ diff --cc drivers/gpu/drm/i915/intel_pm.c index 7a4c31e783c1b,197169f012260..65bc3709f54c5 --- a/drivers/gpu/drm/i915/intel_pm.c +++ b/drivers/gpu/drm/i915/intel_pm.c @@@ -7345,21 -7463,23 +7463,21 @@@ static void icl_init_clock_gating(struc intel_uncore_write(&dev_priv->uncore, ILK_DPFC_CHICKEN, ILK_DPFC_CHICKEN_COMP_DUMMY_PIXEL); - /* This is not an Wa. Enable to reduce Sampler power */ - intel_uncore_write(&dev_priv->uncore, GEN10_DFR_RATIO_EN_AND_CHICKEN, - intel_uncore_read(&dev_priv->uncore, GEN10_DFR_RATIO_EN_AND_CHICKEN) & ~DFR_DISABLE); - /*Wa_14010594013:icl, ehl */ intel_uncore_rmw(&dev_priv->uncore, GEN8_CHICKEN_DCPR_1, - 0, CNL_DELAY_PMRSP); + 0, ICL_DELAY_PMRSP); } static void gen12lp_init_clock_gating(struct drm_i915_private *dev_priv) { - /* Wa_1409120013:tgl,rkl,adl_s,dg1 */ - intel_uncore_write(&dev_priv->uncore, ILK_DPFC_CHICKEN, - ILK_DPFC_CHICKEN_COMP_DUMMY_PIXEL); + /* Wa_1409120013:tgl,rkl,adl-s,dg1 */ + if (IS_TIGERLAKE(dev_priv) || IS_ROCKETLAKE(dev_priv) || + IS_ALDERLAKE_S(dev_priv) || IS_DG1(dev_priv)) + intel_uncore_write(&dev_priv->uncore, ILK_DPFC_CHICKEN, + ILK_DPFC_CHICKEN_COMP_DUMMY_PIXEL); /* Wa_1409825376:tgl (pre-prod)*/ - if (IS_TGL_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B1)) + if (IS_TGL_DISPLAY_STEP(dev_priv, STEP_A0, STEP_C0)) intel_uncore_write(&dev_priv->uncore, GEN9_CLKGATE_DIS_3, intel_uncore_read(&dev_priv->uncore, GEN9_CLKGATE_DIS_3) | TGL_VRH_GATING_DIS);