From: Alistair Francis <alistair.francis@wdc.com>
Date: Sat, 1 Feb 2020 01:02:20 +0000 (-0800)
Subject: target/riscv: Extend the SIP CSR to support virtulisation
X-Git-Tag: v5.0.0-rc0~62^2~21
X-Git-Url: http://git.ipfire.org/?a=commitdiff_plain;h=a2e9f57d06279220b1834eca2494e52adae121b8;p=thirdparty%2Fqemu.git

target/riscv: Extend the SIP CSR to support virtulisation

Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Palmer Dabbelt <palmerdabbelt@google.com>
Signed-off-by: Palmer Dabbelt <palmerdabbelt@google.com>
---

diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index 918678789af..2e6700bbebe 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -743,8 +743,19 @@ static int write_sbadaddr(CPURISCVState *env, int csrno, target_ulong val)
 static int rmw_sip(CPURISCVState *env, int csrno, target_ulong *ret_value,
                    target_ulong new_value, target_ulong write_mask)
 {
-    int ret = rmw_mip(env, CSR_MSTATUS, ret_value, new_value,
+    int ret;
+
+    if (riscv_cpu_virt_enabled(env)) {
+        /* Shift the new values to line up with the VS bits */
+        ret = rmw_mip(env, CSR_MSTATUS, ret_value, new_value << 1,
+                      (write_mask & sip_writable_mask) << 1 & env->mideleg);
+        ret &= vsip_writable_mask;
+        ret >>= 1;
+    } else {
+        ret = rmw_mip(env, CSR_MSTATUS, ret_value, new_value,
                       write_mask & env->mideleg & sip_writable_mask);
+    }
+
     *ret_value &= env->mideleg;
     return ret;
 }