From: Greg Kroah-Hartman Date: Tue, 2 Sep 2025 12:34:50 +0000 (+0200) Subject: 6.12-stable patches X-Git-Tag: v5.4.298~5 X-Git-Url: http://git.ipfire.org/?a=commitdiff_plain;h=a3180bc4015330289a46196ef67b35a86ac29346;p=thirdparty%2Fkernel%2Fstable-queue.git 6.12-stable patches added patches: pci-dwc-ensure-that-dw_pcie_wait_for_link-waits-100-ms-after-link-up.patch pci-rename-pcie_reset_config_device_wait_ms-to-pcie_reset_config_wait_ms.patch revert-drm-dp-change-aux-dpcd-probe-address-from-dpcd_rev-to-lane0_1_status.patch thermal-drivers-mediatek-lvts_thermal-add-lvts-commands-and-their-sizes-to-driver-data.patch thermal-drivers-mediatek-lvts_thermal-add-mt7988-lvts-commands.patch thermal-drivers-mediatek-lvts_thermal-change-lvts-commands-array-to-static-const.patch --- diff --git a/queue-6.12/pci-dwc-ensure-that-dw_pcie_wait_for_link-waits-100-ms-after-link-up.patch b/queue-6.12/pci-dwc-ensure-that-dw_pcie_wait_for_link-waits-100-ms-after-link-up.patch new file mode 100644 index 0000000000..a16768fdc1 --- /dev/null +++ b/queue-6.12/pci-dwc-ensure-that-dw_pcie_wait_for_link-waits-100-ms-after-link-up.patch @@ -0,0 +1,49 @@ +From 80dc18a0cba8dea42614f021b20a04354b213d86 Mon Sep 17 00:00:00 2001 +From: Niklas Cassel +Date: Wed, 25 Jun 2025 12:23:51 +0200 +Subject: PCI: dwc: Ensure that dw_pcie_wait_for_link() waits 100 ms after link up + +From: Niklas Cassel + +commit 80dc18a0cba8dea42614f021b20a04354b213d86 upstream. + +As per PCIe r6.0, sec 6.6.1, a Downstream Port that supports Link speeds +greater than 5.0 GT/s, software must wait a minimum of 100 ms after Link +training completes before sending a Configuration Request. + +Add this delay in dw_pcie_wait_for_link(), after the link is reported as +up. The delay will only be performed in the success case where the link +came up. + +DWC glue drivers that have a link up IRQ (drivers that set +use_linkup_irq = true) do not call dw_pcie_wait_for_link(), instead they +perform this delay in their threaded link up IRQ handler. + +Signed-off-by: Niklas Cassel +Signed-off-by: Manivannan Sadhasivam +Reviewed-by: Damien Le Moal +Reviewed-by: Wilfred Mallawa +Link: https://patch.msgid.link/20250625102347.1205584-14-cassel@kernel.org +Signed-off-by: Marek Vasut +Signed-off-by: Greg Kroah-Hartman +--- + drivers/pci/controller/dwc/pcie-designware.c | 8 ++++++++ + 1 file changed, 8 insertions(+) + +--- a/drivers/pci/controller/dwc/pcie-designware.c ++++ b/drivers/pci/controller/dwc/pcie-designware.c +@@ -655,6 +655,14 @@ int dw_pcie_wait_for_link(struct dw_pcie + return -ETIMEDOUT; + } + ++ /* ++ * As per PCIe r6.0, sec 6.6.1, a Downstream Port that supports Link ++ * speeds greater than 5.0 GT/s, software must wait a minimum of 100 ms ++ * after Link training completes before sending a Configuration Request. ++ */ ++ if (pci->max_link_speed > 2) ++ msleep(PCIE_RESET_CONFIG_WAIT_MS); ++ + offset = dw_pcie_find_capability(pci, PCI_CAP_ID_EXP); + val = dw_pcie_readw_dbi(pci, offset + PCI_EXP_LNKSTA); + diff --git a/queue-6.12/pci-rename-pcie_reset_config_device_wait_ms-to-pcie_reset_config_wait_ms.patch b/queue-6.12/pci-rename-pcie_reset_config_device_wait_ms-to-pcie_reset_config_wait_ms.patch new file mode 100644 index 0000000000..bd39afcef0 --- /dev/null +++ b/queue-6.12/pci-rename-pcie_reset_config_device_wait_ms-to-pcie_reset_config_wait_ms.patch @@ -0,0 +1,44 @@ +From 817f989700fddefa56e5e443e7d138018ca6709d Mon Sep 17 00:00:00 2001 +From: Niklas Cassel +Date: Wed, 25 Jun 2025 12:23:47 +0200 +Subject: PCI: Rename PCIE_RESET_CONFIG_DEVICE_WAIT_MS to PCIE_RESET_CONFIG_WAIT_MS + +From: Niklas Cassel + +commit 817f989700fddefa56e5e443e7d138018ca6709d upstream. + +Rename PCIE_RESET_CONFIG_DEVICE_WAIT_MS to PCIE_RESET_CONFIG_WAIT_MS. + +Suggested-by: Bjorn Helgaas +Signed-off-by: Niklas Cassel +Signed-off-by: Manivannan Sadhasivam +Link: https://patch.msgid.link/20250625102347.1205584-10-cassel@kernel.org +Signed-off-by: Marek Vasut +Signed-off-by: Greg Kroah-Hartman +--- + drivers/pci/controller/plda/pcie-starfive.c | 2 +- + drivers/pci/pci.h | 2 +- + 2 files changed, 2 insertions(+), 2 deletions(-) + +--- a/drivers/pci/controller/plda/pcie-starfive.c ++++ b/drivers/pci/controller/plda/pcie-starfive.c +@@ -368,7 +368,7 @@ static int starfive_pcie_host_init(struc + * of 100ms following exit from a conventional reset before + * sending a configuration request to the device. + */ +- msleep(PCIE_RESET_CONFIG_DEVICE_WAIT_MS); ++ msleep(PCIE_RESET_CONFIG_WAIT_MS); + + if (starfive_pcie_host_wait_for_link(pcie)) + dev_info(dev, "port link down\n"); +--- a/drivers/pci/pci.h ++++ b/drivers/pci/pci.h +@@ -57,7 +57,7 @@ + * completes before sending a Configuration Request to the device + * immediately below that Port." + */ +-#define PCIE_RESET_CONFIG_DEVICE_WAIT_MS 100 ++#define PCIE_RESET_CONFIG_WAIT_MS 100 + + /* Message Routing (r[2:0]); PCIe r6.0, sec 2.2.8 */ + #define PCIE_MSG_TYPE_R_RC 0 diff --git a/queue-6.12/revert-drm-dp-change-aux-dpcd-probe-address-from-dpcd_rev-to-lane0_1_status.patch b/queue-6.12/revert-drm-dp-change-aux-dpcd-probe-address-from-dpcd_rev-to-lane0_1_status.patch new file mode 100644 index 0000000000..db9b877ba3 --- /dev/null +++ b/queue-6.12/revert-drm-dp-change-aux-dpcd-probe-address-from-dpcd_rev-to-lane0_1_status.patch @@ -0,0 +1,40 @@ +From imre.deak@intel.com Tue Sep 2 13:50:59 2025 +From: Imre Deak +Date: Thu, 28 Aug 2025 20:49:29 +0300 +Subject: Revert "drm/dp: Change AUX DPCD probe address from DPCD_REV to LANE0_1_STATUS" +To: +Cc: , , Sasha Levin + +From: Imre Deak + +This reverts commit 3c778a98bee16b4c7ba364a0101ee3c399a95b85 which is +commit a40c5d727b8111b5db424a1e43e14a1dcce1e77f upstream. + +The upstream commit a40c5d727b8111b5db424a1e43e14a1dcce1e77f ("drm/dp: +Change AUX DPCD probe address from DPCD_REV to LANE0_1_STATUS") the +reverted commit backported causes a regression, on one eDP panel at +least resulting in display flickering, described in detail at the Link: +below. The issue fixed by the upstream commit will need a different +solution, revert the backport for now. + +Cc: intel-gfx@lists.freedesktop.org +Cc: dri-devel@lists.freedesktop.org +Cc: Sasha Levin +Link: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/14558 +Signed-off-by: Imre Deak +Signed-off-by: Greg Kroah-Hartman +--- + drivers/gpu/drm/display/drm_dp_helper.c | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +--- a/drivers/gpu/drm/display/drm_dp_helper.c ++++ b/drivers/gpu/drm/display/drm_dp_helper.c +@@ -664,7 +664,7 @@ ssize_t drm_dp_dpcd_read(struct drm_dp_a + * monitor doesn't power down exactly after the throw away read. + */ + if (!aux->is_remote) { +- ret = drm_dp_dpcd_probe(aux, DP_LANE0_1_STATUS); ++ ret = drm_dp_dpcd_probe(aux, DP_DPCD_REV); + if (ret < 0) + return ret; + } diff --git a/queue-6.12/series b/queue-6.12/series index 074316ca65..379d4f6db2 100644 --- a/queue-6.12/series +++ b/queue-6.12/series @@ -87,3 +87,9 @@ drm-nouveau-fix-error-path-in-nvkm_gsp_fwsec_v2.patch drm-mediatek-fix-device-node-reference-count-leaks-in-mtk_drm_get_all_drm_priv.patch drm-amd-amdgpu-disable-hwmon-power1_cap-for-gfx-11.0.3-on-vf-mode.patch net-rose-fix-a-typo-in-rose_clear_routes.patch +pci-rename-pcie_reset_config_device_wait_ms-to-pcie_reset_config_wait_ms.patch +pci-dwc-ensure-that-dw_pcie_wait_for_link-waits-100-ms-after-link-up.patch +revert-drm-dp-change-aux-dpcd-probe-address-from-dpcd_rev-to-lane0_1_status.patch +thermal-drivers-mediatek-lvts_thermal-change-lvts-commands-array-to-static-const.patch +thermal-drivers-mediatek-lvts_thermal-add-lvts-commands-and-their-sizes-to-driver-data.patch +thermal-drivers-mediatek-lvts_thermal-add-mt7988-lvts-commands.patch diff --git a/queue-6.12/thermal-drivers-mediatek-lvts_thermal-add-lvts-commands-and-their-sizes-to-driver-data.patch b/queue-6.12/thermal-drivers-mediatek-lvts_thermal-add-lvts-commands-and-their-sizes-to-driver-data.patch new file mode 100644 index 0000000000..3e30c8ec4d --- /dev/null +++ b/queue-6.12/thermal-drivers-mediatek-lvts_thermal-add-lvts-commands-and-their-sizes-to-driver-data.patch @@ -0,0 +1,190 @@ +From 6203a5e6fd090ed05f6d9b92e33bc7e7679a3dd6 Mon Sep 17 00:00:00 2001 +From: Mason Chang +Date: Mon, 26 May 2025 18:26:58 +0800 +Subject: thermal/drivers/mediatek/lvts_thermal: Add lvts commands and their sizes to driver data + +From: Mason Chang + +commit 6203a5e6fd090ed05f6d9b92e33bc7e7679a3dd6 upstream. + +Add LVTS commands and their sizes to driver data in preparation for +adding different commands. + +Signed-off-by: Mason Chang +Link: https://lore.kernel.org/r/20250526102659.30225-3-mason-cw.chang@mediatek.com +Signed-off-by: Daniel Lezcano +Signed-off-by: Daniel Golle +Signed-off-by: Greg Kroah-Hartman +--- + drivers/thermal/mediatek/lvts_thermal.c | 65 +++++++++++++++++++++++++------- + 1 file changed, 52 insertions(+), 13 deletions(-) + +--- a/drivers/thermal/mediatek/lvts_thermal.c ++++ b/drivers/thermal/mediatek/lvts_thermal.c +@@ -92,17 +92,6 @@ + + #define LVTS_MINIMUM_THRESHOLD 20000 + +-static const u32 default_conn_cmds[] = { 0xC103FFFF, 0xC502FF55 }; +-/* +- * Write device mask: 0xC1030000 +- */ +-static const u32 default_init_cmds[] = { +- 0xC1030E01, 0xC1030CFC, 0xC1030A8C, 0xC103098D, 0xC10308F1, +- 0xC10307A6, 0xC10306B8, 0xC1030500, 0xC1030420, 0xC1030300, +- 0xC1030030, 0xC10300F6, 0xC1030050, 0xC1030060, 0xC10300AC, +- 0xC10300FC, 0xC103009D, 0xC10300F1, 0xC10300E1 +-}; +- + static int golden_temp = LVTS_GOLDEN_TEMP_DEFAULT; + static int golden_temp_offset; + +@@ -132,7 +121,11 @@ struct lvts_ctrl_data { + + struct lvts_data { + const struct lvts_ctrl_data *lvts_ctrl; ++ const u32 *conn_cmd; ++ const u32 *init_cmd; + int num_lvts_ctrl; ++ int num_conn_cmd; ++ int num_init_cmd; + int temp_factor; + int temp_offset; + int gt_calib_bit_offset; +@@ -974,9 +967,10 @@ static int lvts_ctrl_set_enable(struct l + + static int lvts_ctrl_connect(struct device *dev, struct lvts_ctrl *lvts_ctrl) + { ++ const struct lvts_data *lvts_data = lvts_ctrl->lvts_data; + u32 id; + +- lvts_write_config(lvts_ctrl, default_conn_cmds, ARRAY_SIZE(default_conn_cmds)); ++ lvts_write_config(lvts_ctrl, lvts_data->conn_cmd, lvts_data->num_conn_cmd); + + /* + * LVTS_ID : Get ID and status of the thermal controller +@@ -995,7 +989,9 @@ static int lvts_ctrl_connect(struct devi + + static int lvts_ctrl_initialize(struct device *dev, struct lvts_ctrl *lvts_ctrl) + { +- lvts_write_config(lvts_ctrl, default_init_cmds, ARRAY_SIZE(default_init_cmds)); ++ const struct lvts_data *lvts_data = lvts_ctrl->lvts_data; ++ ++ lvts_write_config(lvts_ctrl, lvts_data->init_cmd, lvts_data->num_init_cmd); + + return 0; + } +@@ -1424,6 +1420,17 @@ static int lvts_resume(struct device *de + return 0; + } + ++static const u32 default_conn_cmds[] = { 0xC103FFFF, 0xC502FF55 }; ++/* ++ * Write device mask: 0xC1030000 ++ */ ++static const u32 default_init_cmds[] = { ++ 0xC1030E01, 0xC1030CFC, 0xC1030A8C, 0xC103098D, 0xC10308F1, ++ 0xC10307A6, 0xC10306B8, 0xC1030500, 0xC1030420, 0xC1030300, ++ 0xC1030030, 0xC10300F6, 0xC1030050, 0xC1030060, 0xC10300AC, ++ 0xC10300FC, 0xC103009D, 0xC10300F1, 0xC10300E1 ++}; ++ + /* + * The MT8186 calibration data is stored as packed 3-byte little-endian + * values using a weird layout that makes sense only when viewed as a 32-bit +@@ -1718,7 +1725,11 @@ static const struct lvts_ctrl_data mt819 + + static const struct lvts_data mt7988_lvts_ap_data = { + .lvts_ctrl = mt7988_lvts_ap_data_ctrl, ++ .conn_cmd = default_conn_cmds, ++ .init_cmd = default_init_cmds, + .num_lvts_ctrl = ARRAY_SIZE(mt7988_lvts_ap_data_ctrl), ++ .num_conn_cmd = ARRAY_SIZE(default_conn_cmds), ++ .num_init_cmd = ARRAY_SIZE(default_init_cmds), + .temp_factor = LVTS_COEFF_A_MT7988, + .temp_offset = LVTS_COEFF_B_MT7988, + .gt_calib_bit_offset = 24, +@@ -1726,7 +1737,11 @@ static const struct lvts_data mt7988_lvt + + static const struct lvts_data mt8186_lvts_data = { + .lvts_ctrl = mt8186_lvts_data_ctrl, ++ .conn_cmd = default_conn_cmds, ++ .init_cmd = default_init_cmds, + .num_lvts_ctrl = ARRAY_SIZE(mt8186_lvts_data_ctrl), ++ .num_conn_cmd = ARRAY_SIZE(default_conn_cmds), ++ .num_init_cmd = ARRAY_SIZE(default_init_cmds), + .temp_factor = LVTS_COEFF_A_MT7988, + .temp_offset = LVTS_COEFF_B_MT7988, + .gt_calib_bit_offset = 24, +@@ -1735,7 +1750,11 @@ static const struct lvts_data mt8186_lvt + + static const struct lvts_data mt8188_lvts_mcu_data = { + .lvts_ctrl = mt8188_lvts_mcu_data_ctrl, ++ .conn_cmd = default_conn_cmds, ++ .init_cmd = default_init_cmds, + .num_lvts_ctrl = ARRAY_SIZE(mt8188_lvts_mcu_data_ctrl), ++ .num_conn_cmd = ARRAY_SIZE(default_conn_cmds), ++ .num_init_cmd = ARRAY_SIZE(default_init_cmds), + .temp_factor = LVTS_COEFF_A_MT8195, + .temp_offset = LVTS_COEFF_B_MT8195, + .gt_calib_bit_offset = 20, +@@ -1744,7 +1763,11 @@ static const struct lvts_data mt8188_lvt + + static const struct lvts_data mt8188_lvts_ap_data = { + .lvts_ctrl = mt8188_lvts_ap_data_ctrl, ++ .conn_cmd = default_conn_cmds, ++ .init_cmd = default_init_cmds, + .num_lvts_ctrl = ARRAY_SIZE(mt8188_lvts_ap_data_ctrl), ++ .num_conn_cmd = ARRAY_SIZE(default_conn_cmds), ++ .num_init_cmd = ARRAY_SIZE(default_init_cmds), + .temp_factor = LVTS_COEFF_A_MT8195, + .temp_offset = LVTS_COEFF_B_MT8195, + .gt_calib_bit_offset = 20, +@@ -1753,7 +1776,11 @@ static const struct lvts_data mt8188_lvt + + static const struct lvts_data mt8192_lvts_mcu_data = { + .lvts_ctrl = mt8192_lvts_mcu_data_ctrl, ++ .conn_cmd = default_conn_cmds, ++ .init_cmd = default_init_cmds, + .num_lvts_ctrl = ARRAY_SIZE(mt8192_lvts_mcu_data_ctrl), ++ .num_conn_cmd = ARRAY_SIZE(default_conn_cmds), ++ .num_init_cmd = ARRAY_SIZE(default_init_cmds), + .temp_factor = LVTS_COEFF_A_MT8195, + .temp_offset = LVTS_COEFF_B_MT8195, + .gt_calib_bit_offset = 24, +@@ -1762,7 +1789,11 @@ static const struct lvts_data mt8192_lvt + + static const struct lvts_data mt8192_lvts_ap_data = { + .lvts_ctrl = mt8192_lvts_ap_data_ctrl, ++ .conn_cmd = default_conn_cmds, ++ .init_cmd = default_init_cmds, + .num_lvts_ctrl = ARRAY_SIZE(mt8192_lvts_ap_data_ctrl), ++ .num_conn_cmd = ARRAY_SIZE(default_conn_cmds), ++ .num_init_cmd = ARRAY_SIZE(default_init_cmds), + .temp_factor = LVTS_COEFF_A_MT8195, + .temp_offset = LVTS_COEFF_B_MT8195, + .gt_calib_bit_offset = 24, +@@ -1771,7 +1802,11 @@ static const struct lvts_data mt8192_lvt + + static const struct lvts_data mt8195_lvts_mcu_data = { + .lvts_ctrl = mt8195_lvts_mcu_data_ctrl, ++ .conn_cmd = default_conn_cmds, ++ .init_cmd = default_init_cmds, + .num_lvts_ctrl = ARRAY_SIZE(mt8195_lvts_mcu_data_ctrl), ++ .num_conn_cmd = ARRAY_SIZE(default_conn_cmds), ++ .num_init_cmd = ARRAY_SIZE(default_init_cmds), + .temp_factor = LVTS_COEFF_A_MT8195, + .temp_offset = LVTS_COEFF_B_MT8195, + .gt_calib_bit_offset = 24, +@@ -1780,7 +1815,11 @@ static const struct lvts_data mt8195_lvt + + static const struct lvts_data mt8195_lvts_ap_data = { + .lvts_ctrl = mt8195_lvts_ap_data_ctrl, ++ .conn_cmd = default_conn_cmds, ++ .init_cmd = default_init_cmds, + .num_lvts_ctrl = ARRAY_SIZE(mt8195_lvts_ap_data_ctrl), ++ .num_conn_cmd = ARRAY_SIZE(default_conn_cmds), ++ .num_init_cmd = ARRAY_SIZE(default_init_cmds), + .temp_factor = LVTS_COEFF_A_MT8195, + .temp_offset = LVTS_COEFF_B_MT8195, + .gt_calib_bit_offset = 24, diff --git a/queue-6.12/thermal-drivers-mediatek-lvts_thermal-add-mt7988-lvts-commands.patch b/queue-6.12/thermal-drivers-mediatek-lvts_thermal-add-mt7988-lvts-commands.patch new file mode 100644 index 0000000000..9d9cc6bc1d --- /dev/null +++ b/queue-6.12/thermal-drivers-mediatek-lvts_thermal-add-mt7988-lvts-commands.patch @@ -0,0 +1,61 @@ +From 685a755089f95b7e205c0202567d9a647f9de096 Mon Sep 17 00:00:00 2001 +From: Mason Chang +Date: Mon, 26 May 2025 18:26:59 +0800 +Subject: thermal/drivers/mediatek/lvts_thermal: Add mt7988 lvts commands + +From: Mason Chang + +commit 685a755089f95b7e205c0202567d9a647f9de096 upstream. + +These commands are necessary to avoid severely abnormal and inaccurate +temperature readings that are caused by using the default commands. + +Signed-off-by: Mason Chang +Link: https://lore.kernel.org/r/20250526102659.30225-4-mason-cw.chang@mediatek.com +Signed-off-by: Daniel Lezcano +Signed-off-by: Daniel Golle +Signed-off-by: Greg Kroah-Hartman +--- + drivers/thermal/mediatek/lvts_thermal.c | 16 ++++++++++++---- + 1 file changed, 12 insertions(+), 4 deletions(-) + +--- a/drivers/thermal/mediatek/lvts_thermal.c ++++ b/drivers/thermal/mediatek/lvts_thermal.c +@@ -1421,6 +1421,8 @@ static int lvts_resume(struct device *de + } + + static const u32 default_conn_cmds[] = { 0xC103FFFF, 0xC502FF55 }; ++static const u32 mt7988_conn_cmds[] = { 0xC103FFFF, 0xC502FC55 }; ++ + /* + * Write device mask: 0xC1030000 + */ +@@ -1431,6 +1433,12 @@ static const u32 default_init_cmds[] = { + 0xC10300FC, 0xC103009D, 0xC10300F1, 0xC10300E1 + }; + ++static const u32 mt7988_init_cmds[] = { ++ 0xC1030300, 0xC1030420, 0xC1030500, 0xC10307A6, 0xC1030CFC, ++ 0xC1030A8C, 0xC103098D, 0xC10308F1, 0xC1030B04, 0xC1030E01, ++ 0xC10306B8 ++}; ++ + /* + * The MT8186 calibration data is stored as packed 3-byte little-endian + * values using a weird layout that makes sense only when viewed as a 32-bit +@@ -1725,11 +1733,11 @@ static const struct lvts_ctrl_data mt819 + + static const struct lvts_data mt7988_lvts_ap_data = { + .lvts_ctrl = mt7988_lvts_ap_data_ctrl, +- .conn_cmd = default_conn_cmds, +- .init_cmd = default_init_cmds, ++ .conn_cmd = mt7988_conn_cmds, ++ .init_cmd = mt7988_init_cmds, + .num_lvts_ctrl = ARRAY_SIZE(mt7988_lvts_ap_data_ctrl), +- .num_conn_cmd = ARRAY_SIZE(default_conn_cmds), +- .num_init_cmd = ARRAY_SIZE(default_init_cmds), ++ .num_conn_cmd = ARRAY_SIZE(mt7988_conn_cmds), ++ .num_init_cmd = ARRAY_SIZE(mt7988_init_cmds), + .temp_factor = LVTS_COEFF_A_MT7988, + .temp_offset = LVTS_COEFF_B_MT7988, + .gt_calib_bit_offset = 24, diff --git a/queue-6.12/thermal-drivers-mediatek-lvts_thermal-change-lvts-commands-array-to-static-const.patch b/queue-6.12/thermal-drivers-mediatek-lvts_thermal-change-lvts-commands-array-to-static-const.patch new file mode 100644 index 0000000000..a160c62b07 --- /dev/null +++ b/queue-6.12/thermal-drivers-mediatek-lvts_thermal-change-lvts-commands-array-to-static-const.patch @@ -0,0 +1,81 @@ +From c5d5a72c01f7faabe7cc0fd63942c18372101daf Mon Sep 17 00:00:00 2001 +From: Mason Chang +Date: Mon, 26 May 2025 18:26:57 +0800 +Subject: thermal/drivers/mediatek/lvts_thermal: Change lvts commands array to static const + +From: Mason Chang + +commit c5d5a72c01f7faabe7cc0fd63942c18372101daf upstream. + +Change the LVTS commands array to static const in preparation for +adding different commands. + +Signed-off-by: Mason Chang +Link: https://lore.kernel.org/r/20250526102659.30225-2-mason-cw.chang@mediatek.com +Signed-off-by: Daniel Lezcano +Signed-off-by: Daniel Golle +Signed-off-by: Greg Kroah-Hartman +--- + drivers/thermal/mediatek/lvts_thermal.c | 29 +++++++++++++++-------------- + 1 file changed, 15 insertions(+), 14 deletions(-) + +--- a/drivers/thermal/mediatek/lvts_thermal.c ++++ b/drivers/thermal/mediatek/lvts_thermal.c +@@ -92,6 +92,17 @@ + + #define LVTS_MINIMUM_THRESHOLD 20000 + ++static const u32 default_conn_cmds[] = { 0xC103FFFF, 0xC502FF55 }; ++/* ++ * Write device mask: 0xC1030000 ++ */ ++static const u32 default_init_cmds[] = { ++ 0xC1030E01, 0xC1030CFC, 0xC1030A8C, 0xC103098D, 0xC10308F1, ++ 0xC10307A6, 0xC10306B8, 0xC1030500, 0xC1030420, 0xC1030300, ++ 0xC1030030, 0xC10300F6, 0xC1030050, 0xC1030060, 0xC10300AC, ++ 0xC10300FC, 0xC103009D, 0xC10300F1, 0xC10300E1 ++}; ++ + static int golden_temp = LVTS_GOLDEN_TEMP_DEFAULT; + static int golden_temp_offset; + +@@ -880,7 +891,7 @@ static void lvts_ctrl_monitor_enable(str + * each write in the configuration register must be separated by a + * delay of 2 us. + */ +-static void lvts_write_config(struct lvts_ctrl *lvts_ctrl, u32 *cmds, int nr_cmds) ++static void lvts_write_config(struct lvts_ctrl *lvts_ctrl, const u32 *cmds, int nr_cmds) + { + int i; + +@@ -963,9 +974,9 @@ static int lvts_ctrl_set_enable(struct l + + static int lvts_ctrl_connect(struct device *dev, struct lvts_ctrl *lvts_ctrl) + { +- u32 id, cmds[] = { 0xC103FFFF, 0xC502FF55 }; ++ u32 id; + +- lvts_write_config(lvts_ctrl, cmds, ARRAY_SIZE(cmds)); ++ lvts_write_config(lvts_ctrl, default_conn_cmds, ARRAY_SIZE(default_conn_cmds)); + + /* + * LVTS_ID : Get ID and status of the thermal controller +@@ -984,17 +995,7 @@ static int lvts_ctrl_connect(struct devi + + static int lvts_ctrl_initialize(struct device *dev, struct lvts_ctrl *lvts_ctrl) + { +- /* +- * Write device mask: 0xC1030000 +- */ +- u32 cmds[] = { +- 0xC1030E01, 0xC1030CFC, 0xC1030A8C, 0xC103098D, 0xC10308F1, +- 0xC10307A6, 0xC10306B8, 0xC1030500, 0xC1030420, 0xC1030300, +- 0xC1030030, 0xC10300F6, 0xC1030050, 0xC1030060, 0xC10300AC, +- 0xC10300FC, 0xC103009D, 0xC10300F1, 0xC10300E1 +- }; +- +- lvts_write_config(lvts_ctrl, cmds, ARRAY_SIZE(cmds)); ++ lvts_write_config(lvts_ctrl, default_init_cmds, ARRAY_SIZE(default_init_cmds)); + + return 0; + }