From: Greg Kroah-Hartman Date: Sat, 13 May 2023 07:26:23 +0000 (+0900) Subject: 6.3-stable patches X-Git-Tag: v4.14.315~85 X-Git-Url: http://git.ipfire.org/?a=commitdiff_plain;h=a37b45e53e4bee5ddf70d620703138058980ea9d;p=thirdparty%2Fkernel%2Fstable-queue.git 6.3-stable patches added patches: drm-amd-display-add-null-plane_state-check-for-cursor-disable-logic.patch drm-amd-display-change-default-z8-watermark-values.patch drm-amd-display-enforce-60us-prefetch-for-200mhz-dcfclk-modes.patch drm-amd-display-filter-out-invalid-bits-in-pipe_fuses.patch drm-amd-display-fix-4to1-mpc-black-screen-with-dpp-rco.patch drm-amd-display-fix-access-hdcp_workqueue-assert.patch drm-amd-display-fix-flickering-caused-by-s-g-mode.patch drm-amd-pm-avoid-potential-ubsan-issue-on-legacy-asics.patch drm-amd-pm-parse-pp_handle-under-appropriate-conditions.patch drm-amdgpu-change-gfx-11.0.4-external_id-range.patch drm-amdgpu-disable-sdma-ecc-irq-only-when-sdma-ras-is-enabled-in-suspend.patch drm-amdgpu-drop-gfx_v11_0_cp_ecc_error_irq_funcs.patch drm-amdgpu-drop-redundant-sched-job-cleanup-when-cs-is-aborted.patch drm-amdgpu-fix-amdgpu_irq_put-call-trace-in-gmc_v10_0_hw_fini.patch drm-amdgpu-fix-amdgpu_irq_put-call-trace-in-gmc_v11_0_hw_fini.patch drm-amdgpu-fix-an-amdgpu_irq_put-issue-in-gmc_v9_0_hw_fini.patch drm-amdgpu-fix-vram-recover-doesn-t-work-after-whole-gpu-reset-v2.patch drm-amdgpu-gfx-disable-gfx9-cp_ecc_error_irq-only-when-enabling-legacy-gfx-ras.patch drm-amdgpu-jpeg-remove-harvest-checking-for-jpeg3.patch --- diff --git a/queue-6.3/drm-amd-display-add-null-plane_state-check-for-cursor-disable-logic.patch b/queue-6.3/drm-amd-display-add-null-plane_state-check-for-cursor-disable-logic.patch new file mode 100644 index 00000000000..0d5c53f3e47 --- /dev/null +++ b/queue-6.3/drm-amd-display-add-null-plane_state-check-for-cursor-disable-logic.patch @@ -0,0 +1,43 @@ +From d29fb7baab09b6a1dc484c9c67933253883e770a Mon Sep 17 00:00:00 2001 +From: Nicholas Kazlauskas +Date: Sat, 11 Mar 2023 09:11:29 -0500 +Subject: drm/amd/display: Add NULL plane_state check for cursor disable logic + +From: Nicholas Kazlauskas + +commit d29fb7baab09b6a1dc484c9c67933253883e770a upstream. + +[Why] +While scanning the top_pipe connections we can run into a case where +the bottom pipe is still connected to a top_pipe but with a NULL +plane_state. + +[How] +Treat a NULL plane_state the same as the plane being invisible for +pipe cursor disable logic. + +Cc: stable@vger.kernel.org +Cc: Mario Limonciello +Reviewed-by: Charlene Liu +Acked-by: Qingqing Zhuo +Signed-off-by: Nicholas Kazlauskas +Tested-by: Daniel Wheeler +Signed-off-by: Alex Deucher +Signed-off-by: Greg Kroah-Hartman +--- + drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c | 4 +++- + 1 file changed, 3 insertions(+), 1 deletion(-) + +--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c ++++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c +@@ -3385,7 +3385,9 @@ static bool dcn10_can_pipe_disable_curso + for (test_pipe = pipe_ctx->top_pipe; test_pipe; + test_pipe = test_pipe->top_pipe) { + // Skip invisible layer and pipe-split plane on same layer +- if (!test_pipe->plane_state->visible || test_pipe->plane_state->layer_index == cur_layer) ++ if (!test_pipe->plane_state || ++ !test_pipe->plane_state->visible || ++ test_pipe->plane_state->layer_index == cur_layer) + continue; + + r2 = test_pipe->plane_res.scl_data.recout; diff --git a/queue-6.3/drm-amd-display-change-default-z8-watermark-values.patch b/queue-6.3/drm-amd-display-change-default-z8-watermark-values.patch new file mode 100644 index 00000000000..7636c152cfe --- /dev/null +++ b/queue-6.3/drm-amd-display-change-default-z8-watermark-values.patch @@ -0,0 +1,38 @@ +From 8f586cc16c1fc3c2202c9d54563db8c7ed365f82 Mon Sep 17 00:00:00 2001 +From: Leo Chen +Date: Thu, 13 Apr 2023 17:34:24 -0400 +Subject: drm/amd/display: Change default Z8 watermark values + +From: Leo Chen + +commit 8f586cc16c1fc3c2202c9d54563db8c7ed365f82 upstream. + +[Why & How] +Previous Z8 watermark values were causing flickering and OTC underflow. +Updating Z8 watermark values based on the measurement. + +Reviewed-by: Nicholas Kazlauskas +Cc: Mario Limonciello +Cc: Alex Deucher +Cc: stable@vger.kernel.org +Acked-by: Alan Liu +Signed-off-by: Leo Chen +Signed-off-by: Alex Deucher +Signed-off-by: Greg Kroah-Hartman +--- + drivers/gpu/drm/amd/display/dc/dml/dcn314/dcn314_fpu.c | 4 ++-- + 1 file changed, 2 insertions(+), 2 deletions(-) + +--- a/drivers/gpu/drm/amd/display/dc/dml/dcn314/dcn314_fpu.c ++++ b/drivers/gpu/drm/amd/display/dc/dml/dcn314/dcn314_fpu.c +@@ -149,8 +149,8 @@ struct _vcs_dpi_soc_bounding_box_st dcn3 + .num_states = 5, + .sr_exit_time_us = 16.5, + .sr_enter_plus_exit_time_us = 18.5, +- .sr_exit_z8_time_us = 210.0, +- .sr_enter_plus_exit_z8_time_us = 310.0, ++ .sr_exit_z8_time_us = 268.0, ++ .sr_enter_plus_exit_z8_time_us = 393.0, + .writeback_latency_us = 12.0, + .dram_channel_width_bytes = 4, + .round_trip_ping_latency_dcfclk_cycles = 106, diff --git a/queue-6.3/drm-amd-display-enforce-60us-prefetch-for-200mhz-dcfclk-modes.patch b/queue-6.3/drm-amd-display-enforce-60us-prefetch-for-200mhz-dcfclk-modes.patch new file mode 100644 index 00000000000..88c42c0f488 --- /dev/null +++ b/queue-6.3/drm-amd-display-enforce-60us-prefetch-for-200mhz-dcfclk-modes.patch @@ -0,0 +1,64 @@ +From b504f99ccaa64da364443431e388ecf30b604e38 Mon Sep 17 00:00:00 2001 +From: Alvin Lee +Date: Thu, 27 Apr 2023 15:10:13 -0400 +Subject: drm/amd/display: Enforce 60us prefetch for 200Mhz DCFCLK modes + +From: Alvin Lee + +commit b504f99ccaa64da364443431e388ecf30b604e38 upstream. + +[Description] +- Due to bandwidth / arbitration issues at 200Mhz DCFCLK, + we want to enforce minimum 60us of prefetch to avoid + intermittent underflow issues +- Since 60us prefetch is already enforced for UCLK DPM0, + and many DCFCLK's > 200Mhz are mapped to UCLK DPM1, in + theory there should not be any UCLK DPM regressions by + enforcing greater prefetch + +Reviewed-by: Nevenko Stupar +Reviewed-by: Jun Lei +Cc: Mario Limonciello +Cc: Alex Deucher +Cc: stable@vger.kernel.org +Acked-by: Alex Hung +Signed-off-by: Alvin Lee +Tested-by: Daniel Wheeler +Signed-off-by: Alex Deucher +Signed-off-by: Greg Kroah-Hartman +--- + drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c | 5 +++-- + drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.h | 1 + + 2 files changed, 4 insertions(+), 2 deletions(-) + +--- a/drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c ++++ b/drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c +@@ -810,7 +810,8 @@ static void DISPCLKDPPCLKDCFCLKDeepSleep + v->SwathHeightY[k], + v->SwathHeightC[k], + TWait, +- v->DRAMSpeedPerState[mode_lib->vba.VoltageLevel] <= MEM_STROBE_FREQ_MHZ ? ++ (v->DRAMSpeedPerState[mode_lib->vba.VoltageLevel] <= MEM_STROBE_FREQ_MHZ || ++ v->DCFCLKPerState[mode_lib->vba.VoltageLevel] <= MIN_DCFCLK_FREQ_MHZ) ? + mode_lib->vba.ip.min_prefetch_in_strobe_us : 0, + /* Output */ + &v->DSTXAfterScaler[k], +@@ -3309,7 +3310,7 @@ void dml32_ModeSupportAndSystemConfigura + v->swath_width_chroma_ub_this_state[k], + v->SwathHeightYThisState[k], + v->SwathHeightCThisState[k], v->TWait, +- v->DRAMSpeedPerState[i] <= MEM_STROBE_FREQ_MHZ ? ++ (v->DRAMSpeedPerState[i] <= MEM_STROBE_FREQ_MHZ || v->DCFCLKState[i][j] <= MIN_DCFCLK_FREQ_MHZ) ? + mode_lib->vba.ip.min_prefetch_in_strobe_us : 0, + + /* Output */ +--- a/drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.h ++++ b/drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.h +@@ -53,6 +53,7 @@ + #define BPP_BLENDED_PIPE 0xffffffff + + #define MEM_STROBE_FREQ_MHZ 1600 ++#define MIN_DCFCLK_FREQ_MHZ 200 + #define MEM_STROBE_MAX_DELIVERY_TIME_US 60.0 + + struct display_mode_lib; diff --git a/queue-6.3/drm-amd-display-filter-out-invalid-bits-in-pipe_fuses.patch b/queue-6.3/drm-amd-display-filter-out-invalid-bits-in-pipe_fuses.patch new file mode 100644 index 00000000000..17d14347d1b --- /dev/null +++ b/queue-6.3/drm-amd-display-filter-out-invalid-bits-in-pipe_fuses.patch @@ -0,0 +1,80 @@ +From 682439fffad9fa9a38d37dd1b1318e9374232213 Mon Sep 17 00:00:00 2001 +From: Samson Tam +Date: Wed, 19 Apr 2023 18:17:14 -0400 +Subject: drm/amd/display: filter out invalid bits in pipe_fuses + +From: Samson Tam + +commit 682439fffad9fa9a38d37dd1b1318e9374232213 upstream. + +[Why] +Reading pipe_fuses from register may have invalid bits set, which may + affect the num_pipes erroneously. + +[How] +Add read_pipes_fuses() call and filter bits based on expected number + of pipes. + +Reviewed-by: Alvin Lee +Acked-by: Alan Liu +Signed-off-by: Samson Tam +Signed-off-by: Alex Deucher +Cc: stable@vger.kernel.org # 6.1.x +Signed-off-by: Greg Kroah-Hartman +--- + drivers/gpu/drm/amd/display/dc/dcn32/dcn32_resource.c | 10 +++++++++- + drivers/gpu/drm/amd/display/dc/dcn321/dcn321_resource.c | 10 +++++++++- + 2 files changed, 18 insertions(+), 2 deletions(-) + +--- a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_resource.c ++++ b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_resource.c +@@ -2077,6 +2077,14 @@ static struct resource_funcs dcn32_res_p + .restore_mall_state = dcn32_restore_mall_state, + }; + ++static uint32_t read_pipe_fuses(struct dc_context *ctx) ++{ ++ uint32_t value = REG_READ(CC_DC_PIPE_DIS); ++ /* DCN32 support max 4 pipes */ ++ value = value & 0xf; ++ return value; ++} ++ + + static bool dcn32_resource_construct( + uint8_t num_virtual_links, +@@ -2119,7 +2127,7 @@ static bool dcn32_resource_construct( + pool->base.res_cap = &res_cap_dcn32; + /* max number of pipes for ASIC before checking for pipe fuses */ + num_pipes = pool->base.res_cap->num_timing_generator; +- pipe_fuses = REG_READ(CC_DC_PIPE_DIS); ++ pipe_fuses = read_pipe_fuses(ctx); + + for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) + if (pipe_fuses & 1 << i) +--- a/drivers/gpu/drm/amd/display/dc/dcn321/dcn321_resource.c ++++ b/drivers/gpu/drm/amd/display/dc/dcn321/dcn321_resource.c +@@ -1626,6 +1626,14 @@ static struct resource_funcs dcn321_res_ + .restore_mall_state = dcn32_restore_mall_state, + }; + ++static uint32_t read_pipe_fuses(struct dc_context *ctx) ++{ ++ uint32_t value = REG_READ(CC_DC_PIPE_DIS); ++ /* DCN321 support max 4 pipes */ ++ value = value & 0xf; ++ return value; ++} ++ + + static bool dcn321_resource_construct( + uint8_t num_virtual_links, +@@ -1668,7 +1676,7 @@ static bool dcn321_resource_construct( + pool->base.res_cap = &res_cap_dcn321; + /* max number of pipes for ASIC before checking for pipe fuses */ + num_pipes = pool->base.res_cap->num_timing_generator; +- pipe_fuses = REG_READ(CC_DC_PIPE_DIS); ++ pipe_fuses = read_pipe_fuses(ctx); + + for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) + if (pipe_fuses & 1 << i) diff --git a/queue-6.3/drm-amd-display-fix-4to1-mpc-black-screen-with-dpp-rco.patch b/queue-6.3/drm-amd-display-fix-4to1-mpc-black-screen-with-dpp-rco.patch new file mode 100644 index 00000000000..be68d93fbec --- /dev/null +++ b/queue-6.3/drm-amd-display-fix-4to1-mpc-black-screen-with-dpp-rco.patch @@ -0,0 +1,264 @@ +From bf224e00a9f54e2bf14b4d720a09c3d2f4aa4aa8 Mon Sep 17 00:00:00 2001 +From: Nicholas Kazlauskas +Date: Mon, 13 Mar 2023 13:23:45 -0400 +Subject: drm/amd/display: Fix 4to1 MPC black screen with DPP RCO + +From: Nicholas Kazlauskas + +commit bf224e00a9f54e2bf14b4d720a09c3d2f4aa4aa8 upstream. + +[Why] +DPP Root clock optimization when combined with 4to1 MPC combine results +in the screen turning black. + +This is because the DPPCLK is stopped during the middle of an +optimize_bandwidth sequence during commit_minimal_transition without +going through plane power down/power up. + +[How] +The intent of a 0Hz DPP clock through update_clocks is to disable the +DTO. This differs from the behavior of stopping the DPPCLK entirely +(utilizing a 0Hz clock on some ASIC) so it's better to move this logic +to reside next to plane power up/power down where we gate the HUBP/DPP +DOMAIN. + +The new sequence should be: +Power down: PG enabled -> RCO on +Power up: RCO off -> PG disabled + +Rename power_on_plane to power_on_plane_resources to reflect the +actual operation that's occurring. + +Cc: stable@vger.kernel.org +Cc: Mario Limonciello +Reviewed-by: Jun Lei +Acked-by: Qingqing Zhuo +Signed-off-by: Nicholas Kazlauskas +Tested-by: Daniel Wheeler +Signed-off-by: Alex Deucher +Signed-off-by: Greg Kroah-Hartman +--- + drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c | 12 ++++++- + drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c | 8 +++- + drivers/gpu/drm/amd/display/dc/dcn31/dcn31_dccg.c | 13 +------ + drivers/gpu/drm/amd/display/dc/dcn314/dcn314_dccg.c | 23 ++++++++++++++ + drivers/gpu/drm/amd/display/dc/dcn314/dcn314_hwseq.c | 10 ++++++ + drivers/gpu/drm/amd/display/dc/dcn314/dcn314_hwseq.h | 2 + + drivers/gpu/drm/amd/display/dc/dcn314/dcn314_init.c | 1 + drivers/gpu/drm/amd/display/dc/inc/hw/dccg.h | 23 +++++++------- + drivers/gpu/drm/amd/display/dc/inc/hw_sequencer_private.h | 4 ++ + 9 files changed, 71 insertions(+), 25 deletions(-) + +--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c ++++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c +@@ -726,11 +726,15 @@ void dcn10_hubp_pg_control( + } + } + +-static void power_on_plane( ++static void power_on_plane_resources( + struct dce_hwseq *hws, + int plane_id) + { + DC_LOGGER_INIT(hws->ctx->logger); ++ ++ if (hws->funcs.dpp_root_clock_control) ++ hws->funcs.dpp_root_clock_control(hws, plane_id, true); ++ + if (REG(DC_IP_REQUEST_CNTL)) { + REG_SET(DC_IP_REQUEST_CNTL, 0, + IP_REQUEST_EN, 1); +@@ -1237,11 +1241,15 @@ void dcn10_plane_atomic_power_down(struc + hws->funcs.hubp_pg_control(hws, hubp->inst, false); + + dpp->funcs->dpp_reset(dpp); ++ + REG_SET(DC_IP_REQUEST_CNTL, 0, + IP_REQUEST_EN, 0); + DC_LOG_DEBUG( + "Power gated front end %d\n", hubp->inst); + } ++ ++ if (hws->funcs.dpp_root_clock_control) ++ hws->funcs.dpp_root_clock_control(hws, dpp->inst, false); + } + + /* disable HW used by plane. +@@ -2462,7 +2470,7 @@ static void dcn10_enable_plane( + + undo_DEGVIDCN10_253_wa(dc); + +- power_on_plane(dc->hwseq, ++ power_on_plane_resources(dc->hwseq, + pipe_ctx->plane_res.hubp->inst); + + /* enable DCFCLK current DCHUB */ +--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c ++++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c +@@ -1121,11 +1121,15 @@ void dcn20_blank_pixel_data( + } + + +-static void dcn20_power_on_plane( ++static void dcn20_power_on_plane_resources( + struct dce_hwseq *hws, + struct pipe_ctx *pipe_ctx) + { + DC_LOGGER_INIT(hws->ctx->logger); ++ ++ if (hws->funcs.dpp_root_clock_control) ++ hws->funcs.dpp_root_clock_control(hws, pipe_ctx->plane_res.dpp->inst, true); ++ + if (REG(DC_IP_REQUEST_CNTL)) { + REG_SET(DC_IP_REQUEST_CNTL, 0, + IP_REQUEST_EN, 1); +@@ -1149,7 +1153,7 @@ static void dcn20_enable_plane(struct dc + //if (dc->debug.sanity_checks) { + // dcn10_verify_allow_pstate_change_high(dc); + //} +- dcn20_power_on_plane(dc->hwseq, pipe_ctx); ++ dcn20_power_on_plane_resources(dc->hwseq, pipe_ctx); + + /* enable DCFCLK current DCHUB */ + pipe_ctx->plane_res.hubp->funcs->hubp_clk_cntl(pipe_ctx->plane_res.hubp, true); +--- a/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_dccg.c ++++ b/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_dccg.c +@@ -66,17 +66,8 @@ void dccg31_update_dpp_dto(struct dccg * + REG_UPDATE(DPPCLK_DTO_CTRL, + DPPCLK_DTO_ENABLE[dpp_inst], 1); + } else { +- //DTO must be enabled to generate a 0Hz clock output +- if (dccg->ctx->dc->debug.root_clock_optimization.bits.dpp) { +- REG_UPDATE(DPPCLK_DTO_CTRL, +- DPPCLK_DTO_ENABLE[dpp_inst], 1); +- REG_SET_2(DPPCLK_DTO_PARAM[dpp_inst], 0, +- DPPCLK0_DTO_PHASE, 0, +- DPPCLK0_DTO_MODULO, 1); +- } else { +- REG_UPDATE(DPPCLK_DTO_CTRL, +- DPPCLK_DTO_ENABLE[dpp_inst], 0); +- } ++ REG_UPDATE(DPPCLK_DTO_CTRL, ++ DPPCLK_DTO_ENABLE[dpp_inst], 0); + } + dccg->pipe_dppclk_khz[dpp_inst] = req_dppclk; + } +--- a/drivers/gpu/drm/amd/display/dc/dcn314/dcn314_dccg.c ++++ b/drivers/gpu/drm/amd/display/dc/dcn314/dcn314_dccg.c +@@ -289,8 +289,31 @@ static void dccg314_set_valid_pixel_rate + dccg314_set_dtbclk_dto(dccg, &dto_params); + } + ++static void dccg314_dpp_root_clock_control( ++ struct dccg *dccg, ++ unsigned int dpp_inst, ++ bool clock_on) ++{ ++ struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg); ++ ++ if (clock_on) { ++ /* turn off the DTO and leave phase/modulo at max */ ++ REG_UPDATE(DPPCLK_DTO_CTRL, DPPCLK_DTO_ENABLE[dpp_inst], 0); ++ REG_SET_2(DPPCLK_DTO_PARAM[dpp_inst], 0, ++ DPPCLK0_DTO_PHASE, 0xFF, ++ DPPCLK0_DTO_MODULO, 0xFF); ++ } else { ++ /* turn on the DTO to generate a 0hz clock */ ++ REG_UPDATE(DPPCLK_DTO_CTRL, DPPCLK_DTO_ENABLE[dpp_inst], 1); ++ REG_SET_2(DPPCLK_DTO_PARAM[dpp_inst], 0, ++ DPPCLK0_DTO_PHASE, 0, ++ DPPCLK0_DTO_MODULO, 1); ++ } ++} ++ + static const struct dccg_funcs dccg314_funcs = { + .update_dpp_dto = dccg31_update_dpp_dto, ++ .dpp_root_clock_control = dccg314_dpp_root_clock_control, + .get_dccg_ref_freq = dccg31_get_dccg_ref_freq, + .dccg_init = dccg31_init, + .set_dpstreamclk = dccg314_set_dpstreamclk, +--- a/drivers/gpu/drm/amd/display/dc/dcn314/dcn314_hwseq.c ++++ b/drivers/gpu/drm/amd/display/dc/dcn314/dcn314_hwseq.c +@@ -390,6 +390,16 @@ void dcn314_set_pixels_per_cycle(struct + pix_per_cycle); + } + ++void dcn314_dpp_root_clock_control(struct dce_hwseq *hws, unsigned int dpp_inst, bool clock_on) ++{ ++ if (!hws->ctx->dc->debug.root_clock_optimization.bits.dpp) ++ return; ++ ++ if (hws->ctx->dc->res_pool->dccg->funcs->dpp_root_clock_control) ++ hws->ctx->dc->res_pool->dccg->funcs->dpp_root_clock_control( ++ hws->ctx->dc->res_pool->dccg, dpp_inst, clock_on); ++} ++ + void dcn314_hubp_pg_control(struct dce_hwseq *hws, unsigned int hubp_inst, bool power_on) + { + struct dc_context *ctx = hws->ctx; +--- a/drivers/gpu/drm/amd/display/dc/dcn314/dcn314_hwseq.h ++++ b/drivers/gpu/drm/amd/display/dc/dcn314/dcn314_hwseq.h +@@ -43,4 +43,6 @@ void dcn314_set_pixels_per_cycle(struct + + void dcn314_hubp_pg_control(struct dce_hwseq *hws, unsigned int hubp_inst, bool power_on); + ++void dcn314_dpp_root_clock_control(struct dce_hwseq *hws, unsigned int dpp_inst, bool clock_on); ++ + #endif /* __DC_HWSS_DCN314_H__ */ +--- a/drivers/gpu/drm/amd/display/dc/dcn314/dcn314_init.c ++++ b/drivers/gpu/drm/amd/display/dc/dcn314/dcn314_init.c +@@ -137,6 +137,7 @@ static const struct hwseq_private_funcs + .plane_atomic_disable = dcn20_plane_atomic_disable, + .plane_atomic_power_down = dcn10_plane_atomic_power_down, + .enable_power_gating_plane = dcn314_enable_power_gating_plane, ++ .dpp_root_clock_control = dcn314_dpp_root_clock_control, + .hubp_pg_control = dcn314_hubp_pg_control, + .program_all_writeback_pipes_in_tree = dcn30_program_all_writeback_pipes_in_tree, + .update_odm = dcn314_update_odm, +--- a/drivers/gpu/drm/amd/display/dc/inc/hw/dccg.h ++++ b/drivers/gpu/drm/amd/display/dc/inc/hw/dccg.h +@@ -148,18 +148,21 @@ struct dccg_funcs { + struct dccg *dccg, + int inst); + +-void (*set_pixel_rate_div)( +- struct dccg *dccg, +- uint32_t otg_inst, +- enum pixel_rate_div k1, +- enum pixel_rate_div k2); ++ void (*set_pixel_rate_div)(struct dccg *dccg, ++ uint32_t otg_inst, ++ enum pixel_rate_div k1, ++ enum pixel_rate_div k2); + +-void (*set_valid_pixel_rate)( +- struct dccg *dccg, +- int ref_dtbclk_khz, +- int otg_inst, +- int pixclk_khz); ++ void (*set_valid_pixel_rate)( ++ struct dccg *dccg, ++ int ref_dtbclk_khz, ++ int otg_inst, ++ int pixclk_khz); + ++ void (*dpp_root_clock_control)( ++ struct dccg *dccg, ++ unsigned int dpp_inst, ++ bool clock_on); + }; + + #endif //__DAL_DCCG_H__ +--- a/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer_private.h ++++ b/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer_private.h +@@ -115,6 +115,10 @@ struct hwseq_private_funcs { + void (*plane_atomic_disable)(struct dc *dc, struct pipe_ctx *pipe_ctx); + void (*enable_power_gating_plane)(struct dce_hwseq *hws, + bool enable); ++ void (*dpp_root_clock_control)( ++ struct dce_hwseq *hws, ++ unsigned int dpp_inst, ++ bool clock_on); + void (*dpp_pg_control)(struct dce_hwseq *hws, + unsigned int dpp_inst, + bool power_on); diff --git a/queue-6.3/drm-amd-display-fix-access-hdcp_workqueue-assert.patch b/queue-6.3/drm-amd-display-fix-access-hdcp_workqueue-assert.patch new file mode 100644 index 00000000000..81a99b44ad0 --- /dev/null +++ b/queue-6.3/drm-amd-display-fix-access-hdcp_workqueue-assert.patch @@ -0,0 +1,81 @@ +From 3cf7cd3f770a0b89dc5f06e19edb52e65b93b214 Mon Sep 17 00:00:00 2001 +From: Hersen Wu +Date: Tue, 28 Mar 2023 10:45:24 -0400 +Subject: drm/amd/display: fix access hdcp_workqueue assert +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +From: Hersen Wu + +commit 3cf7cd3f770a0b89dc5f06e19edb52e65b93b214 upstream. + +[Why] hdcp are enabled for asics from raven. for old asics +which hdcp are not enabled, hdcp_workqueue are null. some +access to hdcp work queue are not guarded with pointer check. + +[How] add hdcp_workqueue pointer check before access workqueue. + +Fixes: 82986fd631fa ("drm/amd/display: save restore hdcp state when display is unplugged from mst hub") +Link: https://gitlab.freedesktop.org/drm/amd/-/issues/2444 +Reported-by: Niklāvs Koļesņikovs <89q1r14hd@relay.firefox.com> +Reviewed-by: Bhawanpreet Lakha +Acked-by: Qingqing Zhuo +Signed-off-by: Hersen Wu +Tested-by: Daniel Wheeler +Signed-off-by: Alex Deucher +Cc: stable@vger.kernel.org +Signed-off-by: Greg Kroah-Hartman +--- + drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 6 ++++ + drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c | 16 +++++++----- + 2 files changed, 16 insertions(+), 6 deletions(-) + +--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c ++++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +@@ -8533,6 +8533,9 @@ static void amdgpu_dm_atomic_commit_tail + struct amdgpu_crtc *acrtc = to_amdgpu_crtc(dm_new_con_state->base.crtc); + struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector); + ++ if (!adev->dm.hdcp_workqueue) ++ continue; ++ + pr_debug("[HDCP_DM] -------------- i : %x ----------\n", i); + + if (!connector) +@@ -8581,6 +8584,9 @@ static void amdgpu_dm_atomic_commit_tail + struct amdgpu_crtc *acrtc = to_amdgpu_crtc(dm_new_con_state->base.crtc); + struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector); + ++ if (!adev->dm.hdcp_workqueue) ++ continue; ++ + new_crtc_state = NULL; + old_crtc_state = NULL; + +--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c ++++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c +@@ -385,13 +385,17 @@ static int dm_dp_mst_get_modes(struct dr + if (aconnector->dc_sink && connector->state) { + struct drm_device *dev = connector->dev; + struct amdgpu_device *adev = drm_to_adev(dev); +- struct hdcp_workqueue *hdcp_work = adev->dm.hdcp_workqueue; +- struct hdcp_workqueue *hdcp_w = &hdcp_work[aconnector->dc_link->link_index]; + +- connector->state->hdcp_content_type = +- hdcp_w->hdcp_content_type[connector->index]; +- connector->state->content_protection = +- hdcp_w->content_protection[connector->index]; ++ if (adev->dm.hdcp_workqueue) { ++ struct hdcp_workqueue *hdcp_work = adev->dm.hdcp_workqueue; ++ struct hdcp_workqueue *hdcp_w = ++ &hdcp_work[aconnector->dc_link->link_index]; ++ ++ connector->state->hdcp_content_type = ++ hdcp_w->hdcp_content_type[connector->index]; ++ connector->state->content_protection = ++ hdcp_w->content_protection[connector->index]; ++ } + } + #endif + diff --git a/queue-6.3/drm-amd-display-fix-flickering-caused-by-s-g-mode.patch b/queue-6.3/drm-amd-display-fix-flickering-caused-by-s-g-mode.patch new file mode 100644 index 00000000000..a70d2fbe72d --- /dev/null +++ b/queue-6.3/drm-amd-display-fix-flickering-caused-by-s-g-mode.patch @@ -0,0 +1,58 @@ +From 08da182175db4c7f80850354849d95f2670e8cd9 Mon Sep 17 00:00:00 2001 +From: Hamza Mahfooz +Date: Fri, 14 Apr 2023 14:26:27 -0400 +Subject: drm/amd/display: fix flickering caused by S/G mode + +From: Hamza Mahfooz + +commit 08da182175db4c7f80850354849d95f2670e8cd9 upstream. + +Currently, on a handful of ASICs. We allow the framebuffer for a given +plane to exist in either VRAM or GTT. However, if the plane's new +framebuffer is in a different memory domain than it's previous +framebuffer, flipping between them can cause the screen to flicker. So, +to fix this, don't perform an immediate flip in the aforementioned case. + +Cc: stable@vger.kernel.org +Link: https://gitlab.freedesktop.org/drm/amd/-/issues/2354 +Reviewed-by: Roman Li +Fixes: 81d0bcf99009 ("drm/amdgpu: make display pinning more flexible (v2)") +Signed-off-by: Hamza Mahfooz +Signed-off-by: Alex Deucher +Signed-off-by: Greg Kroah-Hartman +--- + drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 13 +++++++++++-- + 1 file changed, 11 insertions(+), 2 deletions(-) + +--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c ++++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +@@ -7876,6 +7876,13 @@ static void amdgpu_dm_commit_cursors(str + handle_cursor_update(plane, old_plane_state); + } + ++static inline uint32_t get_mem_type(struct drm_framebuffer *fb) ++{ ++ struct amdgpu_bo *abo = gem_to_amdgpu_bo(fb->obj[0]); ++ ++ return abo->tbo.resource ? abo->tbo.resource->mem_type : 0; ++} ++ + static void amdgpu_dm_commit_planes(struct drm_atomic_state *state, + struct dc_state *dc_state, + struct drm_device *dev, +@@ -8016,11 +8023,13 @@ static void amdgpu_dm_commit_planes(stru + + /* + * Only allow immediate flips for fast updates that don't +- * change FB pitch, DCC state, rotation or mirroing. ++ * change memory domain, FB pitch, DCC state, rotation or ++ * mirroring. + */ + bundle->flip_addrs[planes_count].flip_immediate = + crtc->state->async_flip && +- acrtc_state->update_type == UPDATE_TYPE_FAST; ++ acrtc_state->update_type == UPDATE_TYPE_FAST && ++ get_mem_type(old_plane_state->fb) == get_mem_type(fb); + + timestamp_ns = ktime_get_ns(); + bundle->flip_addrs[planes_count].flip_timestamp_in_us = div_u64(timestamp_ns, 1000); diff --git a/queue-6.3/drm-amd-pm-avoid-potential-ubsan-issue-on-legacy-asics.patch b/queue-6.3/drm-amd-pm-avoid-potential-ubsan-issue-on-legacy-asics.patch new file mode 100644 index 00000000000..b2fa792997e --- /dev/null +++ b/queue-6.3/drm-amd-pm-avoid-potential-ubsan-issue-on-legacy-asics.patch @@ -0,0 +1,51 @@ +From 5247f05eadf1081a74b2233f291cee2efed25e3a Mon Sep 17 00:00:00 2001 +From: Guchun Chen +Date: Tue, 9 May 2023 09:36:49 +0800 +Subject: drm/amd/pm: avoid potential UBSAN issue on legacy asics + +From: Guchun Chen + +commit 5247f05eadf1081a74b2233f291cee2efed25e3a upstream. + +Prevent further dpm casting on legacy asics without od_enabled in +amdgpu_dpm_is_overdrive_supported. This can avoid UBSAN complain +in init sequence. + +v2: add a macro to check legacy dpm instead of checking asic family/type +v3: refine macro name for naming consistency + +Suggested-by: Evan Quan +Signed-off-by: Guchun Chen +Reviewed-by: Lijo Lazar +Signed-off-by: Alex Deucher +Cc: stable@vger.kernel.org +Signed-off-by: Greg Kroah-Hartman +--- + drivers/gpu/drm/amd/pm/amdgpu_dpm.c | 9 +++++++-- + 1 file changed, 7 insertions(+), 2 deletions(-) + +--- a/drivers/gpu/drm/amd/pm/amdgpu_dpm.c ++++ b/drivers/gpu/drm/amd/pm/amdgpu_dpm.c +@@ -36,6 +36,8 @@ + #define amdgpu_dpm_enable_bapm(adev, e) \ + ((adev)->powerplay.pp_funcs->enable_bapm((adev)->powerplay.pp_handle, (e))) + ++#define amdgpu_dpm_is_legacy_dpm(adev) ((adev)->powerplay.pp_handle == (adev)) ++ + int amdgpu_dpm_get_sclk(struct amdgpu_device *adev, bool low) + { + const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; +@@ -1439,8 +1441,11 @@ int amdgpu_dpm_is_overdrive_supported(st + } else { + struct pp_hwmgr *hwmgr; + +- /* SI asic does not carry od_enabled */ +- if (adev->family == AMDGPU_FAMILY_SI) ++ /* ++ * dpm on some legacy asics don't carry od_enabled member ++ * as its pp_handle is casted directly from adev. ++ */ ++ if (amdgpu_dpm_is_legacy_dpm(adev)) + return false; + + hwmgr = (struct pp_hwmgr *)adev->powerplay.pp_handle; diff --git a/queue-6.3/drm-amd-pm-parse-pp_handle-under-appropriate-conditions.patch b/queue-6.3/drm-amd-pm-parse-pp_handle-under-appropriate-conditions.patch new file mode 100644 index 00000000000..bf4fc5eba42 --- /dev/null +++ b/queue-6.3/drm-amd-pm-parse-pp_handle-under-appropriate-conditions.patch @@ -0,0 +1,59 @@ +From 58d9b9a14b47c2a3da6effcbb01607ad7edc0275 Mon Sep 17 00:00:00 2001 +From: Guchun Chen +Date: Fri, 5 May 2023 13:20:11 +0800 +Subject: drm/amd/pm: parse pp_handle under appropriate conditions + +From: Guchun Chen + +commit 58d9b9a14b47c2a3da6effcbb01607ad7edc0275 upstream. + +amdgpu_dpm_is_overdrive_supported is a common API across all +asics, so we should cast pp_handle into correct structure +under different power frameworks. + +v2: using return directly to simplify code +v3: SI asic does not carry od_enabled member in pp_handle, and update Fixes tag + +Link: https://gitlab.freedesktop.org/drm/amd/-/issues/2541 +Fixes: eb4900aa4c49 ("drm/amdgpu: Fix kernel NULL pointer dereference in dpm functions") +Suggested-by: Mario Limonciello +Signed-off-by: Guchun Chen +Reviewed-by: Mario Limonciello +Signed-off-by: Alex Deucher +Cc: stable@vger.kernel.org +Signed-off-by: Greg Kroah-Hartman +--- + drivers/gpu/drm/amd/pm/amdgpu_dpm.c | 20 +++++++++++++------- + 1 file changed, 13 insertions(+), 7 deletions(-) + +--- a/drivers/gpu/drm/amd/pm/amdgpu_dpm.c ++++ b/drivers/gpu/drm/amd/pm/amdgpu_dpm.c +@@ -1432,15 +1432,21 @@ int amdgpu_dpm_get_smu_prv_buf_details(s + + int amdgpu_dpm_is_overdrive_supported(struct amdgpu_device *adev) + { +- struct pp_hwmgr *hwmgr = adev->powerplay.pp_handle; +- struct smu_context *smu = adev->powerplay.pp_handle; ++ if (is_support_sw_smu(adev)) { ++ struct smu_context *smu = adev->powerplay.pp_handle; + +- if ((is_support_sw_smu(adev) && smu->od_enabled) || +- (is_support_sw_smu(adev) && smu->is_apu) || +- (!is_support_sw_smu(adev) && hwmgr->od_enabled)) +- return true; ++ return (smu->od_enabled || smu->is_apu); ++ } else { ++ struct pp_hwmgr *hwmgr; + +- return false; ++ /* SI asic does not carry od_enabled */ ++ if (adev->family == AMDGPU_FAMILY_SI) ++ return false; ++ ++ hwmgr = (struct pp_hwmgr *)adev->powerplay.pp_handle; ++ ++ return hwmgr->od_enabled; ++ } + } + + int amdgpu_dpm_set_pp_table(struct amdgpu_device *adev, diff --git a/queue-6.3/drm-amdgpu-change-gfx-11.0.4-external_id-range.patch b/queue-6.3/drm-amdgpu-change-gfx-11.0.4-external_id-range.patch new file mode 100644 index 00000000000..c2fa5d950cd --- /dev/null +++ b/queue-6.3/drm-amdgpu-change-gfx-11.0.4-external_id-range.patch @@ -0,0 +1,34 @@ +From 996e93a3fe74dcf9d467ae3020aea42cc3ff65e3 Mon Sep 17 00:00:00 2001 +From: Yifan Zhang +Date: Wed, 10 May 2023 16:13:48 +0800 +Subject: drm/amdgpu: change gfx 11.0.4 external_id range + +From: Yifan Zhang + +commit 996e93a3fe74dcf9d467ae3020aea42cc3ff65e3 upstream. + +gfx 11.0.4 range starts from 0x80. + +Fixes: 311d52367d0a ("drm/amdgpu: add soc21 common ip block support for GC 11.0.4") +Cc: stable@vger.kernel.org +Signed-off-by: Yifan Zhang +Reported-by: Yogesh Mohan Marimuthu +Acked-by: Alex Deucher +Reviewed-by: Tim Huang +Signed-off-by: Alex Deucher +Signed-off-by: Greg Kroah-Hartman +--- + drivers/gpu/drm/amd/amdgpu/soc21.c | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +--- a/drivers/gpu/drm/amd/amdgpu/soc21.c ++++ b/drivers/gpu/drm/amd/amdgpu/soc21.c +@@ -778,7 +778,7 @@ static int soc21_common_early_init(void + AMD_PG_SUPPORT_VCN_DPG | + AMD_PG_SUPPORT_GFX_PG | + AMD_PG_SUPPORT_JPEG; +- adev->external_rev_id = adev->rev_id + 0x1; ++ adev->external_rev_id = adev->rev_id + 0x80; + break; + + default: diff --git a/queue-6.3/drm-amdgpu-disable-sdma-ecc-irq-only-when-sdma-ras-is-enabled-in-suspend.patch b/queue-6.3/drm-amdgpu-disable-sdma-ecc-irq-only-when-sdma-ras-is-enabled-in-suspend.patch new file mode 100644 index 00000000000..26bad0334f9 --- /dev/null +++ b/queue-6.3/drm-amdgpu-disable-sdma-ecc-irq-only-when-sdma-ras-is-enabled-in-suspend.patch @@ -0,0 +1,60 @@ +From 8b229ada2669b74fdae06c83fbfda5a5a99fc253 Mon Sep 17 00:00:00 2001 +From: Guchun Chen +Date: Sat, 6 May 2023 16:52:59 +0800 +Subject: drm/amdgpu: disable sdma ecc irq only when sdma RAS is enabled in suspend + +From: Guchun Chen + +commit 8b229ada2669b74fdae06c83fbfda5a5a99fc253 upstream. + +sdma_v4_0_ip is shared on a few asics, but in sdma_v4_0_hw_fini, +driver unconditionally disables ecc_irq which is only enabled on +those asics enabling sdma ecc. This will introduce a warning in +suspend cycle on those chips with sdma ip v4.0, while without +sdma ecc. So this patch correct this. + +[ 7283.166354] RIP: 0010:amdgpu_irq_put+0x45/0x70 [amdgpu] +[ 7283.167001] RSP: 0018:ffff9a5fc3967d08 EFLAGS: 00010246 +[ 7283.167019] RAX: ffff98d88afd3770 RBX: 0000000000000001 RCX: 0000000000000000 +[ 7283.167023] RDX: 0000000000000000 RSI: ffff98d89da30390 RDI: ffff98d89da20000 +[ 7283.167025] RBP: ffff98d89da20000 R08: 0000000000036838 R09: 0000000000000006 +[ 7283.167028] R10: ffffd5764243c008 R11: 0000000000000000 R12: ffff98d89da30390 +[ 7283.167030] R13: ffff98d89da38978 R14: ffffffff999ae15a R15: ffff98d880130105 +[ 7283.167032] FS: 0000000000000000(0000) GS:ffff98d996f00000(0000) knlGS:0000000000000000 +[ 7283.167036] CS: 0010 DS: 0000 ES: 0000 CR0: 0000000080050033 +[ 7283.167039] CR2: 00000000f7a9d178 CR3: 00000001c42ea000 CR4: 00000000003506e0 +[ 7283.167041] Call Trace: +[ 7283.167046] +[ 7283.167048] sdma_v4_0_hw_fini+0x38/0xa0 [amdgpu] +[ 7283.167704] amdgpu_device_ip_suspend_phase2+0x101/0x1a0 [amdgpu] +[ 7283.168296] amdgpu_device_suspend+0x103/0x180 [amdgpu] +[ 7283.168875] amdgpu_pmops_freeze+0x21/0x60 [amdgpu] +[ 7283.169464] pci_pm_freeze+0x54/0xc0 + +Link: https://gitlab.freedesktop.org/drm/amd/-/issues/2522 +Signed-off-by: Guchun Chen +Reviewed-by: Tao Zhou +Signed-off-by: Alex Deucher +Cc: stable@vger.kernel.org +Signed-off-by: Greg Kroah-Hartman +--- + drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c | 8 +++++--- + 1 file changed, 5 insertions(+), 3 deletions(-) + +--- a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c ++++ b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c +@@ -1903,9 +1903,11 @@ static int sdma_v4_0_hw_fini(void *handl + return 0; + } + +- for (i = 0; i < adev->sdma.num_instances; i++) { +- amdgpu_irq_put(adev, &adev->sdma.ecc_irq, +- AMDGPU_SDMA_IRQ_INSTANCE0 + i); ++ if (amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__SDMA)) { ++ for (i = 0; i < adev->sdma.num_instances; i++) { ++ amdgpu_irq_put(adev, &adev->sdma.ecc_irq, ++ AMDGPU_SDMA_IRQ_INSTANCE0 + i); ++ } + } + + sdma_v4_0_ctx_switch_enable(adev, false); diff --git a/queue-6.3/drm-amdgpu-drop-gfx_v11_0_cp_ecc_error_irq_funcs.patch b/queue-6.3/drm-amdgpu-drop-gfx_v11_0_cp_ecc_error_irq_funcs.patch new file mode 100644 index 00000000000..060c47892f9 --- /dev/null +++ b/queue-6.3/drm-amdgpu-drop-gfx_v11_0_cp_ecc_error_irq_funcs.patch @@ -0,0 +1,162 @@ +From 720b47229a5b24061d1c2e29ddb6043a59178d79 Mon Sep 17 00:00:00 2001 +From: Horatio Zhang +Date: Thu, 4 May 2023 01:46:12 -0400 +Subject: drm/amdgpu: drop gfx_v11_0_cp_ecc_error_irq_funcs +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +From: Horatio Zhang + +commit 720b47229a5b24061d1c2e29ddb6043a59178d79 upstream. + +The gfx.cp_ecc_error_irq is retired in gfx11. In gfx_v11_0_hw_fini still +use amdgpu_irq_put to disable this interrupt, which caused the call trace +in this function. + +[ 102.873958] Call Trace: +[ 102.873959] +[ 102.873961] gfx_v11_0_hw_fini+0x23/0x1e0 [amdgpu] +[ 102.874019] gfx_v11_0_suspend+0xe/0x20 [amdgpu] +[ 102.874072] amdgpu_device_ip_suspend_phase2+0x240/0x460 [amdgpu] +[ 102.874122] amdgpu_device_ip_suspend+0x3d/0x80 [amdgpu] +[ 102.874172] amdgpu_device_pre_asic_reset+0xd9/0x490 [amdgpu] +[ 102.874223] amdgpu_device_gpu_recover.cold+0x548/0xce6 [amdgpu] +[ 102.874321] amdgpu_debugfs_reset_work+0x4c/0x70 [amdgpu] +[ 102.874375] process_one_work+0x21f/0x3f0 +[ 102.874377] worker_thread+0x200/0x3e0 +[ 102.874378] ? process_one_work+0x3f0/0x3f0 +[ 102.874379] kthread+0xfd/0x130 +[ 102.874380] ? kthread_complete_and_exit+0x20/0x20 +[ 102.874381] ret_from_fork+0x22/0x30 + +v2: +- Handle umc and gfx ras cases in separated patch +- Retired the gfx_v11_0_cp_ecc_error_irq_funcs in gfx11 + +v3: +- Improve the subject and code comments +- Add judgment on gfx11 in the function of amdgpu_gfx_ras_late_init + +v4: +- Drop the define of CP_ME1_PIPE_INST_ADDR_INTERVAL and +SET_ECC_ME_PIPE_STATE which using in gfx_v11_0_set_cp_ecc_error_state +- Check cp_ecc_error_irq.funcs rather than ip version for a more +sustainable life + +v5: +- Simplify judgment conditions + +Signed-off-by: Horatio Zhang +Reviewed-by: Hawking Zhang +Acked-by: Christian König +Reviewed-by: Guchun Chen +Reviewed-by: Feifei Xu +Signed-off-by: Alex Deucher +Cc: stable@vger.kernel.org +Signed-off-by: Greg Kroah-Hartman +--- + drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c | 8 +++-- + drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c | 46 -------------------------------- + 2 files changed, 5 insertions(+), 49 deletions(-) + +--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c ++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c +@@ -686,9 +686,11 @@ int amdgpu_gfx_ras_late_init(struct amdg + if (r) + return r; + +- r = amdgpu_irq_get(adev, &adev->gfx.cp_ecc_error_irq, 0); +- if (r) +- goto late_fini; ++ if (adev->gfx.cp_ecc_error_irq.funcs) { ++ r = amdgpu_irq_get(adev, &adev->gfx.cp_ecc_error_irq, 0); ++ if (r) ++ goto late_fini; ++ } + } else { + amdgpu_ras_feature_enable_on_boot(adev, ras_block, 0); + } +--- a/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c ++++ b/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c +@@ -1313,13 +1313,6 @@ static int gfx_v11_0_sw_init(void *handl + if (r) + return r; + +- /* ECC error */ +- r = amdgpu_irq_add_id(adev, SOC21_IH_CLIENTID_GRBM_CP, +- GFX_11_0_0__SRCID__CP_ECC_ERROR, +- &adev->gfx.cp_ecc_error_irq); +- if (r) +- return r; +- + /* FED error */ + r = amdgpu_irq_add_id(adev, SOC21_IH_CLIENTID_GFX, + GFX_11_0_0__SRCID__RLC_GC_FED_INTERRUPT, +@@ -4442,7 +4435,6 @@ static int gfx_v11_0_hw_fini(void *handl + struct amdgpu_device *adev = (struct amdgpu_device *)handle; + int r; + +- amdgpu_irq_put(adev, &adev->gfx.cp_ecc_error_irq, 0); + amdgpu_irq_put(adev, &adev->gfx.priv_reg_irq, 0); + amdgpu_irq_put(adev, &adev->gfx.priv_inst_irq, 0); + +@@ -5882,36 +5874,6 @@ static void gfx_v11_0_set_compute_eop_in + } + } + +-#define CP_ME1_PIPE_INST_ADDR_INTERVAL 0x1 +-#define SET_ECC_ME_PIPE_STATE(reg_addr, state) \ +- do { \ +- uint32_t tmp = RREG32_SOC15_IP(GC, reg_addr); \ +- tmp = REG_SET_FIELD(tmp, CP_ME1_PIPE0_INT_CNTL, CP_ECC_ERROR_INT_ENABLE, state); \ +- WREG32_SOC15_IP(GC, reg_addr, tmp); \ +- } while (0) +- +-static int gfx_v11_0_set_cp_ecc_error_state(struct amdgpu_device *adev, +- struct amdgpu_irq_src *source, +- unsigned type, +- enum amdgpu_interrupt_state state) +-{ +- uint32_t ecc_irq_state = 0; +- uint32_t pipe0_int_cntl_addr = 0; +- int i = 0; +- +- ecc_irq_state = (state == AMDGPU_IRQ_STATE_ENABLE) ? 1 : 0; +- +- pipe0_int_cntl_addr = SOC15_REG_OFFSET(GC, 0, regCP_ME1_PIPE0_INT_CNTL); +- +- WREG32_FIELD15_PREREG(GC, 0, CP_INT_CNTL_RING0, CP_ECC_ERROR_INT_ENABLE, ecc_irq_state); +- +- for (i = 0; i < adev->gfx.mec.num_pipe_per_mec; i++) +- SET_ECC_ME_PIPE_STATE(pipe0_int_cntl_addr + i * CP_ME1_PIPE_INST_ADDR_INTERVAL, +- ecc_irq_state); +- +- return 0; +-} +- + static int gfx_v11_0_set_eop_interrupt_state(struct amdgpu_device *adev, + struct amdgpu_irq_src *src, + unsigned type, +@@ -6329,11 +6291,6 @@ static const struct amdgpu_irq_src_funcs + .process = gfx_v11_0_priv_inst_irq, + }; + +-static const struct amdgpu_irq_src_funcs gfx_v11_0_cp_ecc_error_irq_funcs = { +- .set = gfx_v11_0_set_cp_ecc_error_state, +- .process = amdgpu_gfx_cp_ecc_error_irq, +-}; +- + static const struct amdgpu_irq_src_funcs gfx_v11_0_rlc_gc_fed_irq_funcs = { + .process = gfx_v11_0_rlc_gc_fed_irq, + }; +@@ -6349,9 +6306,6 @@ static void gfx_v11_0_set_irq_funcs(stru + adev->gfx.priv_inst_irq.num_types = 1; + adev->gfx.priv_inst_irq.funcs = &gfx_v11_0_priv_inst_irq_funcs; + +- adev->gfx.cp_ecc_error_irq.num_types = 1; /* CP ECC error */ +- adev->gfx.cp_ecc_error_irq.funcs = &gfx_v11_0_cp_ecc_error_irq_funcs; +- + adev->gfx.rlc_gc_fed_irq.num_types = 1; /* 0x80 FED error */ + adev->gfx.rlc_gc_fed_irq.funcs = &gfx_v11_0_rlc_gc_fed_irq_funcs; + diff --git a/queue-6.3/drm-amdgpu-drop-redundant-sched-job-cleanup-when-cs-is-aborted.patch b/queue-6.3/drm-amdgpu-drop-redundant-sched-job-cleanup-when-cs-is-aborted.patch new file mode 100644 index 00000000000..6f2f8b93c18 --- /dev/null +++ b/queue-6.3/drm-amdgpu-drop-redundant-sched-job-cleanup-when-cs-is-aborted.patch @@ -0,0 +1,65 @@ +From 1253685f0d3eb3eab0bfc4bf15ab341a5f3da0c8 Mon Sep 17 00:00:00 2001 +From: Guchun Chen +Date: Wed, 26 Apr 2023 09:46:54 +0800 +Subject: drm/amdgpu: drop redundant sched job cleanup when cs is aborted +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +From: Guchun Chen + +commit 1253685f0d3eb3eab0bfc4bf15ab341a5f3da0c8 upstream. + +Once command submission failed due to userptr invalidation in +amdgpu_cs_submit, legacy code will perform cleanup of scheduler +job. However, it's not needed at all, as former commit has integrated +job cleanup stuff into amdgpu_job_free. Otherwise, because of double +free, a NULL pointer dereference will occur in such scenario. + +Bug: https://gitlab.freedesktop.org/drm/amd/-/issues/2457 +Fixes: f7d66fb2ea43 ("drm/amdgpu: cleanup scheduler job initialization v2") +Signed-off-by: Guchun Chen +Reviewed-by: Christian König +Signed-off-by: Alex Deucher +Cc: stable@vger.kernel.org +Signed-off-by: Greg Kroah-Hartman +--- + drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c | 13 +++---------- + 1 file changed, 3 insertions(+), 10 deletions(-) + +--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c ++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c +@@ -1276,7 +1276,7 @@ static int amdgpu_cs_submit(struct amdgp + r = drm_sched_job_add_dependency(&leader->base, fence); + if (r) { + dma_fence_put(fence); +- goto error_cleanup; ++ return r; + } + } + +@@ -1303,7 +1303,8 @@ static int amdgpu_cs_submit(struct amdgp + } + if (r) { + r = -EAGAIN; +- goto error_unlock; ++ mutex_unlock(&p->adev->notifier_lock); ++ return r; + } + + p->fence = dma_fence_get(&leader->base.s_fence->finished); +@@ -1350,14 +1351,6 @@ static int amdgpu_cs_submit(struct amdgp + mutex_unlock(&p->adev->notifier_lock); + mutex_unlock(&p->bo_list->bo_list_mutex); + return 0; +- +-error_unlock: +- mutex_unlock(&p->adev->notifier_lock); +- +-error_cleanup: +- for (i = 0; i < p->gang_size; ++i) +- drm_sched_job_cleanup(&p->jobs[i]->base); +- return r; + } + + /* Cleanup the parser structure */ diff --git a/queue-6.3/drm-amdgpu-fix-amdgpu_irq_put-call-trace-in-gmc_v10_0_hw_fini.patch b/queue-6.3/drm-amdgpu-fix-amdgpu_irq_put-call-trace-in-gmc_v10_0_hw_fini.patch new file mode 100644 index 00000000000..ca5cdcb5891 --- /dev/null +++ b/queue-6.3/drm-amdgpu-fix-amdgpu_irq_put-call-trace-in-gmc_v10_0_hw_fini.patch @@ -0,0 +1,53 @@ +From 08c677cb0b436a96a836792bb35a8ec5de4999c2 Mon Sep 17 00:00:00 2001 +From: Horatio Zhang +Date: Tue, 25 Apr 2023 10:52:28 +0800 +Subject: drm/amdgpu: fix amdgpu_irq_put call trace in gmc_v10_0_hw_fini + +From: Horatio Zhang + +commit 08c677cb0b436a96a836792bb35a8ec5de4999c2 upstream. + +The gmc.ecc_irq is enabled by firmware per IFWI setting, +and the host driver is not privileged to enable/disable +the interrupt. So, it is meaningless to use the amdgpu_irq_put +function in gmc_v10_0_hw_fini, which also leads to the call +trace. + +[ 82.340264] Call Trace: +[ 82.340265] +[ 82.340269] gmc_v10_0_hw_fini+0x83/0xa0 [amdgpu] +[ 82.340447] gmc_v10_0_suspend+0xe/0x20 [amdgpu] +[ 82.340623] amdgpu_device_ip_suspend_phase2+0x127/0x1c0 [amdgpu] +[ 82.340789] amdgpu_device_ip_suspend+0x3d/0x80 [amdgpu] +[ 82.340955] amdgpu_device_pre_asic_reset+0xdd/0x2b0 [amdgpu] +[ 82.341122] amdgpu_device_gpu_recover.cold+0x4dd/0xbb2 [amdgpu] +[ 82.341359] amdgpu_debugfs_reset_work+0x4c/0x70 [amdgpu] +[ 82.341529] process_one_work+0x21d/0x3f0 +[ 82.341535] worker_thread+0x1fa/0x3c0 +[ 82.341538] ? process_one_work+0x3f0/0x3f0 +[ 82.341540] kthread+0xff/0x130 +[ 82.341544] ? kthread_complete_and_exit+0x20/0x20 +[ 82.341547] ret_from_fork+0x22/0x30 + +Signed-off-by: Horatio Zhang +Reviewed-by: Hawking Zhang +Reviewed-by: Guchun Chen +Signed-off-by: Alex Deucher +Link: https://gitlab.freedesktop.org/drm/amd/-/issues/2522 +Fixes: c8b5a95b5709 ("drm/amdgpu: Fix desktop freezed after gpu-reset") +Cc: stable@vger.kernel.org +Signed-off-by: Greg Kroah-Hartman +--- + drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c | 1 - + 1 file changed, 1 deletion(-) + +--- a/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c ++++ b/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c +@@ -1161,7 +1161,6 @@ static int gmc_v10_0_hw_fini(void *handl + return 0; + } + +- amdgpu_irq_put(adev, &adev->gmc.ecc_irq, 0); + amdgpu_irq_put(adev, &adev->gmc.vm_fault, 0); + + return 0; diff --git a/queue-6.3/drm-amdgpu-fix-amdgpu_irq_put-call-trace-in-gmc_v11_0_hw_fini.patch b/queue-6.3/drm-amdgpu-fix-amdgpu_irq_put-call-trace-in-gmc_v11_0_hw_fini.patch new file mode 100644 index 00000000000..799aa1e576e --- /dev/null +++ b/queue-6.3/drm-amdgpu-fix-amdgpu_irq_put-call-trace-in-gmc_v11_0_hw_fini.patch @@ -0,0 +1,53 @@ +From 13af556104fa93b1945c70bbf8a0a62cd2c92879 Mon Sep 17 00:00:00 2001 +From: Horatio Zhang +Date: Tue, 25 Apr 2023 13:16:32 +0800 +Subject: drm/amdgpu: fix amdgpu_irq_put call trace in gmc_v11_0_hw_fini + +From: Horatio Zhang + +commit 13af556104fa93b1945c70bbf8a0a62cd2c92879 upstream. + +The gmc.ecc_irq is enabled by firmware per IFWI setting, +and the host driver is not privileged to enable/disable +the interrupt. So, it is meaningless to use the amdgpu_irq_put +function in gmc_v11_0_hw_fini, which also leads to the call +trace. + +[ 102.980303] Call Trace: +[ 102.980303] +[ 102.980304] gmc_v11_0_hw_fini+0x54/0x90 [amdgpu] +[ 102.980357] gmc_v11_0_suspend+0xe/0x20 [amdgpu] +[ 102.980409] amdgpu_device_ip_suspend_phase2+0x240/0x460 [amdgpu] +[ 102.980459] amdgpu_device_ip_suspend+0x3d/0x80 [amdgpu] +[ 102.980520] amdgpu_device_pre_asic_reset+0xd9/0x490 [amdgpu] +[ 102.980573] amdgpu_device_gpu_recover.cold+0x548/0xce6 [amdgpu] +[ 102.980687] amdgpu_debugfs_reset_work+0x4c/0x70 [amdgpu] +[ 102.980740] process_one_work+0x21f/0x3f0 +[ 102.980741] worker_thread+0x200/0x3e0 +[ 102.980742] ? process_one_work+0x3f0/0x3f0 +[ 102.980743] kthread+0xfd/0x130 +[ 102.980743] ? kthread_complete_and_exit+0x20/0x20 +[ 102.980744] ret_from_fork+0x22/0x30 + +Signed-off-by: Horatio Zhang +Reviewed-by: Hawking Zhang +Reviewed-by: Guchun Chen +Signed-off-by: Alex Deucher +Link: https://gitlab.freedesktop.org/drm/amd/-/issues/2522 +Fixes: c8b5a95b5709 ("drm/amdgpu: Fix desktop freezed after gpu-reset") +Cc: stable@vger.kernel.org +Signed-off-by: Greg Kroah-Hartman +--- + drivers/gpu/drm/amd/amdgpu/gmc_v11_0.c | 1 - + 1 file changed, 1 deletion(-) + +--- a/drivers/gpu/drm/amd/amdgpu/gmc_v11_0.c ++++ b/drivers/gpu/drm/amd/amdgpu/gmc_v11_0.c +@@ -954,7 +954,6 @@ static int gmc_v11_0_hw_fini(void *handl + return 0; + } + +- amdgpu_irq_put(adev, &adev->gmc.ecc_irq, 0); + amdgpu_irq_put(adev, &adev->gmc.vm_fault, 0); + gmc_v11_0_gart_disable(adev); + diff --git a/queue-6.3/drm-amdgpu-fix-an-amdgpu_irq_put-issue-in-gmc_v9_0_hw_fini.patch b/queue-6.3/drm-amdgpu-fix-an-amdgpu_irq_put-issue-in-gmc_v9_0_hw_fini.patch new file mode 100644 index 00000000000..f3ccf26fa31 --- /dev/null +++ b/queue-6.3/drm-amdgpu-fix-an-amdgpu_irq_put-issue-in-gmc_v9_0_hw_fini.patch @@ -0,0 +1,36 @@ +From 922a76ba31adf84e72bc947267385be420c689ee Mon Sep 17 00:00:00 2001 +From: Hamza Mahfooz +Date: Tue, 2 May 2023 11:59:08 -0400 +Subject: drm/amdgpu: fix an amdgpu_irq_put() issue in gmc_v9_0_hw_fini() + +From: Hamza Mahfooz + +commit 922a76ba31adf84e72bc947267385be420c689ee upstream. + +As made mention of in commit 08c677cb0b43 ("drm/amdgpu: fix +amdgpu_irq_put call trace in gmc_v10_0_hw_fini") and commit 13af556104fa +("drm/amdgpu: fix amdgpu_irq_put call trace in gmc_v11_0_hw_fini"). It +is meaningless to call amdgpu_irq_put() for gmc.ecc_irq. So, remove it +from gmc_v9_0_hw_fini(). + +Link: https://gitlab.freedesktop.org/drm/amd/-/issues/2522 +Fixes: 3029c855d79f ("drm/amdgpu: Fix desktop freezed after gpu-reset") +Reviewed-by: Mario Limonciello +Signed-off-by: Hamza Mahfooz +Signed-off-by: Alex Deucher +Cc: stable@vger.kernel.org +Signed-off-by: Greg Kroah-Hartman +--- + drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c | 1 - + 1 file changed, 1 deletion(-) + +--- a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c ++++ b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c +@@ -1987,7 +1987,6 @@ static int gmc_v9_0_hw_fini(void *handle + if (adev->mmhub.funcs->update_power_gating) + adev->mmhub.funcs->update_power_gating(adev, false); + +- amdgpu_irq_put(adev, &adev->gmc.ecc_irq, 0); + amdgpu_irq_put(adev, &adev->gmc.vm_fault, 0); + + return 0; diff --git a/queue-6.3/drm-amdgpu-fix-vram-recover-doesn-t-work-after-whole-gpu-reset-v2.patch b/queue-6.3/drm-amdgpu-fix-vram-recover-doesn-t-work-after-whole-gpu-reset-v2.patch new file mode 100644 index 00000000000..ecbd43564a2 --- /dev/null +++ b/queue-6.3/drm-amdgpu-fix-vram-recover-doesn-t-work-after-whole-gpu-reset-v2.patch @@ -0,0 +1,42 @@ +From 6c032c37ac3ef3b7df30937c785ecc4da428edc0 Mon Sep 17 00:00:00 2001 +From: "Lin.Cao" +Date: Mon, 8 May 2023 17:28:41 +0800 +Subject: drm/amdgpu: Fix vram recover doesn't work after whole GPU reset (v2) +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +From: Lin.Cao + +commit 6c032c37ac3ef3b7df30937c785ecc4da428edc0 upstream. + +v1: Vmbo->shadow is used to back vram bo up when vram lost. So that we +should set shadow as vmbo->shadow to recover vmbo->bo +v2: Modify if(vmbo->shadow) shadow = vmbo->shadow as if(!vmbo->shadow) +continue; + +Fixes: e18aaea733da ("drm/amdgpu: move shadow_list to amdgpu_bo_vm") +Reviewed-by: Christian König +Signed-off-by: Lin.Cao +Signed-off-by: Alex Deucher +Cc: stable@vger.kernel.org +Signed-off-by: Greg Kroah-Hartman +--- + drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 6 +++++- + 1 file changed, 5 insertions(+), 1 deletion(-) + +--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c ++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c +@@ -4482,7 +4482,11 @@ static int amdgpu_device_recover_vram(st + dev_info(adev->dev, "recover vram bo from shadow start\n"); + mutex_lock(&adev->shadow_list_lock); + list_for_each_entry(vmbo, &adev->shadow_list, shadow_list) { +- shadow = &vmbo->bo; ++ /* If vm is compute context or adev is APU, shadow will be NULL */ ++ if (!vmbo->shadow) ++ continue; ++ shadow = vmbo->shadow; ++ + /* No need to recover an evicted BO */ + if (shadow->tbo.resource->mem_type != TTM_PL_TT || + shadow->tbo.resource->start == AMDGPU_BO_INVALID_OFFSET || diff --git a/queue-6.3/drm-amdgpu-gfx-disable-gfx9-cp_ecc_error_irq-only-when-enabling-legacy-gfx-ras.patch b/queue-6.3/drm-amdgpu-gfx-disable-gfx9-cp_ecc_error_irq-only-when-enabling-legacy-gfx-ras.patch new file mode 100644 index 00000000000..26dc1a702d8 --- /dev/null +++ b/queue-6.3/drm-amdgpu-gfx-disable-gfx9-cp_ecc_error_irq-only-when-enabling-legacy-gfx-ras.patch @@ -0,0 +1,59 @@ +From 4a76680311330aefe5074bed8f06afa354b85c48 Mon Sep 17 00:00:00 2001 +From: Guchun Chen +Date: Sat, 6 May 2023 20:06:45 +0800 +Subject: drm/amdgpu/gfx: disable gfx9 cp_ecc_error_irq only when enabling legacy gfx ras + +From: Guchun Chen + +commit 4a76680311330aefe5074bed8f06afa354b85c48 upstream. + +gfx9 cp_ecc_error_irq is only enabled when legacy gfx ras is assert. +So in gfx_v9_0_hw_fini, interrupt disablement for cp_ecc_error_irq +should be executed under such condition, otherwise, an amdgpu_irq_put +calltrace will occur. + +[ 7283.170322] RIP: 0010:amdgpu_irq_put+0x45/0x70 [amdgpu] +[ 7283.170964] RSP: 0018:ffff9a5fc3967d00 EFLAGS: 00010246 +[ 7283.170967] RAX: ffff98d88afd3040 RBX: ffff98d89da20000 RCX: 0000000000000000 +[ 7283.170969] RDX: 0000000000000000 RSI: ffff98d89da2bef8 RDI: ffff98d89da20000 +[ 7283.170971] RBP: ffff98d89da20000 R08: ffff98d89da2ca18 R09: 0000000000000006 +[ 7283.170973] R10: ffffd5764243c008 R11: 0000000000000000 R12: 0000000000001050 +[ 7283.170975] R13: ffff98d89da38978 R14: ffffffff999ae15a R15: ffff98d880130105 +[ 7283.170978] FS: 0000000000000000(0000) GS:ffff98d996f00000(0000) knlGS:0000000000000000 +[ 7283.170981] CS: 0010 DS: 0000 ES: 0000 CR0: 0000000080050033 +[ 7283.170983] CR2: 00000000f7a9d178 CR3: 00000001c42ea000 CR4: 00000000003506e0 +[ 7283.170986] Call Trace: +[ 7283.170988] +[ 7283.170989] gfx_v9_0_hw_fini+0x1c/0x6d0 [amdgpu] +[ 7283.171655] amdgpu_device_ip_suspend_phase2+0x101/0x1a0 [amdgpu] +[ 7283.172245] amdgpu_device_suspend+0x103/0x180 [amdgpu] +[ 7283.172823] amdgpu_pmops_freeze+0x21/0x60 [amdgpu] +[ 7283.173412] pci_pm_freeze+0x54/0xc0 +[ 7283.173419] ? __pfx_pci_pm_freeze+0x10/0x10 +[ 7283.173425] dpm_run_callback+0x98/0x200 +[ 7283.173430] __device_suspend+0x164/0x5f0 + +v2: drop gfx11 as it's fixed in a different solution by retiring cp_ecc_irq funcs(Hawking) + +Link: https://gitlab.freedesktop.org/drm/amd/-/issues/2522 +Signed-off-by: Guchun Chen +Reviewed-by: Tao Zhou +Signed-off-by: Alex Deucher +Cc: stable@vger.kernel.org +Signed-off-by: Greg Kroah-Hartman +--- + drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 3 ++- + 1 file changed, 2 insertions(+), 1 deletion(-) + +--- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c ++++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c +@@ -3751,7 +3751,8 @@ static int gfx_v9_0_hw_fini(void *handle + { + struct amdgpu_device *adev = (struct amdgpu_device *)handle; + +- amdgpu_irq_put(adev, &adev->gfx.cp_ecc_error_irq, 0); ++ if (amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__GFX)) ++ amdgpu_irq_put(adev, &adev->gfx.cp_ecc_error_irq, 0); + amdgpu_irq_put(adev, &adev->gfx.priv_reg_irq, 0); + amdgpu_irq_put(adev, &adev->gfx.priv_inst_irq, 0); + diff --git a/queue-6.3/drm-amdgpu-jpeg-remove-harvest-checking-for-jpeg3.patch b/queue-6.3/drm-amdgpu-jpeg-remove-harvest-checking-for-jpeg3.patch new file mode 100644 index 00000000000..1cf105d3873 --- /dev/null +++ b/queue-6.3/drm-amdgpu-jpeg-remove-harvest-checking-for-jpeg3.patch @@ -0,0 +1,30 @@ +From 5b94db73e45e2e6c2840f39c022fd71dfa47fc58 Mon Sep 17 00:00:00 2001 +From: Saleemkhan Jamadar +Date: Tue, 9 May 2023 12:37:50 +0530 +Subject: drm/amdgpu/jpeg: Remove harvest checking for JPEG3 + +From: Saleemkhan Jamadar + +commit 5b94db73e45e2e6c2840f39c022fd71dfa47fc58 upstream. + +Register CC_UVD_HARVESTING is obsolete for JPEG 3.1.2 + +Signed-off-by: Saleemkhan Jamadar +Reviewed-by: Veerabadhran Gopalakrishnan +Signed-off-by: Alex Deucher +Cc: stable@vger.kernel.org # 6.1.x +Signed-off-by: Greg Kroah-Hartman +--- + drivers/gpu/drm/amd/amdgpu/jpeg_v3_0.c | 1 + + 1 file changed, 1 insertion(+) + +--- a/drivers/gpu/drm/amd/amdgpu/jpeg_v3_0.c ++++ b/drivers/gpu/drm/amd/amdgpu/jpeg_v3_0.c +@@ -54,6 +54,7 @@ static int jpeg_v3_0_early_init(void *ha + + switch (adev->ip_versions[UVD_HWIP][0]) { + case IP_VERSION(3, 1, 1): ++ case IP_VERSION(3, 1, 2): + break; + default: + harvest = RREG32_SOC15(JPEG, 0, mmCC_UVD_HARVESTING); diff --git a/queue-6.3/series b/queue-6.3/series index 9dc3e198c88..35e6cb4f648 100644 --- a/queue-6.3/series +++ b/queue-6.3/series @@ -187,3 +187,22 @@ irqchip-loongson-eiointc-fix-returned-value-on-parsing-madt.patch irqchip-loongson-eiointc-fix-incorrect-use-of-acpi_get_vec_parent.patch irqchip-loongson-eiointc-fix-registration-of-syscore_ops.patch drm-panel-otm8009a-set-backlight-parent-to-panel-device.patch +drm-amd-display-add-null-plane_state-check-for-cursor-disable-logic.patch +drm-amd-display-fix-4to1-mpc-black-screen-with-dpp-rco.patch +drm-amd-display-filter-out-invalid-bits-in-pipe_fuses.patch +drm-amd-display-fix-access-hdcp_workqueue-assert.patch +drm-amd-display-fix-flickering-caused-by-s-g-mode.patch +drm-amdgpu-drop-redundant-sched-job-cleanup-when-cs-is-aborted.patch +drm-amd-display-change-default-z8-watermark-values.patch +drm-amdgpu-fix-amdgpu_irq_put-call-trace-in-gmc_v10_0_hw_fini.patch +drm-amdgpu-fix-an-amdgpu_irq_put-issue-in-gmc_v9_0_hw_fini.patch +drm-amdgpu-fix-amdgpu_irq_put-call-trace-in-gmc_v11_0_hw_fini.patch +drm-amdgpu-gfx-disable-gfx9-cp_ecc_error_irq-only-when-enabling-legacy-gfx-ras.patch +drm-amdgpu-jpeg-remove-harvest-checking-for-jpeg3.patch +drm-amdgpu-change-gfx-11.0.4-external_id-range.patch +drm-amdgpu-fix-vram-recover-doesn-t-work-after-whole-gpu-reset-v2.patch +drm-amd-display-enforce-60us-prefetch-for-200mhz-dcfclk-modes.patch +drm-amd-pm-parse-pp_handle-under-appropriate-conditions.patch +drm-amdgpu-drop-gfx_v11_0_cp_ecc_error_irq_funcs.patch +drm-amdgpu-disable-sdma-ecc-irq-only-when-sdma-ras-is-enabled-in-suspend.patch +drm-amd-pm-avoid-potential-ubsan-issue-on-legacy-asics.patch