From: Aurelien Jarno Date: Mon, 1 May 2017 21:20:43 +0000 (+0200) Subject: target/sh4: optimize gen_write_sr using extract op X-Git-Tag: v2.10.0-rc0~191^2~5 X-Git-Url: http://git.ipfire.org/?a=commitdiff_plain;h=a380f9db96dc94e5109611e4fd0fb4f671e30143;p=thirdparty%2Fqemu.git target/sh4: optimize gen_write_sr using extract op This doesn't change the generated code on x86, but optimizes it on most RISC architectures and makes the code simpler to read. Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson Signed-off-by: Aurelien Jarno --- diff --git a/target/sh4/translate.c b/target/sh4/translate.c index fe8bff54a6d..7a504a7f5ab 100644 --- a/target/sh4/translate.c +++ b/target/sh4/translate.c @@ -204,12 +204,9 @@ static void gen_write_sr(TCGv src) { tcg_gen_andi_i32(cpu_sr, src, ~((1u << SR_Q) | (1u << SR_M) | (1u << SR_T))); - tcg_gen_shri_i32(cpu_sr_q, src, SR_Q); - tcg_gen_andi_i32(cpu_sr_q, cpu_sr_q, 1); - tcg_gen_shri_i32(cpu_sr_m, src, SR_M); - tcg_gen_andi_i32(cpu_sr_m, cpu_sr_m, 1); - tcg_gen_shri_i32(cpu_sr_t, src, SR_T); - tcg_gen_andi_i32(cpu_sr_t, cpu_sr_t, 1); + tcg_gen_extract_i32(cpu_sr_q, src, SR_Q, 1); + tcg_gen_extract_i32(cpu_sr_m, src, SR_M, 1); + tcg_gen_extract_i32(cpu_sr_t, src, SR_T, 1); } static inline void gen_save_cpu_state(DisasContext *ctx, bool save_pc)