From: T Karthik Reddy <t.karthik.reddy@xilinx.com>
Date: Tue, 12 Mar 2019 14:50:20 +0000 (+0530)
Subject: fpga: zynqpl: Check fpga config completion
X-Git-Url: http://git.ipfire.org/?a=commitdiff_plain;h=a3d1bdb13705a446ecbb1dc49bed7bdf6e6f49b7;p=thirdparty%2Fu-boot.git

fpga: zynqpl: Check fpga config completion

This patch checks fpga config completion when a bitstream is loaded
into PL.

Signed-off-by: T Karthik Reddy <t.karthik.reddy@xilinx.com>
Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
---

diff --git a/drivers/fpga/zynqpl.c b/drivers/fpga/zynqpl.c
index 9745d8a7152..eabeb8aa873 100644
--- a/drivers/fpga/zynqpl.c
+++ b/drivers/fpga/zynqpl.c
@@ -548,22 +548,22 @@ int zynq_decrypt_load(u32 srcaddr, u32 srclen, u32 dstaddr, u32 dstlen,
 	if (zynq_dma_transfer(srcaddr | 1, srclen, dstaddr | 1, dstlen))
 		return FPGA_FAIL;
 
-	isr_status = readl(&devcfg_base->int_sts);
-	/* Check FPGA configuration completion */
-	ts = get_timer(0);
-	while (!(isr_status & DEVCFG_ISR_PCFG_DONE)) {
-		if (get_timer(ts) > CONFIG_SYS_FPGA_WAIT) {
-			printf("%s: Timeout wait for FPGA to config\n",
-			       __func__);
-			return FPGA_FAIL;
-		}
+	if (bstype == BIT_FULL) {
 		isr_status = readl(&devcfg_base->int_sts);
+		/* Check FPGA configuration completion */
+		ts = get_timer(0);
+		while (!(isr_status & DEVCFG_ISR_PCFG_DONE)) {
+			if (get_timer(ts) > CONFIG_SYS_FPGA_WAIT) {
+				printf("%s: Timeout wait for FPGA to config\n",
+				       __func__);
+				return FPGA_FAIL;
+			}
+			isr_status = readl(&devcfg_base->int_sts);
+		}
+		printf("%s: FPGA config done\n", __func__);
+		zynq_slcr_devcfg_enable();
 	}
 
-	printf("%s: FPGA config done\n", __func__);
-
-	zynq_slcr_devcfg_enable();
-
 	return FPGA_SUCCESS;
 }
 #endif