From: Imre Deak Date: Mon, 22 Jul 2024 16:54:54 +0000 (+0300) Subject: drm/i915/dp: Initialize the link parameters during HW readout X-Git-Tag: v6.12-rc1~126^2~22^2~31 X-Git-Url: http://git.ipfire.org/?a=commitdiff_plain;h=a3f91f405aa7c54d0856c1b8698e4ff05ae7d439;p=thirdparty%2Fkernel%2Flinux.git drm/i915/dp: Initialize the link parameters during HW readout Initialize the DP link parameters during HW readout. These need to be up-to-date at least for the MST topology probing, which depends on the link rate and lane count programmed in DPCD. A follow-up patch will program the DPCD values to reflect the maximum link parameters before the first MST topology probing, but should do so only if the link is disabled (link_trained==false). Reviewed-by: Suraj Kandpal Signed-off-by: Imre Deak Link: https://patchwork.freedesktop.org/patch/msgid/20240722165503.2084999-6-imre.deak@intel.com --- diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c index 86412ae7b48f7..32964e15f3b11 100644 --- a/drivers/gpu/drm/i915/display/intel_dp.c +++ b/drivers/gpu/drm/i915/display/intel_dp.c @@ -3352,8 +3352,11 @@ void intel_dp_sync_state(struct intel_encoder *encoder, intel_dp_tunnel_resume(intel_dp, crtc_state, dpcd_updated); - if (crtc_state) + if (crtc_state) { intel_dp_reset_link_params(intel_dp); + intel_dp_set_link_params(intel_dp, crtc_state->port_clock, crtc_state->lane_count); + intel_dp->link_trained = true; + } } bool intel_dp_initial_fastset_check(struct intel_encoder *encoder,