From: Rodrigo Siqueira Date: Tue, 2 Apr 2024 23:39:42 +0000 (-0600) Subject: drm/amd/display: Group scl_data together in resource_build_scaling_params X-Git-Tag: v6.10-rc1~148^2~19^2~42 X-Git-Url: http://git.ipfire.org/?a=commitdiff_plain;h=a50f6fddbaefc26ec2c9a401ea3e71fd5d25582d;p=thirdparty%2Flinux.git drm/amd/display: Group scl_data together in resource_build_scaling_params Move the scl_data.format to be close to other similar parts. Reviewed-by: Leo Li Signed-off-by: Rodrigo Siqueira Tested-by: Daniel Wheeler Signed-off-by: Alex Deucher --- diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c index 2633e481234f3..876b0e5eda95f 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c @@ -1500,9 +1500,6 @@ bool resource_build_scaling_params(struct pipe_ctx *pipe_ctx) return false; } - pipe_ctx->plane_res.scl_data.format = convert_pixel_format_to_dalsurface( - pipe_ctx->plane_state->format); - /* Timing borders are part of vactive that we are also supposed to skip in addition * to any stream dst offset. Since dm logic assumes dst is in addressable * space we need to add the left and top borders to dst offsets temporarily. @@ -1514,6 +1511,8 @@ bool resource_build_scaling_params(struct pipe_ctx *pipe_ctx) /* Calculate H and V active size */ pipe_ctx->plane_res.scl_data.h_active = odm_slice_rec.width; pipe_ctx->plane_res.scl_data.v_active = odm_slice_rec.height; + pipe_ctx->plane_res.scl_data.format = convert_pixel_format_to_dalsurface( + pipe_ctx->plane_state->format); /* depends on h_active */ calculate_recout(pipe_ctx);