From: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Date: Sun, 18 Aug 2024 17:28:43 +0000 (+0200)
Subject: dt-bindings: PCI: socionext,uniphier-pcie-ep: Add top-level constraints
X-Git-Tag: v6.12-rc1~96^2~20^2~8
X-Git-Url: http://git.ipfire.org/?a=commitdiff_plain;h=a5c1bf7e9a4638fbb27461e9801f07204b50dcb6;p=thirdparty%2Fkernel%2Flinux.git

dt-bindings: PCI: socionext,uniphier-pcie-ep: Add top-level constraints

Properties with variable number of items per each device are expected to
have widest constraints in top-level "properties:" block and further
customized (narrowed) in "if:then:".

Add missing top-level constraints for clock-names and reset-names.

Link: https://lore.kernel.org/linux-pci/20240818172843.121787-3-krzysztof.kozlowski@linaro.org
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Krzysztof Wilczyński <kwilczynski@kernel.org>
Reviewed-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
Reviewed-by: Rob Herring (Arm) <robh@kernel.org>
---

diff --git a/Documentation/devicetree/bindings/pci/socionext,uniphier-pcie-ep.yaml b/Documentation/devicetree/bindings/pci/socionext,uniphier-pcie-ep.yaml
index f0d8e486a07da..93f3d0f4bb942 100644
--- a/Documentation/devicetree/bindings/pci/socionext,uniphier-pcie-ep.yaml
+++ b/Documentation/devicetree/bindings/pci/socionext,uniphier-pcie-ep.yaml
@@ -38,13 +38,17 @@ properties:
     minItems: 1
     maxItems: 2
 
-  clock-names: true
+  clock-names:
+    minItems: 1
+    maxItems: 2
 
   resets:
     minItems: 1
     maxItems: 2
 
-  reset-names: true
+  reset-names:
+    minItems: 1
+    maxItems: 2
 
   num-ib-windows:
     const: 16