From: Greg Kroah-Hartman Date: Fri, 25 Jun 2021 09:29:00 +0000 (+0200) Subject: 4.19-stable patches X-Git-Tag: v5.12.14~56 X-Git-Url: http://git.ipfire.org/?a=commitdiff_plain;h=a5d6a005b11f17803b8e261e6d3d13091ff043cc;p=thirdparty%2Fkernel%2Fstable-queue.git 4.19-stable patches added patches: arm-9081-1-fix-gcc-10-thumb2-kernel-regression.patch drm-nouveau-wait-for-moving-fence-after-pinning-v2.patch drm-radeon-wait-for-moving-fence-after-pinning.patch --- diff --git a/queue-4.19/arm-9081-1-fix-gcc-10-thumb2-kernel-regression.patch b/queue-4.19/arm-9081-1-fix-gcc-10-thumb2-kernel-regression.patch new file mode 100644 index 00000000000..9e8a47c96cc --- /dev/null +++ b/queue-4.19/arm-9081-1-fix-gcc-10-thumb2-kernel-regression.patch @@ -0,0 +1,81 @@ +From dad7b9896a5dbac5da8275d5a6147c65c81fb5f2 Mon Sep 17 00:00:00 2001 +From: Arnd Bergmann +Date: Fri, 14 May 2021 11:26:37 +0100 +Subject: ARM: 9081/1: fix gcc-10 thumb2-kernel regression + +From: Arnd Bergmann + +commit dad7b9896a5dbac5da8275d5a6147c65c81fb5f2 upstream. + +When building the kernel wtih gcc-10 or higher using the +CONFIG_CC_OPTIMIZE_FOR_PERFORMANCE=y flag, the compiler picks a slightly +different set of registers for the inline assembly in cpu_init() that +subsequently results in a corrupt kernel stack as well as remaining in +FIQ mode. If a banked register is used for the last argument, the wrong +version of that register gets loaded into CPSR_c. When building in Arm +mode, the arguments are passed as immediate values and the bug cannot +happen. + +This got introduced when Daniel reworked the FIQ handling and was +technically always broken, but happened to work with both clang and gcc +before gcc-10 as long as they picked one of the lower registers. +This is probably an indication that still very few people build the +kernel in Thumb2 mode. + +Marek pointed out the problem on IRC, Arnd narrowed it down to this +inline assembly and Russell pinpointed the exact bug. + +Change the constraints to force the final mode switch to use a non-banked +register for the argument to ensure that the correct constant gets loaded. +Another alternative would be to always use registers for the constant +arguments to avoid the #ifdef that has now become more complex. + +Cc: # v3.18+ +Cc: Daniel Thompson +Reported-by: Marek Vasut +Acked-by: Ard Biesheuvel +Fixes: c0e7f7ee717e ("ARM: 8150/3: fiq: Replace default FIQ handler") +Signed-off-by: Arnd Bergmann +Signed-off-by: Russell King +Signed-off-by: Greg Kroah-Hartman +--- + arch/arm/kernel/setup.c | 16 +++++++++------- + 1 file changed, 9 insertions(+), 7 deletions(-) + +--- a/arch/arm/kernel/setup.c ++++ b/arch/arm/kernel/setup.c +@@ -547,9 +547,11 @@ void notrace cpu_init(void) + * In Thumb-2, msr with an immediate value is not allowed. + */ + #ifdef CONFIG_THUMB2_KERNEL +-#define PLC "r" ++#define PLC_l "l" ++#define PLC_r "r" + #else +-#define PLC "I" ++#define PLC_l "I" ++#define PLC_r "I" + #endif + + /* +@@ -571,15 +573,15 @@ void notrace cpu_init(void) + "msr cpsr_c, %9" + : + : "r" (stk), +- PLC (PSR_F_BIT | PSR_I_BIT | IRQ_MODE), ++ PLC_r (PSR_F_BIT | PSR_I_BIT | IRQ_MODE), + "I" (offsetof(struct stack, irq[0])), +- PLC (PSR_F_BIT | PSR_I_BIT | ABT_MODE), ++ PLC_r (PSR_F_BIT | PSR_I_BIT | ABT_MODE), + "I" (offsetof(struct stack, abt[0])), +- PLC (PSR_F_BIT | PSR_I_BIT | UND_MODE), ++ PLC_r (PSR_F_BIT | PSR_I_BIT | UND_MODE), + "I" (offsetof(struct stack, und[0])), +- PLC (PSR_F_BIT | PSR_I_BIT | FIQ_MODE), ++ PLC_r (PSR_F_BIT | PSR_I_BIT | FIQ_MODE), + "I" (offsetof(struct stack, fiq[0])), +- PLC (PSR_F_BIT | PSR_I_BIT | SVC_MODE) ++ PLC_l (PSR_F_BIT | PSR_I_BIT | SVC_MODE) + : "r14"); + #endif + } diff --git a/queue-4.19/drm-nouveau-wait-for-moving-fence-after-pinning-v2.patch b/queue-4.19/drm-nouveau-wait-for-moving-fence-after-pinning-v2.patch new file mode 100644 index 00000000000..945ac7c0148 --- /dev/null +++ b/queue-4.19/drm-nouveau-wait-for-moving-fence-after-pinning-v2.patch @@ -0,0 +1,53 @@ +From 17b11f71795abdce46f62a808f906857e525cea8 Mon Sep 17 00:00:00 2001 +From: =?UTF-8?q?Christian=20K=C3=B6nig?= +Date: Mon, 21 Jun 2021 13:36:35 +0200 +Subject: drm/nouveau: wait for moving fence after pinning v2 +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +From: Christian König + +commit 17b11f71795abdce46f62a808f906857e525cea8 upstream. + +We actually need to wait for the moving fence after pinning +the BO to make sure that the pin is completed. + +v2: grab the lock while waiting + +Signed-off-by: Christian König +Reviewed-by: Daniel Vetter +References: https://lore.kernel.org/dri-devel/20210621151758.2347474-1-daniel.vetter@ffwll.ch/ +CC: stable@kernel.org +Link: https://patchwork.freedesktop.org/patch/msgid/20210622114506.106349-1-christian.koenig@amd.com +Signed-off-by: Greg Kroah-Hartman +--- + drivers/gpu/drm/nouveau/nouveau_prime.c | 17 ++++++++++++++++- + 1 file changed, 16 insertions(+), 1 deletion(-) + +--- a/drivers/gpu/drm/nouveau/nouveau_prime.c ++++ b/drivers/gpu/drm/nouveau/nouveau_prime.c +@@ -98,7 +98,22 @@ int nouveau_gem_prime_pin(struct drm_gem + if (ret) + return -EINVAL; + +- return 0; ++ ret = ttm_bo_reserve(&nvbo->bo, false, false, NULL); ++ if (ret) ++ goto error; ++ ++ if (nvbo->bo.moving) ++ ret = dma_fence_wait(nvbo->bo.moving, true); ++ ++ ttm_bo_unreserve(&nvbo->bo); ++ if (ret) ++ goto error; ++ ++ return ret; ++ ++error: ++ nouveau_bo_unpin(nvbo); ++ return ret; + } + + void nouveau_gem_prime_unpin(struct drm_gem_object *obj) diff --git a/queue-4.19/drm-radeon-wait-for-moving-fence-after-pinning.patch b/queue-4.19/drm-radeon-wait-for-moving-fence-after-pinning.patch new file mode 100644 index 00000000000..fe483418050 --- /dev/null +++ b/queue-4.19/drm-radeon-wait-for-moving-fence-after-pinning.patch @@ -0,0 +1,49 @@ +From 4b41726aae563273bb4b4a9462ba51ce4d372f78 Mon Sep 17 00:00:00 2001 +From: =?UTF-8?q?Christian=20K=C3=B6nig?= +Date: Mon, 21 Jun 2021 13:43:05 +0200 +Subject: drm/radeon: wait for moving fence after pinning +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +From: Christian König + +commit 4b41726aae563273bb4b4a9462ba51ce4d372f78 upstream. + +We actually need to wait for the moving fence after pinning +the BO to make sure that the pin is completed. + +Signed-off-by: Christian König +Reviewed-by: Daniel Vetter +References: https://lore.kernel.org/dri-devel/20210621151758.2347474-1-daniel.vetter@ffwll.ch/ +CC: stable@kernel.org +Link: https://patchwork.freedesktop.org/patch/msgid/20210622114506.106349-2-christian.koenig@amd.com +Signed-off-by: Greg Kroah-Hartman +--- + drivers/gpu/drm/radeon/radeon_prime.c | 14 ++++++++++++-- + 1 file changed, 12 insertions(+), 2 deletions(-) + +--- a/drivers/gpu/drm/radeon/radeon_prime.c ++++ b/drivers/gpu/drm/radeon/radeon_prime.c +@@ -92,9 +92,19 @@ int radeon_gem_prime_pin(struct drm_gem_ + + /* pin buffer into GTT */ + ret = radeon_bo_pin(bo, RADEON_GEM_DOMAIN_GTT, NULL); +- if (likely(ret == 0)) +- bo->prime_shared_count++; ++ if (unlikely(ret)) ++ goto error; + ++ if (bo->tbo.moving) { ++ ret = dma_fence_wait(bo->tbo.moving, false); ++ if (unlikely(ret)) { ++ radeon_bo_unpin(bo); ++ goto error; ++ } ++ } ++ ++ bo->prime_shared_count++; ++error: + radeon_bo_unreserve(bo); + return ret; + } diff --git a/queue-4.19/series b/queue-4.19/series index a9377295a48..a0b64d470b2 100644 --- a/queue-4.19/series +++ b/queue-4.19/series @@ -81,3 +81,6 @@ usb-dwc3-debugfs-add-and-remove-endpoint-dirs-dynamically.patch usb-dwc3-core-fix-kernel-panic-when-do-reboot.patch x86-fpu-reset-state-for-all-signal-restore-failures.patch module-limit-enabling-module.sig_enforce.patch +drm-nouveau-wait-for-moving-fence-after-pinning-v2.patch +drm-radeon-wait-for-moving-fence-after-pinning.patch +arm-9081-1-fix-gcc-10-thumb2-kernel-regression.patch