From: Pan Nengyuan <pannengyuan@huawei.com>
Date: Tue, 10 Dec 2019 07:14:37 +0000 (+0800)
Subject: riscv/sifive_u: fix a memory leak in soc_realize()
X-Git-Tag: v4.2.1~69
X-Git-Url: http://git.ipfire.org/?a=commitdiff_plain;h=a6e44eee6c6567b1cbf0365bd95f9f199d8f2764;p=thirdparty%2Fqemu.git

riscv/sifive_u: fix a memory leak in soc_realize()

Fix a minor memory leak in riscv_sifive_u_soc_realize()

Reported-by: Euler Robot <euler.robot@huawei.com>
Signed-off-by: Pan Nengyuan <pannengyuan@huawei.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Palmer Dabbelt <palmerdabbelt@google.com>
(cherry picked from commit bb8136df698bd565ee4f6c18d26c50dee320bfe4)
Signed-off-by: Michael Roth <mdroth@linux.vnet.ibm.com>
---

diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c
index 0140e95732a..0e12b3ccef5 100644
--- a/hw/riscv/sifive_u.c
+++ b/hw/riscv/sifive_u.c
@@ -542,6 +542,7 @@ static void riscv_sifive_u_soc_realize(DeviceState *dev, Error **errp)
         SIFIVE_U_PLIC_CONTEXT_BASE,
         SIFIVE_U_PLIC_CONTEXT_STRIDE,
         memmap[SIFIVE_U_PLIC].size);
+    g_free(plic_hart_config);
     sifive_uart_create(system_memory, memmap[SIFIVE_U_UART0].base,
         serial_hd(0), qdev_get_gpio_in(DEVICE(s->plic), SIFIVE_U_UART0_IRQ));
     sifive_uart_create(system_memory, memmap[SIFIVE_U_UART1].base,