From: Greg Kroah-Hartman Date: Tue, 1 Mar 2016 20:00:50 +0000 (-0800) Subject: 4.4-stable patches X-Git-Tag: v3.10.99~23 X-Git-Url: http://git.ipfire.org/?a=commitdiff_plain;h=a6ef5104ba9e90e23da54b48bc5a524145a0e04c;p=thirdparty%2Fkernel%2Fstable-queue.git 4.4-stable patches added patches: drm-add-helper-to-check-for-wc-memory-support.patch drm-fix-missing-reference-counting-decrease.patch drm-radeon-add-a-common-function-for-dfs-handling.patch drm-radeon-call-hpd_irq_event-on-resume.patch drm-radeon-clean-up-fujitsu-quirks.patch drm-radeon-cleaned-up-vco-output-settings-for-dp-audio.patch drm-radeon-fix-dp-audio-support-for-apu-with-dce4.1-display-engine.patch drm-radeon-fix-off-by-one-errors-in-radeon_vm_bo_set_addr.patch drm-radeon-fix-slow-audio-over-dp-on-dce8.patch drm-radeon-hold-reference-to-fences-in-radeon_sa_bo_new.patch drm-radeon-mask-out-wc-from-bo-on-unsupported-arches.patch drm-radeon-properly-byte-swap-vce-firmware-setup.patch --- diff --git a/queue-4.4/drm-add-helper-to-check-for-wc-memory-support.patch b/queue-4.4/drm-add-helper-to-check-for-wc-memory-support.patch new file mode 100644 index 00000000000..6d4bd341db4 --- /dev/null +++ b/queue-4.4/drm-add-helper-to-check-for-wc-memory-support.patch @@ -0,0 +1,38 @@ +From 4b0e4e4af6c6dc8354dcb72182d52c1bc55f12fc Mon Sep 17 00:00:00 2001 +From: Dave Airlie +Date: Sat, 30 Jan 2016 07:59:32 +0200 +Subject: drm: add helper to check for wc memory support +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +From: Dave Airlie + +commit 4b0e4e4af6c6dc8354dcb72182d52c1bc55f12fc upstream. + +Reviewed-by: Christian König +Reviewed-by: Michel Dänzer +Signed-off-by: Dave Airlie +Signed-off-by: Oded Gabbay +Signed-off-by: Alex Deucher +Cc: stable@vger.kernel.org +Signed-off-by: Greg Kroah-Hartman + +diff --git a/include/drm/drm_cache.h b/include/drm/drm_cache.h +index 7bfb063029d8..461a0558bca4 100644 +--- a/include/drm/drm_cache.h ++++ b/include/drm/drm_cache.h +@@ -35,4 +35,13 @@ + + void drm_clflush_pages(struct page *pages[], unsigned long num_pages); + ++static inline bool drm_arch_can_wc_memory(void) ++{ ++#if defined(CONFIG_PPC) && !defined(CONFIG_NOT_COHERENT_CACHE) ++ return false; ++#else ++ return true; ++#endif ++} ++ + #endif diff --git a/queue-4.4/drm-fix-missing-reference-counting-decrease.patch b/queue-4.4/drm-fix-missing-reference-counting-decrease.patch new file mode 100644 index 00000000000..1828f215fbc --- /dev/null +++ b/queue-4.4/drm-fix-missing-reference-counting-decrease.patch @@ -0,0 +1,30 @@ +From dabe19540af9e563d526113bb102e1b9b9fa73f9 Mon Sep 17 00:00:00 2001 +From: Insu Yun +Date: Mon, 1 Feb 2016 11:08:29 -0500 +Subject: drm: fix missing reference counting decrease + +From: Insu Yun + +commit dabe19540af9e563d526113bb102e1b9b9fa73f9 upstream. + +In drm_dp_mst_allocate_vcpi, it returns true in two paths, +but in one path, there is no reference couting decrease. + +Signed-off-by: Insu Yun +Signed-off-by: Dave Airlie +Signed-off-by: Greg Kroah-Hartman + +--- + drivers/gpu/drm/drm_dp_mst_topology.c | 1 + + 1 file changed, 1 insertion(+) + +--- a/drivers/gpu/drm/drm_dp_mst_topology.c ++++ b/drivers/gpu/drm/drm_dp_mst_topology.c +@@ -2463,6 +2463,7 @@ bool drm_dp_mst_allocate_vcpi(struct drm + DRM_DEBUG_KMS("payload: vcpi %d already allocated for pbn %d - requested pbn %d\n", port->vcpi.vcpi, port->vcpi.pbn, pbn); + if (pbn == port->vcpi.pbn) { + *slots = port->vcpi.num_slots; ++ drm_dp_put_port(port); + return true; + } + } diff --git a/queue-4.4/drm-radeon-add-a-common-function-for-dfs-handling.patch b/queue-4.4/drm-radeon-add-a-common-function-for-dfs-handling.patch new file mode 100644 index 00000000000..8cf13f400d0 --- /dev/null +++ b/queue-4.4/drm-radeon-add-a-common-function-for-dfs-handling.patch @@ -0,0 +1,77 @@ +From a64c9dab1c4d05c87ec8a1cb9b48915816462143 Mon Sep 17 00:00:00 2001 +From: Slava Grigorev +Date: Tue, 26 Jan 2016 16:56:25 -0500 +Subject: drm/radeon: Add a common function for DFS handling +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +From: Slava Grigorev + +commit a64c9dab1c4d05c87ec8a1cb9b48915816462143 upstream. + +Move encoding of DFS (digital frequency synthesizer) divider into a +separate function and improve calculation precision. + +Signed-off-by: Slava Grigorev +Reviewed-by: Alex Deucher +Reviewed-by: Christian König +Signed-off-by: Alex Deucher +Signed-off-by: Greg Kroah-Hartman + +--- + drivers/gpu/drm/radeon/dce6_afmt.c | 12 ++---------- + drivers/gpu/drm/radeon/radeon_audio.c | 12 ++++++++++++ + drivers/gpu/drm/radeon/radeon_audio.h | 1 + + 3 files changed, 15 insertions(+), 10 deletions(-) + +--- a/drivers/gpu/drm/radeon/dce6_afmt.c ++++ b/drivers/gpu/drm/radeon/dce6_afmt.c +@@ -304,18 +304,10 @@ void dce6_dp_audio_set_dto(struct radeon + unsigned int div = (RREG32(DENTIST_DISPCLK_CNTL) & + DENTIST_DPREFCLK_WDIVIDER_MASK) >> + DENTIST_DPREFCLK_WDIVIDER_SHIFT; +- +- if (div < 128 && div >= 96) +- div -= 64; +- else if (div >= 64) +- div = div / 2 - 16; +- else if (div >= 8) +- div /= 4; +- else +- div = 0; ++ div = radeon_audio_decode_dfs_div(div); + + if (div) +- clock /= div; ++ clock = clock * 100 / div; + + WREG32(DCE8_DCCG_AUDIO_DTO1_PHASE, 24000); + WREG32(DCE8_DCCG_AUDIO_DTO1_MODULE, clock); +--- a/drivers/gpu/drm/radeon/radeon_audio.c ++++ b/drivers/gpu/drm/radeon/radeon_audio.c +@@ -775,3 +775,15 @@ void radeon_audio_dpms(struct drm_encode + if (radeon_encoder->audio && radeon_encoder->audio->dpms) + radeon_encoder->audio->dpms(encoder, mode == DRM_MODE_DPMS_ON); + } ++ ++unsigned int radeon_audio_decode_dfs_div(unsigned int div) ++{ ++ if (div >= 8 && div < 64) ++ return (div - 8) * 25 + 200; ++ else if (div >= 64 && div < 96) ++ return (div - 64) * 50 + 1600; ++ else if (div >= 96 && div < 128) ++ return (div - 96) * 100 + 3200; ++ else ++ return 0; ++} +--- a/drivers/gpu/drm/radeon/radeon_audio.h ++++ b/drivers/gpu/drm/radeon/radeon_audio.h +@@ -79,5 +79,6 @@ void radeon_audio_fini(struct radeon_dev + void radeon_audio_mode_set(struct drm_encoder *encoder, + struct drm_display_mode *mode); + void radeon_audio_dpms(struct drm_encoder *encoder, int mode); ++unsigned int radeon_audio_decode_dfs_div(unsigned int div); + + #endif diff --git a/queue-4.4/drm-radeon-call-hpd_irq_event-on-resume.patch b/queue-4.4/drm-radeon-call-hpd_irq_event-on-resume.patch new file mode 100644 index 00000000000..a24ba9b7146 --- /dev/null +++ b/queue-4.4/drm-radeon-call-hpd_irq_event-on-resume.patch @@ -0,0 +1,29 @@ +From dbb17a21c131eca94eb31136eee9a7fe5aff00d9 Mon Sep 17 00:00:00 2001 +From: Alex Deucher +Date: Tue, 24 Nov 2015 14:32:44 -0500 +Subject: drm/radeon: call hpd_irq_event on resume + +From: Alex Deucher + +commit dbb17a21c131eca94eb31136eee9a7fe5aff00d9 upstream. + +Need to call this on resume if displays changes during +suspend in order to properly be notified of changes. + +Signed-off-by: Alex Deucher +Signed-off-by: Greg Kroah-Hartman + +--- + drivers/gpu/drm/radeon/radeon_device.c | 1 + + 1 file changed, 1 insertion(+) + +--- a/drivers/gpu/drm/radeon/radeon_device.c ++++ b/drivers/gpu/drm/radeon/radeon_device.c +@@ -1744,6 +1744,7 @@ int radeon_resume_kms(struct drm_device + } + + drm_kms_helper_poll_enable(dev); ++ drm_helper_hpd_irq_event(dev); + + /* set the power state here in case we are a PX system or headless */ + if ((rdev->pm.pm_method == PM_METHOD_DPM) && rdev->pm.dpm_enabled) diff --git a/queue-4.4/drm-radeon-clean-up-fujitsu-quirks.patch b/queue-4.4/drm-radeon-clean-up-fujitsu-quirks.patch new file mode 100644 index 00000000000..86206327761 --- /dev/null +++ b/queue-4.4/drm-radeon-clean-up-fujitsu-quirks.patch @@ -0,0 +1,49 @@ +From 0eb1c3d4084eeb6fb3a703f88d6ce1521f8fcdd1 Mon Sep 17 00:00:00 2001 +From: Alex Deucher +Date: Thu, 17 Dec 2015 12:52:17 -0500 +Subject: drm/radeon: clean up fujitsu quirks + +From: Alex Deucher + +commit 0eb1c3d4084eeb6fb3a703f88d6ce1521f8fcdd1 upstream. + +Combine the two quirks. + +bug: +https://bugzilla.kernel.org/show_bug.cgi?id=109481 + +Signed-off-by: Alex Deucher +Signed-off-by: Greg Kroah-Hartman + +--- + drivers/gpu/drm/radeon/radeon_atombios.c | 12 +++--------- + 1 file changed, 3 insertions(+), 9 deletions(-) + +--- a/drivers/gpu/drm/radeon/radeon_atombios.c ++++ b/drivers/gpu/drm/radeon/radeon_atombios.c +@@ -437,7 +437,9 @@ static bool radeon_atom_apply_quirks(str + } + + /* Fujitsu D3003-S2 board lists DVI-I as DVI-D and VGA */ +- if (((dev->pdev->device == 0x9802) || (dev->pdev->device == 0x9806)) && ++ if (((dev->pdev->device == 0x9802) || ++ (dev->pdev->device == 0x9805) || ++ (dev->pdev->device == 0x9806)) && + (dev->pdev->subsystem_vendor == 0x1734) && + (dev->pdev->subsystem_device == 0x11bd)) { + if (*connector_type == DRM_MODE_CONNECTOR_VGA) { +@@ -448,14 +450,6 @@ static bool radeon_atom_apply_quirks(str + } + } + +- /* Fujitsu D3003-S2 board lists DVI-I as DVI-I and VGA */ +- if ((dev->pdev->device == 0x9805) && +- (dev->pdev->subsystem_vendor == 0x1734) && +- (dev->pdev->subsystem_device == 0x11bd)) { +- if (*connector_type == DRM_MODE_CONNECTOR_VGA) +- return false; +- } +- + return true; + } + diff --git a/queue-4.4/drm-radeon-cleaned-up-vco-output-settings-for-dp-audio.patch b/queue-4.4/drm-radeon-cleaned-up-vco-output-settings-for-dp-audio.patch new file mode 100644 index 00000000000..ace2ace3cff --- /dev/null +++ b/queue-4.4/drm-radeon-cleaned-up-vco-output-settings-for-dp-audio.patch @@ -0,0 +1,95 @@ +From c9a392eac18409f51a071520cf508c0b4ad990e2 Mon Sep 17 00:00:00 2001 +From: Slava Grigorev +Date: Tue, 26 Jan 2016 16:45:10 -0500 +Subject: drm/radeon: cleaned up VCO output settings for DP audio +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +From: Slava Grigorev + +commit c9a392eac18409f51a071520cf508c0b4ad990e2 upstream. + +This is preparation for the fixes in the following patches. + +Signed-off-by: Slava Grigorev +Reviewed-by: Alex Deucher +Reviewed-by: Christian König +Signed-off-by: Alex Deucher +Signed-off-by: Greg Kroah-Hartman + +--- + drivers/gpu/drm/radeon/dce6_afmt.c | 2 +- + drivers/gpu/drm/radeon/radeon.h | 2 +- + drivers/gpu/drm/radeon/radeon_atombios.c | 12 +++++++----- + drivers/gpu/drm/radeon/radeon_audio.c | 8 +------- + 4 files changed, 10 insertions(+), 14 deletions(-) + +--- a/drivers/gpu/drm/radeon/dce6_afmt.c ++++ b/drivers/gpu/drm/radeon/dce6_afmt.c +@@ -315,7 +315,7 @@ void dce6_dp_audio_set_dto(struct radeon + div = 0; + + if (div) +- clock = rdev->clock.gpupll_outputfreq * 10 / div; ++ clock /= div; + + WREG32(DCE8_DCCG_AUDIO_DTO1_PHASE, 24000); + WREG32(DCE8_DCCG_AUDIO_DTO1_MODULE, clock); +--- a/drivers/gpu/drm/radeon/radeon.h ++++ b/drivers/gpu/drm/radeon/radeon.h +@@ -268,7 +268,7 @@ struct radeon_clock { + uint32_t current_dispclk; + uint32_t dp_extclk; + uint32_t max_pixel_clock; +- uint32_t gpupll_outputfreq; ++ uint32_t vco_freq; + }; + + /* +--- a/drivers/gpu/drm/radeon/radeon_atombios.c ++++ b/drivers/gpu/drm/radeon/radeon_atombios.c +@@ -1257,12 +1257,14 @@ bool radeon_atom_get_clock_info(struct d + rdev->mode_info.firmware_flags = + le16_to_cpu(firmware_info->info.usFirmwareCapability.susAccess); + +- if (ASIC_IS_DCE8(rdev)) { +- rdev->clock.gpupll_outputfreq = ++ if (ASIC_IS_DCE8(rdev)) ++ rdev->clock.vco_freq = + le32_to_cpu(firmware_info->info_22.ulGPUPLL_OutputFreq); +- if (rdev->clock.gpupll_outputfreq == 0) +- rdev->clock.gpupll_outputfreq = 360000; /* 3.6 GHz */ +- } ++ else ++ rdev->clock.vco_freq = rdev->clock.current_dispclk; ++ ++ if (rdev->clock.vco_freq == 0) ++ rdev->clock.vco_freq = 360000; /* 3.6 GHz */ + + return true; + } +--- a/drivers/gpu/drm/radeon/radeon_audio.c ++++ b/drivers/gpu/drm/radeon/radeon_audio.c +@@ -739,9 +739,6 @@ static void radeon_audio_dp_mode_set(str + struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); + struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv; + struct drm_connector *connector = radeon_get_connector_for_encoder(encoder); +- struct radeon_connector *radeon_connector = to_radeon_connector(connector); +- struct radeon_connector_atom_dig *dig_connector = +- radeon_connector->con_priv; + + if (!dig || !dig->afmt) + return; +@@ -753,10 +750,7 @@ static void radeon_audio_dp_mode_set(str + radeon_audio_write_speaker_allocation(encoder); + radeon_audio_write_sad_regs(encoder); + radeon_audio_write_latency_fields(encoder, mode); +- if (rdev->clock.dp_extclk || ASIC_IS_DCE5(rdev)) +- radeon_audio_set_dto(encoder, rdev->clock.default_dispclk * 10); +- else +- radeon_audio_set_dto(encoder, dig_connector->dp_clock); ++ radeon_audio_set_dto(encoder, rdev->clock.vco_freq * 10); + radeon_audio_set_audio_packet(encoder); + radeon_audio_select_pin(encoder); + diff --git a/queue-4.4/drm-radeon-fix-dp-audio-support-for-apu-with-dce4.1-display-engine.patch b/queue-4.4/drm-radeon-fix-dp-audio-support-for-apu-with-dce4.1-display-engine.patch new file mode 100644 index 00000000000..23a5d9d9cf0 --- /dev/null +++ b/queue-4.4/drm-radeon-fix-dp-audio-support-for-apu-with-dce4.1-display-engine.patch @@ -0,0 +1,119 @@ +From fe6fc1f132b4300c1f6defd43a5d673eb60a820d Mon Sep 17 00:00:00 2001 +From: Slava Grigorev +Date: Tue, 26 Jan 2016 17:35:57 -0500 +Subject: drm/radeon: fix DP audio support for APU with DCE4.1 display engine +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +From: Slava Grigorev + +commit fe6fc1f132b4300c1f6defd43a5d673eb60a820d upstream. + +Properly setup the DFS divider for DP audio for DCE4.1. + +Signed-off-by: Slava Grigorev +Reviewed-by: Alex Deucher +Reviewed-by: Christian König +Signed-off-by: Alex Deucher +Signed-off-by: Greg Kroah-Hartman + +--- + drivers/gpu/drm/radeon/evergreen_hdmi.c | 10 ++++++++ + drivers/gpu/drm/radeon/evergreend.h | 5 ++++ + drivers/gpu/drm/radeon/radeon_atombios.c | 37 ++++++++++++++++++++++++------- + 3 files changed, 44 insertions(+), 8 deletions(-) + +--- a/drivers/gpu/drm/radeon/evergreen_hdmi.c ++++ b/drivers/gpu/drm/radeon/evergreen_hdmi.c +@@ -289,6 +289,16 @@ void dce4_dp_audio_set_dto(struct radeon + * number (coefficient of two integer numbers. DCCG_AUDIO_DTOx_PHASE + * is the numerator, DCCG_AUDIO_DTOx_MODULE is the denominator + */ ++ if (ASIC_IS_DCE41(rdev)) { ++ unsigned int div = (RREG32(DCE41_DENTIST_DISPCLK_CNTL) & ++ DENTIST_DPREFCLK_WDIVIDER_MASK) >> ++ DENTIST_DPREFCLK_WDIVIDER_SHIFT; ++ div = radeon_audio_decode_dfs_div(div); ++ ++ if (div) ++ clock = 100 * clock / div; ++ } ++ + WREG32(DCCG_AUDIO_DTO1_PHASE, 24000); + WREG32(DCCG_AUDIO_DTO1_MODULE, clock); + } +--- a/drivers/gpu/drm/radeon/evergreend.h ++++ b/drivers/gpu/drm/radeon/evergreend.h +@@ -511,6 +511,11 @@ + #define DCCG_AUDIO_DTO1_CNTL 0x05cc + # define DCCG_AUDIO_DTO1_USE_512FBR_DTO (1 << 3) + ++#define DCE41_DENTIST_DISPCLK_CNTL 0x049c ++# define DENTIST_DPREFCLK_WDIVIDER(x) (((x) & 0x7f) << 24) ++# define DENTIST_DPREFCLK_WDIVIDER_MASK (0x7f << 24) ++# define DENTIST_DPREFCLK_WDIVIDER_SHIFT 24 ++ + /* DCE 4.0 AFMT */ + #define HDMI_CONTROL 0x7030 + # define HDMI_KEEPOUT_MODE (1 << 0) +--- a/drivers/gpu/drm/radeon/radeon_atombios.c ++++ b/drivers/gpu/drm/radeon/radeon_atombios.c +@@ -1106,6 +1106,31 @@ union firmware_info { + ATOM_FIRMWARE_INFO_V2_2 info_22; + }; + ++union igp_info { ++ struct _ATOM_INTEGRATED_SYSTEM_INFO info; ++ struct _ATOM_INTEGRATED_SYSTEM_INFO_V2 info_2; ++ struct _ATOM_INTEGRATED_SYSTEM_INFO_V6 info_6; ++ struct _ATOM_INTEGRATED_SYSTEM_INFO_V1_7 info_7; ++ struct _ATOM_INTEGRATED_SYSTEM_INFO_V1_8 info_8; ++}; ++ ++static void radeon_atombios_get_dentist_vco_freq(struct radeon_device *rdev) ++{ ++ struct radeon_mode_info *mode_info = &rdev->mode_info; ++ int index = GetIndexIntoMasterTable(DATA, IntegratedSystemInfo); ++ union igp_info *igp_info; ++ u8 frev, crev; ++ u16 data_offset; ++ ++ if (atom_parse_data_header(mode_info->atom_context, index, NULL, ++ &frev, &crev, &data_offset)) { ++ igp_info = (union igp_info *)(mode_info->atom_context->bios + ++ data_offset); ++ rdev->clock.vco_freq = ++ le32_to_cpu(igp_info->info_6.ulDentistVCOFreq); ++ } ++} ++ + bool radeon_atom_get_clock_info(struct drm_device *dev) + { + struct radeon_device *rdev = dev->dev_private; +@@ -1260,6 +1285,10 @@ bool radeon_atom_get_clock_info(struct d + if (ASIC_IS_DCE8(rdev)) + rdev->clock.vco_freq = + le32_to_cpu(firmware_info->info_22.ulGPUPLL_OutputFreq); ++ else if (ASIC_IS_DCE5(rdev)) ++ rdev->clock.vco_freq = rdev->clock.current_dispclk; ++ else if (ASIC_IS_DCE41(rdev)) ++ radeon_atombios_get_dentist_vco_freq(rdev); + else + rdev->clock.vco_freq = rdev->clock.current_dispclk; + +@@ -1272,14 +1301,6 @@ bool radeon_atom_get_clock_info(struct d + return false; + } + +-union igp_info { +- struct _ATOM_INTEGRATED_SYSTEM_INFO info; +- struct _ATOM_INTEGRATED_SYSTEM_INFO_V2 info_2; +- struct _ATOM_INTEGRATED_SYSTEM_INFO_V6 info_6; +- struct _ATOM_INTEGRATED_SYSTEM_INFO_V1_7 info_7; +- struct _ATOM_INTEGRATED_SYSTEM_INFO_V1_8 info_8; +-}; +- + bool radeon_atombios_sideport_present(struct radeon_device *rdev) + { + struct radeon_mode_info *mode_info = &rdev->mode_info; diff --git a/queue-4.4/drm-radeon-fix-off-by-one-errors-in-radeon_vm_bo_set_addr.patch b/queue-4.4/drm-radeon-fix-off-by-one-errors-in-radeon_vm_bo_set_addr.patch new file mode 100644 index 00000000000..83f993a2ec6 --- /dev/null +++ b/queue-4.4/drm-radeon-fix-off-by-one-errors-in-radeon_vm_bo_set_addr.patch @@ -0,0 +1,75 @@ +From 42ef344c0994cc453477afdc7a8eadc578ed0257 Mon Sep 17 00:00:00 2001 +From: Felix Kuehling +Date: Mon, 23 Nov 2015 17:39:11 -0500 +Subject: drm/radeon: Fix off-by-one errors in radeon_vm_bo_set_addr +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +From: Felix Kuehling + +commit 42ef344c0994cc453477afdc7a8eadc578ed0257 upstream. + +eoffset is sometimes treated as the last address inside the address +range, and sometimes as the first address outside the range. This +was resulting in errors when a test filled up the entire address +space. Make it consistent to always be the last address within the +range. Also fixed related errors when checking the VA limit and in +radeon_vm_fence_pts. + +Signed-off-by: Felix.Kuehling +Reviewed-by: Christian König +Signed-off-by: Greg Kroah-Hartman + +--- + drivers/gpu/drm/radeon/radeon_vm.c | 12 ++++++------ + 1 file changed, 6 insertions(+), 6 deletions(-) + +--- a/drivers/gpu/drm/radeon/radeon_vm.c ++++ b/drivers/gpu/drm/radeon/radeon_vm.c +@@ -455,15 +455,15 @@ int radeon_vm_bo_set_addr(struct radeon_ + + if (soffset) { + /* make sure object fit at this offset */ +- eoffset = soffset + size; ++ eoffset = soffset + size - 1; + if (soffset >= eoffset) { + r = -EINVAL; + goto error_unreserve; + } + + last_pfn = eoffset / RADEON_GPU_PAGE_SIZE; +- if (last_pfn > rdev->vm_manager.max_pfn) { +- dev_err(rdev->dev, "va above limit (0x%08X > 0x%08X)\n", ++ if (last_pfn >= rdev->vm_manager.max_pfn) { ++ dev_err(rdev->dev, "va above limit (0x%08X >= 0x%08X)\n", + last_pfn, rdev->vm_manager.max_pfn); + r = -EINVAL; + goto error_unreserve; +@@ -478,7 +478,7 @@ int radeon_vm_bo_set_addr(struct radeon_ + eoffset /= RADEON_GPU_PAGE_SIZE; + if (soffset || eoffset) { + struct interval_tree_node *it; +- it = interval_tree_iter_first(&vm->va, soffset, eoffset - 1); ++ it = interval_tree_iter_first(&vm->va, soffset, eoffset); + if (it && it != &bo_va->it) { + struct radeon_bo_va *tmp; + tmp = container_of(it, struct radeon_bo_va, it); +@@ -518,7 +518,7 @@ int radeon_vm_bo_set_addr(struct radeon_ + if (soffset || eoffset) { + spin_lock(&vm->status_lock); + bo_va->it.start = soffset; +- bo_va->it.last = eoffset - 1; ++ bo_va->it.last = eoffset; + list_add(&bo_va->vm_status, &vm->cleared); + spin_unlock(&vm->status_lock); + interval_tree_insert(&bo_va->it, &vm->va); +@@ -888,7 +888,7 @@ static void radeon_vm_fence_pts(struct r + unsigned i; + + start >>= radeon_vm_block_size; +- end >>= radeon_vm_block_size; ++ end = (end - 1) >> radeon_vm_block_size; + + for (i = start; i <= end; ++i) + radeon_bo_fence(vm->page_tables[i].bo, fence, true); diff --git a/queue-4.4/drm-radeon-fix-slow-audio-over-dp-on-dce8.patch b/queue-4.4/drm-radeon-fix-slow-audio-over-dp-on-dce8.patch new file mode 100644 index 00000000000..e28581d6571 --- /dev/null +++ b/queue-4.4/drm-radeon-fix-slow-audio-over-dp-on-dce8.patch @@ -0,0 +1,87 @@ +From ac4a9350abddc51ccb897abf0d9f3fd592b97e0b Mon Sep 17 00:00:00 2001 +From: Slava Grigorev +Date: Thu, 17 Dec 2015 11:09:58 -0500 +Subject: drm/radeon: Fix "slow" audio over DP on DCE8+ + +From: Slava Grigorev + +commit ac4a9350abddc51ccb897abf0d9f3fd592b97e0b upstream. + +DP audio is derived from the dfs clock. + +Signed-off-by: Slava Grigorev +Reviewed-by: Alex Deucher +Signed-off-by: Greg Kroah-Hartman + +--- + drivers/gpu/drm/radeon/dce6_afmt.c | 16 ++++++++++++++++ + drivers/gpu/drm/radeon/radeon.h | 1 + + drivers/gpu/drm/radeon/radeon_atombios.c | 7 +++++++ + drivers/gpu/drm/radeon/sid.h | 5 +++++ + 4 files changed, 29 insertions(+) + +--- a/drivers/gpu/drm/radeon/dce6_afmt.c ++++ b/drivers/gpu/drm/radeon/dce6_afmt.c +@@ -301,6 +301,22 @@ void dce6_dp_audio_set_dto(struct radeon + * is the numerator, DCCG_AUDIO_DTOx_MODULE is the denominator + */ + if (ASIC_IS_DCE8(rdev)) { ++ unsigned int div = (RREG32(DENTIST_DISPCLK_CNTL) & ++ DENTIST_DPREFCLK_WDIVIDER_MASK) >> ++ DENTIST_DPREFCLK_WDIVIDER_SHIFT; ++ ++ if (div < 128 && div >= 96) ++ div -= 64; ++ else if (div >= 64) ++ div = div / 2 - 16; ++ else if (div >= 8) ++ div /= 4; ++ else ++ div = 0; ++ ++ if (div) ++ clock = rdev->clock.gpupll_outputfreq * 10 / div; ++ + WREG32(DCE8_DCCG_AUDIO_DTO1_PHASE, 24000); + WREG32(DCE8_DCCG_AUDIO_DTO1_MODULE, clock); + } else { +--- a/drivers/gpu/drm/radeon/radeon.h ++++ b/drivers/gpu/drm/radeon/radeon.h +@@ -268,6 +268,7 @@ struct radeon_clock { + uint32_t current_dispclk; + uint32_t dp_extclk; + uint32_t max_pixel_clock; ++ uint32_t gpupll_outputfreq; + }; + + /* +--- a/drivers/gpu/drm/radeon/radeon_atombios.c ++++ b/drivers/gpu/drm/radeon/radeon_atombios.c +@@ -1263,6 +1263,13 @@ bool radeon_atom_get_clock_info(struct d + rdev->mode_info.firmware_flags = + le16_to_cpu(firmware_info->info.usFirmwareCapability.susAccess); + ++ if (ASIC_IS_DCE8(rdev)) { ++ rdev->clock.gpupll_outputfreq = ++ le32_to_cpu(firmware_info->info_22.ulGPUPLL_OutputFreq); ++ if (rdev->clock.gpupll_outputfreq == 0) ++ rdev->clock.gpupll_outputfreq = 360000; /* 3.6 GHz */ ++ } ++ + return true; + } + +--- a/drivers/gpu/drm/radeon/sid.h ++++ b/drivers/gpu/drm/radeon/sid.h +@@ -915,6 +915,11 @@ + #define DCCG_AUDIO_DTO1_PHASE 0x05c0 + #define DCCG_AUDIO_DTO1_MODULE 0x05c4 + ++#define DENTIST_DISPCLK_CNTL 0x0490 ++# define DENTIST_DPREFCLK_WDIVIDER(x) (((x) & 0x7f) << 24) ++# define DENTIST_DPREFCLK_WDIVIDER_MASK (0x7f << 24) ++# define DENTIST_DPREFCLK_WDIVIDER_SHIFT 24 ++ + #define AFMT_AUDIO_SRC_CONTROL 0x713c + #define AFMT_AUDIO_SRC_SELECT(x) (((x) & 7) << 0) + /* AFMT_AUDIO_SRC_SELECT diff --git a/queue-4.4/drm-radeon-hold-reference-to-fences-in-radeon_sa_bo_new.patch b/queue-4.4/drm-radeon-hold-reference-to-fences-in-radeon_sa_bo_new.patch new file mode 100644 index 00000000000..0bfa6f36900 --- /dev/null +++ b/queue-4.4/drm-radeon-hold-reference-to-fences-in-radeon_sa_bo_new.patch @@ -0,0 +1,42 @@ +From f6ff4f67cdf8455d0a4226eeeaf5af17c37d05eb Mon Sep 17 00:00:00 2001 +From: =?UTF-8?q?Nicolai=20H=C3=A4hnle?= +Date: Fri, 5 Feb 2016 14:35:53 -0500 +Subject: drm/radeon: hold reference to fences in radeon_sa_bo_new +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +From: Nicolai Hähnle + +commit f6ff4f67cdf8455d0a4226eeeaf5af17c37d05eb upstream. + +An arbitrary amount of time can pass between spin_unlock and +radeon_fence_wait_any, so we need to ensure that nobody frees the +fences from under us. + +Based on the analogous fix for amdgpu. + +Signed-off-by: Nicolai Hähnle +Reviewed-by: Christian König +Signed-off-by: Greg Kroah-Hartman + +--- + drivers/gpu/drm/radeon/radeon_sa.c | 5 +++++ + 1 file changed, 5 insertions(+) + +--- a/drivers/gpu/drm/radeon/radeon_sa.c ++++ b/drivers/gpu/drm/radeon/radeon_sa.c +@@ -349,8 +349,13 @@ int radeon_sa_bo_new(struct radeon_devic + /* see if we can skip over some allocations */ + } while (radeon_sa_bo_next_hole(sa_manager, fences, tries)); + ++ for (i = 0; i < RADEON_NUM_RINGS; ++i) ++ radeon_fence_ref(fences[i]); ++ + spin_unlock(&sa_manager->wq.lock); + r = radeon_fence_wait_any(rdev, fences, false); ++ for (i = 0; i < RADEON_NUM_RINGS; ++i) ++ radeon_fence_unref(&fences[i]); + spin_lock(&sa_manager->wq.lock); + /* if we have nothing to wait for block */ + if (r == -ENOENT) { diff --git a/queue-4.4/drm-radeon-mask-out-wc-from-bo-on-unsupported-arches.patch b/queue-4.4/drm-radeon-mask-out-wc-from-bo-on-unsupported-arches.patch new file mode 100644 index 00000000000..5086e1ce515 --- /dev/null +++ b/queue-4.4/drm-radeon-mask-out-wc-from-bo-on-unsupported-arches.patch @@ -0,0 +1,45 @@ +From c5244987394648913ae1a03879c58058a2fc2cee Mon Sep 17 00:00:00 2001 +From: Oded Gabbay +Date: Sat, 30 Jan 2016 07:59:33 +0200 +Subject: drm/radeon: mask out WC from BO on unsupported arches +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +From: Oded Gabbay + +commit c5244987394648913ae1a03879c58058a2fc2cee upstream. + +Reviewed-by: Christian König +Reviewed-by: Michel Dänzer +Signed-off-by: Oded Gabbay +Signed-off-by: Alex Deucher +Signed-off-by: Greg Kroah-Hartman + +--- + drivers/gpu/drm/radeon/radeon_object.c | 7 +++++++ + 1 file changed, 7 insertions(+) + +--- a/drivers/gpu/drm/radeon/radeon_object.c ++++ b/drivers/gpu/drm/radeon/radeon_object.c +@@ -33,6 +33,7 @@ + #include + #include + #include ++#include + #include "radeon.h" + #include "radeon_trace.h" + +@@ -245,6 +246,12 @@ int radeon_bo_create(struct radeon_devic + DRM_INFO_ONCE("Please enable CONFIG_MTRR and CONFIG_X86_PAT for " + "better performance thanks to write-combining\n"); + bo->flags &= ~(RADEON_GEM_GTT_WC | RADEON_GEM_GTT_UC); ++#else ++ /* For architectures that don't support WC memory, ++ * mask out the WC flag from the BO ++ */ ++ if (!drm_arch_can_wc_memory()) ++ bo->flags &= ~RADEON_GEM_GTT_WC; + #endif + + radeon_ttm_placement_from_domain(bo, domain); diff --git a/queue-4.4/drm-radeon-properly-byte-swap-vce-firmware-setup.patch b/queue-4.4/drm-radeon-properly-byte-swap-vce-firmware-setup.patch new file mode 100644 index 00000000000..949cc32283a --- /dev/null +++ b/queue-4.4/drm-radeon-properly-byte-swap-vce-firmware-setup.patch @@ -0,0 +1,63 @@ +From cc78eb22885bba64445cde438ba098de0104920f Mon Sep 17 00:00:00 2001 +From: Alex Deucher +Date: Fri, 22 Jan 2016 00:13:15 -0500 +Subject: drm/radeon: properly byte swap vce firmware setup +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +From: Alex Deucher + +commit cc78eb22885bba64445cde438ba098de0104920f upstream. + +Firmware is LE. Need to properly byteswap some of the fields +so they are interpreted correctly by the driver on BE systems. + +Reviewed-by: Christian König +Signed-off-by: Alex Deucher +Signed-off-by: Greg Kroah-Hartman + +--- + drivers/gpu/drm/radeon/vce_v1_0.c | 12 ++++++------ + 1 file changed, 6 insertions(+), 6 deletions(-) + +--- a/drivers/gpu/drm/radeon/vce_v1_0.c ++++ b/drivers/gpu/drm/radeon/vce_v1_0.c +@@ -178,12 +178,12 @@ int vce_v1_0_load_fw(struct radeon_devic + return -EINVAL; + } + +- for (i = 0; i < sign->num; ++i) { +- if (sign->val[i].chip_id == chip_id) ++ for (i = 0; i < le32_to_cpu(sign->num); ++i) { ++ if (le32_to_cpu(sign->val[i].chip_id) == chip_id) + break; + } + +- if (i == sign->num) ++ if (i == le32_to_cpu(sign->num)) + return -EINVAL; + + data += (256 - 64) / 4; +@@ -191,18 +191,18 @@ int vce_v1_0_load_fw(struct radeon_devic + data[1] = sign->val[i].nonce[1]; + data[2] = sign->val[i].nonce[2]; + data[3] = sign->val[i].nonce[3]; +- data[4] = sign->len + 64; ++ data[4] = cpu_to_le32(le32_to_cpu(sign->len) + 64); + + memset(&data[5], 0, 44); + memcpy(&data[16], &sign[1], rdev->vce_fw->size - sizeof(*sign)); + +- data += data[4] / 4; ++ data += le32_to_cpu(data[4]) / 4; + data[0] = sign->val[i].sigval[0]; + data[1] = sign->val[i].sigval[1]; + data[2] = sign->val[i].sigval[2]; + data[3] = sign->val[i].sigval[3]; + +- rdev->vce.keyselect = sign->val[i].keyselect; ++ rdev->vce.keyselect = le32_to_cpu(sign->val[i].keyselect); + + return 0; + } diff --git a/queue-4.4/series b/queue-4.4/series index 95bf492c5c5..a551131ff41 100644 --- a/queue-4.4/series +++ b/queue-4.4/series @@ -202,3 +202,15 @@ drm-dp-mst-calculate-mst-pbn-with-31.32-fixed-point.patch drm-dp-mst-move-guid-storage-from-mgr-port-to-only-mst-branch.patch drm-dp-mst-reverse-order-of-mst-enable-and-clearing-vc-payload-table.patch drm-dp-mst-deallocate-payload-on-port-destruction.patch +drm-radeon-fix-off-by-one-errors-in-radeon_vm_bo_set_addr.patch +drm-radeon-call-hpd_irq_event-on-resume.patch +drm-radeon-fix-slow-audio-over-dp-on-dce8.patch +drm-radeon-clean-up-fujitsu-quirks.patch +drm-radeon-properly-byte-swap-vce-firmware-setup.patch +drm-radeon-cleaned-up-vco-output-settings-for-dp-audio.patch +drm-radeon-add-a-common-function-for-dfs-handling.patch +drm-radeon-fix-dp-audio-support-for-apu-with-dce4.1-display-engine.patch +drm-add-helper-to-check-for-wc-memory-support.patch +drm-radeon-mask-out-wc-from-bo-on-unsupported-arches.patch +drm-radeon-hold-reference-to-fences-in-radeon_sa_bo_new.patch +drm-fix-missing-reference-counting-decrease.patch