From: Stefan Hajnoczi <stefanha@redhat.com>
Date: Fri, 4 Jul 2025 12:58:27 +0000 (-0400)
Subject: Merge tag 'pull-aspeed-20250704' of https://github.com/legoater/qemu into staging
X-Git-Tag: v10.1.0-rc0~34
X-Git-Url: http://git.ipfire.org/?a=commitdiff_plain;h=a876b05d38c813501e60fb50c8a45b30a965e902;p=thirdparty%2Fqemu.git

Merge tag 'pull-aspeed-20250704' of https://github.com/legoater/qemu into staging

aspeed queue:

* Improved AST2700 SoC modeling (SDMC, SCU)
* Fixed hardware strapping of 'bletchley-bmc' machine
* Added new Meta 'catalina-bmc' machine and functional test using OpenBMC
* Improved AST2600 SCU protection key modeling
* Introduced AST2600 SCU unit tests
* Deprecated 'ast2700a0-evb' machine
* Added new NVIDIA 'gb200-bmc' machine and functional test using OpenBMC

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# gpg: Signature made Fri 04 Jul 2025 04:36:05 EDT
# gpg:                using RSA key A0F66548F04895EBFE6B0B6051A343C7CFFBECA1
# gpg: Good signature from "Cédric Le Goater <clg@redhat.com>" [full]
# gpg:                 aka "Cédric Le Goater <clg@kaod.org>" [full]
# Primary key fingerprint: A0F6 6548 F048 95EB FE6B  0B60 51A3 43C7 CFFB ECA1

* tag 'pull-aspeed-20250704' of https://github.com/legoater/qemu:
  tests/functional: Add gb200 tests
  hw/arm/aspeed: Add GB200 BMC target
  docs: add support for gb200-bmc
  hw/arm/aspeed: Add second SPI chip to Aspeed model
  aspeed: Deprecate the ast2700a0-evb machine
  tests/qtest: Add test for ASPEED SCU
  hw/misc/aspeed_scu: Handle AST2600 protection key registers correctly
  hw/arm/aspeed: add Catalina machine type
  hw/arm/aspeed: bletchley: update hw strap values
  hw/misc/aspeed_scu: Support the Frequency Counter Control register for AST2700
  hw/misc/aspeed_sdmc: Skipping dram_init in u-boot for AST2700

Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
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a876b05d38c813501e60fb50c8a45b30a965e902