From: Julian Seward <jseward@acm.org>
Date: Wed, 30 Mar 2005 23:20:47 +0000 (+0000)
Subject: Support a few more insns I ran across whilst trying to start up
X-Git-Tag: svn/VALGRIND_3_0_1^2~219
X-Git-Url: http://git.ipfire.org/?a=commitdiff_plain;h=ab603b820f9f9dcf2f41e9c41737750ed0f89e78;p=thirdparty%2Fvalgrind.git

Support a few more insns I ran across whilst trying to start up
konqueror (mostly successfully) and mozilla (promising but
unsuccessful).



git-svn-id: svn://svn.valgrind.org/vex/trunk@1115
---

diff --git a/VEX/priv/guest-amd64/toIR.c b/VEX/priv/guest-amd64/toIR.c
index 647651d370..91846b9a6c 100644
--- a/VEX/priv/guest-amd64/toIR.c
+++ b/VEX/priv/guest-amd64/toIR.c
@@ -3605,9 +3605,9 @@ ULong dis_Grp3 ( Prefix pfx, Int sz, ULong delta )
          case 4: /* MUL (unsigned widening) */
             codegen_mulL_A_D ( sz, False, t1, dis_buf );
             break;
-//..          case 5: /* IMUL */
-//..             codegen_mulL_A_D ( sz, True, t1, dis_buf );
-//..             break;
+         case 5: /* IMUL */
+            codegen_mulL_A_D ( sz, True, t1, dis_buf );
+            break;
          case 6: /* DIV */
             codegen_div ( sz, t1, False );
             DIP("div%c %s\n", nameISize(sz), dis_buf);
@@ -8060,11 +8060,12 @@ DisResult disInstr ( /*IN*/  Bool       resteerOK,
       goto decode_success;
    }
 
-//..    /* 0F 55 = ANDNPS -- G = (not G) and E */
-//..    if (sz == 4 && insn[0] == 0x0F && insn[1] == 0x55) {
-//..       delta = dis_SSE_E_to_G_all_invG( sorb, delta+2, "andnps", Iop_And128 );
-//..       goto decode_success;
-//..    }
+   /* 0F 55 = ANDNPS -- G = (not G) and E */
+   if (haveNo66noF2noF3(pfx) && sz == 4 
+       && insn[0] == 0x0F && insn[1] == 0x55) {
+      delta = dis_SSE_E_to_G_all_invG( pfx, delta+2, "andnps", Iop_AndV128 );
+      goto decode_success;
+   }
 
    /* 0F 54 = ANDPS -- G = G and E */
    if (haveNo66noF2noF3(pfx) && sz == 4 
@@ -8077,15 +8078,15 @@ DisResult disInstr ( /*IN*/  Bool       resteerOK,
 //..    if (sz == 4 && insn[0] == 0x0F && insn[1] == 0xC2) {
 //..       delta = dis_SSEcmp_E_to_G( sorb, delta+2, "cmpps", True, 4 );
 //..       goto decode_success;
-//..    }
-//.. 
-//..    /* F3 0F C2 = CMPSS -- 32F0x4 comparison from R/M to R */
-//..    if (insn[0] == 0xF3 && insn[1] == 0x0F && insn[2] == 0xC2) {
-//..       vassert(sz == 4);
-//..       delta = dis_SSEcmp_E_to_G( sorb, delta+3, "cmpss", False, 4 );
-//..       goto decode_success;
 //..    }
 
+   /* F3 0F C2 = CMPSS -- 32F0x4 comparison from R/M to R */
+   if (haveF3no66noF2(pfx) && sz == 4
+       && insn[0] == 0x0F && insn[1] == 0xC2) {
+      delta = dis_SSEcmp_E_to_G( pfx, delta+2, "cmpss", False, 4 );
+      goto decode_success;
+   }
+
    /* 0F 2F = COMISS  -- 32F0x4 comparison G,E, and set ZCP */
    /* 0F 2E = UCOMISS -- 32F0x4 comparison G,E, and set ZCP */
    if (haveNo66noF2noF3(pfx) && sz == 4 
@@ -8700,12 +8701,13 @@ DisResult disInstr ( /*IN*/  Bool       resteerOK,
       goto decode_success;
    }
 
-//..    /* 0F 56 = ORPS -- G = G and E */
-//..    if (sz == 4 && insn[0] == 0x0F && insn[1] == 0x56) {
-//..       delta = dis_SSE_E_to_G_all( sorb, delta+2, "orps", Iop_Or128 );
-//..       goto decode_success;
-//..    }
-//.. 
+   /* 0F 56 = ORPS -- G = G and E */
+   if (haveNo66noF2noF3(pfx) && sz == 4
+       && insn[0] == 0x0F && insn[1] == 0x56) {
+      delta = dis_SSE_E_to_G_all( pfx, delta+2, "orps", Iop_OrV128 );
+      goto decode_success;
+   }
+
 //..    /* ***--- this is an MMX class insn introduced in SSE1 ---*** */
 //..    /* 0F E0 = PAVGB -- 8x8 unsigned Packed Average, with rounding */
 //..    if (sz == 4 && insn[0] == 0x0F && insn[1] == 0xE0) {
diff --git a/VEX/priv/host-amd64/hdefs.c b/VEX/priv/host-amd64/hdefs.c
index d22ee707d7..821def08f7 100644
--- a/VEX/priv/host-amd64/hdefs.c
+++ b/VEX/priv/host-amd64/hdefs.c
@@ -3109,7 +3109,7 @@ Int emit_AMD64Instr ( UChar* buf, Int nbuf, AMD64Instr* i )
 //..          case Xsse_SQRTF:  *p++ = 0x51; break;
          case Asse_SUBF:   *p++ = 0x5C; break;
 //..          case Xsse_CMPEQF: *p++ = 0xC2; xtra = 0x100; break;
-//..          case Xsse_CMPLTF: *p++ = 0xC2; xtra = 0x101; break;
+         case Asse_CMPLTF: *p++ = 0xC2; xtra = 0x101; break;
 //..          case Xsse_CMPLEF: *p++ = 0xC2; xtra = 0x102; break;
          default: goto bad;
       }
diff --git a/VEX/priv/host-amd64/isel.c b/VEX/priv/host-amd64/isel.c
index f2d28b80e1..1063049f06 100644
--- a/VEX/priv/host-amd64/isel.c
+++ b/VEX/priv/host-amd64/isel.c
@@ -2976,6 +2976,16 @@ static HReg iselVecExpr_wrk ( ISelEnv* env, IRExpr* e )
          addInstr(env, AMD64Instr_SseLdSt( True/*load*/, 16, dst, rsp0 ));
          add_to_rsp(env, 16);
          return dst;
+      } else 
+      if (e->Iex.Const.con->Ico.V128 == 0x000F) {
+         HReg tmp = newVRegI(env);
+         AMD64AMode* rsp0 = AMD64AMode_IR(0, hregAMD64_RSP());
+         addInstr(env, AMD64Instr_Imm64(0xFFFFFFFFULL, tmp));
+         addInstr(env, AMD64Instr_Push(AMD64RMI_Imm(0)));
+         addInstr(env, AMD64Instr_Push(AMD64RMI_Reg(tmp)));
+         addInstr(env, AMD64Instr_SseLdSt( True/*load*/, 16, dst, rsp0 ));
+         add_to_rsp(env, 16);
+         return dst;
       } else {
          goto vec_fail;
 #        if 0
@@ -3238,7 +3248,7 @@ static HReg iselVecExpr_wrk ( ISelEnv* env, IRExpr* e )
 //..       }
 
 //..       case Iop_CmpEQ32F0x4: op = Xsse_CMPEQF; goto do_32F0x4;
-//..       case Iop_CmpLT32F0x4: op = Xsse_CMPLTF; goto do_32F0x4;
+      case Iop_CmpLT32F0x4: op = Asse_CMPLTF; goto do_32F0x4;
 //..       case Iop_CmpLE32F0x4: op = Xsse_CMPLEF; goto do_32F0x4;
       case Iop_Add32F0x4:   op = Asse_ADDF;   goto do_32F0x4;
       case Iop_Div32F0x4:   op = Asse_DIVF;   goto do_32F0x4;