From: Greg Kroah-Hartman Date: Wed, 22 Feb 2012 22:02:36 +0000 (-0800) Subject: 3.2-stable patches X-Git-Tag: v3.2.8~15 X-Git-Url: http://git.ipfire.org/?a=commitdiff_plain;h=ab6ae555acf9170efceded0335e11b6b97f08c1b;p=thirdparty%2Fkernel%2Fstable-queue.git 3.2-stable patches added patches: arm-7321-1-cache-v7-disable-preemption-when-reading-ccsidr.patch arm-7325-1-fix-v7-boot-with-lockdep-enabled.patch --- diff --git a/queue-3.2/arm-7321-1-cache-v7-disable-preemption-when-reading-ccsidr.patch b/queue-3.2/arm-7321-1-cache-v7-disable-preemption-when-reading-ccsidr.patch new file mode 100644 index 00000000000..4da1428ddf8 --- /dev/null +++ b/queue-3.2/arm-7321-1-cache-v7-disable-preemption-when-reading-ccsidr.patch @@ -0,0 +1,58 @@ +From b46c0f74657d1fe1c1b0c1452631cc38a9e6987f Mon Sep 17 00:00:00 2001 +From: Stephen Boyd +Date: Tue, 7 Feb 2012 19:42:07 +0100 +Subject: ARM: 7321/1: cache-v7: Disable preemption when reading CCSIDR + +From: Stephen Boyd + +commit b46c0f74657d1fe1c1b0c1452631cc38a9e6987f upstream. + +armv7's flush_cache_all() flushes caches via set/way. To +determine the cache attributes (line size, number of sets, +etc.) the assembly first writes the CSSELR register to select a +cache level and then reads the CCSIDR register. The CSSELR register +is banked per-cpu and is used to determine which cache level CCSIDR +reads. If the task is migrated between when the CSSELR is written and +the CCSIDR is read the CCSIDR value may be for an unexpected cache +level (for example L1 instead of L2) and incorrect cache flushing +could occur. + +Disable interrupts across the write and read so that the correct +cache attributes are read and used for the cache flushing +routine. We disable interrupts instead of disabling preemption +because the critical section is only 3 instructions and we want +to call v7_dcache_flush_all from __v7_setup which doesn't have a +full kernel stack with a struct thread_info. + +This fixes a problem we see in scm_call() when flush_cache_all() +is called from preemptible context and sometimes the L2 cache is +not properly flushed out. + +Signed-off-by: Stephen Boyd +Acked-by: Catalin Marinas +Reviewed-by: Nicolas Pitre +Signed-off-by: Russell King +Signed-off-by: Greg Kroah-Hartman + +--- + arch/arm/mm/cache-v7.S | 6 ++++++ + 1 file changed, 6 insertions(+) + +--- a/arch/arm/mm/cache-v7.S ++++ b/arch/arm/mm/cache-v7.S +@@ -54,9 +54,15 @@ loop1: + and r1, r1, #7 @ mask of the bits for current cache only + cmp r1, #2 @ see what cache we have at this level + blt skip @ skip if no cache, or just i-cache ++#ifdef CONFIG_PREEMPT ++ save_and_disable_irqs r9 @ make cssr&csidr read atomic ++#endif + mcr p15, 2, r10, c0, c0, 0 @ select current cache level in cssr + isb @ isb to sych the new cssr&csidr + mrc p15, 1, r1, c0, c0, 0 @ read the new csidr ++#ifdef CONFIG_PREEMPT ++ restore_irqs_notrace r9 ++#endif + and r2, r1, #7 @ extract the length of the cache lines + add r2, r2, #4 @ add 4 (line length offset) + ldr r4, =0x3ff diff --git a/queue-3.2/arm-7325-1-fix-v7-boot-with-lockdep-enabled.patch b/queue-3.2/arm-7325-1-fix-v7-boot-with-lockdep-enabled.patch new file mode 100644 index 00000000000..36735e9c25b --- /dev/null +++ b/queue-3.2/arm-7325-1-fix-v7-boot-with-lockdep-enabled.patch @@ -0,0 +1,57 @@ +From 8e43a905dd574f54c5715d978318290ceafbe275 Mon Sep 17 00:00:00 2001 +From: Rabin Vincent +Date: Wed, 15 Feb 2012 16:01:42 +0100 +Subject: ARM: 7325/1: fix v7 boot with lockdep enabled + +From: Rabin Vincent + +commit 8e43a905dd574f54c5715d978318290ceafbe275 upstream. + +Bootup with lockdep enabled has been broken on v7 since b46c0f74657d +("ARM: 7321/1: cache-v7: Disable preemption when reading CCSIDR"). + +This is because v7_setup (which is called very early during boot) calls +v7_flush_dcache_all, and the save_and_disable_irqs added by that patch +ends up attempting to call into lockdep C code (trace_hardirqs_off()) +when we are in no position to execute it (no stack, MMU off). + +Fix this by using a notrace variant of save_and_disable_irqs. The code +already uses the notrace variant of restore_irqs. + +Reviewed-by: Nicolas Pitre +Acked-by: Stephen Boyd +Cc: Catalin Marinas +Signed-off-by: Rabin Vincent +Signed-off-by: Russell King +Signed-off-by: Greg Kroah-Hartman + +--- + arch/arm/include/asm/assembler.h | 5 +++++ + arch/arm/mm/cache-v7.S | 2 +- + 2 files changed, 6 insertions(+), 1 deletion(-) + +--- a/arch/arm/include/asm/assembler.h ++++ b/arch/arm/include/asm/assembler.h +@@ -137,6 +137,11 @@ + disable_irq + .endm + ++ .macro save_and_disable_irqs_notrace, oldcpsr ++ mrs \oldcpsr, cpsr ++ disable_irq_notrace ++ .endm ++ + /* + * Restore interrupt state previously stored in a register. We don't + * guarantee that this will preserve the flags. +--- a/arch/arm/mm/cache-v7.S ++++ b/arch/arm/mm/cache-v7.S +@@ -55,7 +55,7 @@ loop1: + cmp r1, #2 @ see what cache we have at this level + blt skip @ skip if no cache, or just i-cache + #ifdef CONFIG_PREEMPT +- save_and_disable_irqs r9 @ make cssr&csidr read atomic ++ save_and_disable_irqs_notrace r9 @ make cssr&csidr read atomic + #endif + mcr p15, 2, r10, c0, c0, 0 @ select current cache level in cssr + isb @ isb to sych the new cssr&csidr diff --git a/queue-3.2/series b/queue-3.2/series index 5a7109965a9..c7b1894f6ab 100644 --- a/queue-3.2/series +++ b/queue-3.2/series @@ -14,3 +14,5 @@ mmc-core-check-for-zero-length-ioctl-data.patch nfsv4-fix-an-oops-in-the-nfsv4-getacl-code.patch nfsv4-ensure-we-throw-out-bad-delegation-stateids-on-nfs4err_bad_stateid.patch nfsv4-fix-server_scope-memory-leak.patch +arm-7321-1-cache-v7-disable-preemption-when-reading-ccsidr.patch +arm-7325-1-fix-v7-boot-with-lockdep-enabled.patch