From: Eric Botcazou Date: Sun, 24 Nov 2024 19:23:34 +0000 (+0100) Subject: Fix vectorization regressions on the SPARC X-Git-Tag: basepoints/gcc-16~3921 X-Git-Url: http://git.ipfire.org/?a=commitdiff_plain;h=ab952929f7741998e3f28959c85e7abbf88ea79f;p=thirdparty%2Fgcc.git Fix vectorization regressions on the SPARC This fixes the vectorization regressions present on the SPARC by switching from vcond[u] patterns to vec_cmp[u] + vcond_mask_ patterns. While I was at it, I merged the patterns for V4HI/V2SI and V8QI enabled with VIS 3/VIS 4 to follow the model of those enabled with VIS 4B, and standardized all the mnemonics to the version documented in the Oracle SPARC architecture 2015. gcc/ PR target/117715 * config/sparc/sparc-protos.h (sparc_expand_vcond): Rename to... (sparc_expand_vcond_mask): ...this. * config/sparc/sparc.cc (TARGET_VECTORIZE_GET_MASK_MODE): Define. (sparc_vis_init_builtins): Adjust the CODE_FOR_* identifiers. (sparc_get_mask_mode): New function. (sparc_expand_vcond): Rename to... (sparc_expand_vcond_mask): ...this and adjust. * config/sparc/sparc.md (unspec): Remove UNSPEC_FCMP & UNSPEC_FUCMP and rename UNSPEC_FPUCMPSHL into UNSPEC_FPCMPUSHL. (fcmp_vis): Merge into... (fpcmp8_vis): Merge into... (fpcmp_vis): ...this. (fucmp8_vis): Merge into... (fpcmpu_vis): Merge into... (fpcmpu_vis): ...this. (vec_cmp): New expander. (vec_cmpu): Likewise. (vcond): Delete. (vcondv8qiv8qi): Likewise. (vcondu): Likewise. (vconduv8qiv8qi): Likewise. (vcond_mask_): New expander. (fpcmpshl): Adjust. (fpcmpushl): Likewise. (fpcmpdeshl): Likewise. (fpcmpurshl): Likewise. * doc/md.texi (vcond_mask_len_): Fix pasto. gcc/testsuite/ * gcc.target/sparc/20230328-1.c: Adjust to new mnemonics. * gcc.target/sparc/20230328-4.c: Likewise. * gcc.target/sparc/fcmp.c: Likewise. * gcc.target/sparc/fucmp.c: Likewise. --- diff --git a/gcc/config/sparc/sparc-protos.h b/gcc/config/sparc/sparc-protos.h index bc306083e5f1..333f48e82da1 100644 --- a/gcc/config/sparc/sparc-protos.h +++ b/gcc/config/sparc/sparc-protos.h @@ -106,7 +106,7 @@ extern void sparc_expand_compare_and_swap (rtx op[]); extern void sparc_expand_vector_init (rtx, rtx); extern void sparc_expand_vec_perm_bmask(machine_mode, rtx); extern bool sparc_expand_conditional_move (machine_mode, rtx *); -extern void sparc_expand_vcond (machine_mode, rtx *, int, int); +extern void sparc_expand_vcond_mask (machine_mode, rtx *, int); unsigned int sparc_regmode_natural_size (machine_mode); #endif /* RTX_CODE */ diff --git a/gcc/config/sparc/sparc.cc b/gcc/config/sparc/sparc.cc index 3935a97fac8b..f1944e510e50 100644 --- a/gcc/config/sparc/sparc.cc +++ b/gcc/config/sparc/sparc.cc @@ -719,6 +719,7 @@ static HOST_WIDE_INT sparc_constant_alignment (const_tree, HOST_WIDE_INT); static bool sparc_vectorize_vec_perm_const (machine_mode, machine_mode, rtx, rtx, rtx, const vec_perm_indices &); +static opt_machine_mode sparc_get_mask_mode (machine_mode); static bool sparc_can_follow_jump (const rtx_insn *, const rtx_insn *); static HARD_REG_SET sparc_zero_call_used_regs (HARD_REG_SET); static machine_mode sparc_c_mode_for_floating_type (enum tree_index); @@ -972,6 +973,9 @@ char sparc_hard_reg_printed[8]; #undef TARGET_VECTORIZE_VEC_PERM_CONST #define TARGET_VECTORIZE_VEC_PERM_CONST sparc_vectorize_vec_perm_const +#undef TARGET_VECTORIZE_GET_MASK_MODE +#define TARGET_VECTORIZE_GET_MASK_MODE sparc_get_mask_mode + #undef TARGET_CAN_FOLLOW_JUMP #define TARGET_CAN_FOLLOW_JUMP sparc_can_follow_jump @@ -11271,40 +11275,40 @@ sparc_vis_init_builtins (void) /* Pixel compare. */ if (TARGET_ARCH64) { - def_builtin_const ("__builtin_vis_fcmple16", CODE_FOR_fcmple16di_vis, + def_builtin_const ("__builtin_vis_fcmple16", CODE_FOR_fpcmple16di_vis, SPARC_BUILTIN_FCMPLE16, di_ftype_v4hi_v4hi); - def_builtin_const ("__builtin_vis_fcmple32", CODE_FOR_fcmple32di_vis, + def_builtin_const ("__builtin_vis_fcmple32", CODE_FOR_fpcmple32di_vis, SPARC_BUILTIN_FCMPLE32, di_ftype_v2si_v2si); - def_builtin_const ("__builtin_vis_fcmpne16", CODE_FOR_fcmpne16di_vis, + def_builtin_const ("__builtin_vis_fcmpne16", CODE_FOR_fpcmpne16di_vis, SPARC_BUILTIN_FCMPNE16, di_ftype_v4hi_v4hi); - def_builtin_const ("__builtin_vis_fcmpne32", CODE_FOR_fcmpne32di_vis, + def_builtin_const ("__builtin_vis_fcmpne32", CODE_FOR_fpcmpne32di_vis, SPARC_BUILTIN_FCMPNE32, di_ftype_v2si_v2si); - def_builtin_const ("__builtin_vis_fcmpgt16", CODE_FOR_fcmpgt16di_vis, + def_builtin_const ("__builtin_vis_fcmpgt16", CODE_FOR_fpcmpgt16di_vis, SPARC_BUILTIN_FCMPGT16, di_ftype_v4hi_v4hi); - def_builtin_const ("__builtin_vis_fcmpgt32", CODE_FOR_fcmpgt32di_vis, + def_builtin_const ("__builtin_vis_fcmpgt32", CODE_FOR_fpcmpgt32di_vis, SPARC_BUILTIN_FCMPGT32, di_ftype_v2si_v2si); - def_builtin_const ("__builtin_vis_fcmpeq16", CODE_FOR_fcmpeq16di_vis, + def_builtin_const ("__builtin_vis_fcmpeq16", CODE_FOR_fpcmpeq16di_vis, SPARC_BUILTIN_FCMPEQ16, di_ftype_v4hi_v4hi); - def_builtin_const ("__builtin_vis_fcmpeq32", CODE_FOR_fcmpeq32di_vis, + def_builtin_const ("__builtin_vis_fcmpeq32", CODE_FOR_fpcmpeq32di_vis, SPARC_BUILTIN_FCMPEQ32, di_ftype_v2si_v2si); } else { - def_builtin_const ("__builtin_vis_fcmple16", CODE_FOR_fcmple16si_vis, + def_builtin_const ("__builtin_vis_fcmple16", CODE_FOR_fpcmple16si_vis, SPARC_BUILTIN_FCMPLE16, si_ftype_v4hi_v4hi); - def_builtin_const ("__builtin_vis_fcmple32", CODE_FOR_fcmple32si_vis, + def_builtin_const ("__builtin_vis_fcmple32", CODE_FOR_fpcmple32si_vis, SPARC_BUILTIN_FCMPLE32, si_ftype_v2si_v2si); - def_builtin_const ("__builtin_vis_fcmpne16", CODE_FOR_fcmpne16si_vis, + def_builtin_const ("__builtin_vis_fcmpne16", CODE_FOR_fpcmpne16si_vis, SPARC_BUILTIN_FCMPNE16, si_ftype_v4hi_v4hi); - def_builtin_const ("__builtin_vis_fcmpne32", CODE_FOR_fcmpne32si_vis, + def_builtin_const ("__builtin_vis_fcmpne32", CODE_FOR_fpcmpne32si_vis, SPARC_BUILTIN_FCMPNE32, si_ftype_v2si_v2si); - def_builtin_const ("__builtin_vis_fcmpgt16", CODE_FOR_fcmpgt16si_vis, + def_builtin_const ("__builtin_vis_fcmpgt16", CODE_FOR_fpcmpgt16si_vis, SPARC_BUILTIN_FCMPGT16, si_ftype_v4hi_v4hi); - def_builtin_const ("__builtin_vis_fcmpgt32", CODE_FOR_fcmpgt32si_vis, + def_builtin_const ("__builtin_vis_fcmpgt32", CODE_FOR_fpcmpgt32si_vis, SPARC_BUILTIN_FCMPGT32, si_ftype_v2si_v2si); - def_builtin_const ("__builtin_vis_fcmpeq16", CODE_FOR_fcmpeq16si_vis, + def_builtin_const ("__builtin_vis_fcmpeq16", CODE_FOR_fpcmpeq16si_vis, SPARC_BUILTIN_FCMPEQ16, si_ftype_v4hi_v4hi); - def_builtin_const ("__builtin_vis_fcmpeq32", CODE_FOR_fcmpeq32si_vis, + def_builtin_const ("__builtin_vis_fcmpeq32", CODE_FOR_fpcmpeq32si_vis, SPARC_BUILTIN_FCMPEQ32, si_ftype_v2si_v2si); } @@ -11471,24 +11475,24 @@ sparc_vis_init_builtins (void) if (TARGET_ARCH64) { - def_builtin_const ("__builtin_vis_fucmple8", CODE_FOR_fucmple8di_vis, + def_builtin_const ("__builtin_vis_fucmple8", CODE_FOR_fpcmpule8di_vis, SPARC_BUILTIN_FUCMPLE8, di_ftype_v8qi_v8qi); - def_builtin_const ("__builtin_vis_fucmpne8", CODE_FOR_fucmpne8di_vis, + def_builtin_const ("__builtin_vis_fucmpne8", CODE_FOR_fpcmpne8di_vis, SPARC_BUILTIN_FUCMPNE8, di_ftype_v8qi_v8qi); - def_builtin_const ("__builtin_vis_fucmpgt8", CODE_FOR_fucmpgt8di_vis, + def_builtin_const ("__builtin_vis_fucmpgt8", CODE_FOR_fpcmpugt8di_vis, SPARC_BUILTIN_FUCMPGT8, di_ftype_v8qi_v8qi); - def_builtin_const ("__builtin_vis_fucmpeq8", CODE_FOR_fucmpeq8di_vis, + def_builtin_const ("__builtin_vis_fucmpeq8", CODE_FOR_fpcmpeq8di_vis, SPARC_BUILTIN_FUCMPEQ8, di_ftype_v8qi_v8qi); } else { - def_builtin_const ("__builtin_vis_fucmple8", CODE_FOR_fucmple8si_vis, + def_builtin_const ("__builtin_vis_fucmple8", CODE_FOR_fpcmpule8si_vis, SPARC_BUILTIN_FUCMPLE8, si_ftype_v8qi_v8qi); - def_builtin_const ("__builtin_vis_fucmpne8", CODE_FOR_fucmpne8si_vis, + def_builtin_const ("__builtin_vis_fucmpne8", CODE_FOR_fpcmpne8si_vis, SPARC_BUILTIN_FUCMPNE8, si_ftype_v8qi_v8qi); - def_builtin_const ("__builtin_vis_fucmpgt8", CODE_FOR_fucmpgt8si_vis, + def_builtin_const ("__builtin_vis_fucmpgt8", CODE_FOR_fpcmpugt8si_vis, SPARC_BUILTIN_FUCMPGT8, si_ftype_v8qi_v8qi); - def_builtin_const ("__builtin_vis_fucmpeq8", CODE_FOR_fucmpeq8si_vis, + def_builtin_const ("__builtin_vis_fucmpeq8", CODE_FOR_fpcmpeq8si_vis, SPARC_BUILTIN_FUCMPEQ8, si_ftype_v8qi_v8qi); } @@ -13105,6 +13109,14 @@ sparc_vectorize_vec_perm_const (machine_mode vmode, machine_mode op_mode, return true; } +/* Implement TARGET_VECTORIZE_GET_MASK_MODE. */ + +static opt_machine_mode +sparc_get_mask_mode (machine_mode) +{ + return Pmode; +} + /* Implement TARGET_FRAME_POINTER_REQUIRED. */ static bool @@ -13679,43 +13691,20 @@ sparc_expand_conditional_move (machine_mode mode, rtx *operands) } /* Emit code to conditionally move a combination of OPERANDS[1] and OPERANDS[2] - into OPERANDS[0] in MODE, depending on the outcome of the comparison of - OPERANDS[4] and OPERANDS[5]. OPERANDS[3] is the operator of the condition. - FCODE is the machine code to be used for OPERANDS[3] and CCODE the machine - code to be used for the condition mask. */ + into OPERANDS[0] in MODE, depending on the mask in OPERANDS[3]. CODE is the + machine code to be used for the cmask instruction. */ void -sparc_expand_vcond (machine_mode mode, rtx *operands, int ccode, int fcode) -{ - enum rtx_code code = signed_condition (GET_CODE (operands[3])); - rtx mask, cop0, cop1, fcmp, cmask, bshuf, gsr; - - mask = gen_reg_rtx (Pmode); - cop0 = operands[4]; - cop1 = operands[5]; - if (code == LT || code == GE) - { - code = swap_condition (code); - std::swap (cop0, cop1); - } - - gsr = gen_rtx_REG (DImode, SPARC_GSR_REG); - - fcmp = gen_rtx_UNSPEC (Pmode, - gen_rtvec (1, gen_rtx_fmt_ee (code, mode, cop0, cop1)), - fcode); - - cmask = gen_rtx_UNSPEC (DImode, - gen_rtvec (2, mask, gsr), - ccode); - - bshuf = gen_rtx_UNSPEC (mode, - gen_rtvec (3, operands[1], operands[2], gsr), - UNSPEC_BSHUFFLE); - - emit_insn (gen_rtx_SET (mask, fcmp)); +sparc_expand_vcond_mask (machine_mode mode, rtx *operands, int code) +{ + rtx gsr = gen_rtx_REG (DImode, SPARC_GSR_REG); + rtx cmask = gen_rtx_UNSPEC (DImode, + gen_rtvec (2, operands[3], gsr), + code); + rtx bshuf = gen_rtx_UNSPEC (mode, + gen_rtvec (3, operands[1], operands[2], gsr), + UNSPEC_BSHUFFLE); emit_insn (gen_rtx_SET (gsr, cmask)); - emit_insn (gen_rtx_SET (operands[0], bshuf)); } diff --git a/gcc/config/sparc/sparc.md b/gcc/config/sparc/sparc.md index 9703a2097e63..0de9a7b6394b 100644 --- a/gcc/config/sparc/sparc.md +++ b/gcc/config/sparc/sparc.md @@ -56,7 +56,6 @@ UNSPEC_MUL8UL UNSPEC_MULDUL UNSPEC_ALIGNDATA - UNSPEC_FCMP UNSPEC_PDIST UNSPEC_EDGE8 UNSPEC_EDGE8L @@ -83,7 +82,6 @@ UNSPEC_CMASK32 UNSPEC_FCHKSM16 UNSPEC_PDISTN - UNSPEC_FUCMP UNSPEC_FHADD UNSPEC_FHSUB UNSPEC_XMUL @@ -97,7 +95,7 @@ UNSPEC_DICTUNPACK UNSPEC_FPCMPSHL - UNSPEC_FPUCMPSHL + UNSPEC_FPCMPUSHL UNSPEC_FPCMPDESHL UNSPEC_FPCMPURSHL ]) @@ -8984,95 +8982,78 @@ "edge32l\t%r1, %r2, %0" [(set_attr "type" "edge")]) -(define_code_iterator gcond [le ne gt eq]) -(define_mode_iterator GCM [V4HI V2SI]) -(define_mode_attr gcm_name [(V4HI "16") (V2SI "32")]) - -(define_insn "fcmp_vis" - [(set (match_operand:P 0 "register_operand" "=r") - (unspec:P [(gcond:GCM (match_operand:GCM 1 "register_operand" "e") - (match_operand:GCM 2 "register_operand" "e"))] - UNSPEC_FCMP))] - "TARGET_VIS" - "fcmp\t%1, %2, %0" - [(set_attr "type" "viscmp")]) +(define_mode_iterator FPCMP [V8QI V4HI V2SI]) +(define_code_iterator fpcmpcond [eq ne le gt]) +(define_code_iterator fpcmpucond [leu gtu]) +(define_code_attr signed_code [(leu "le") (gtu "gt")]) -(define_insn "fpcmp8_vis" +(define_insn "fpcmp_vis" [(set (match_operand:P 0 "register_operand" "=r") - (unspec:P [(gcond:V8QI (match_operand:V8QI 1 "register_operand" "e") - (match_operand:V8QI 2 "register_operand" "e"))] - UNSPEC_FCMP))] - "TARGET_VIS4" - "fpcmp8\t%1, %2, %0" + (fpcmpcond:P (match_operand:FPCMP 1 "register_operand" "e") + (match_operand:FPCMP 2 "register_operand" "e")))] + "TARGET_VIS + && (mode != V8QImode + || (TARGET_VIS3 && ( == EQ || == NE)) + || TARGET_VIS4)" + "fpcmp\t%1, %2, %0" [(set_attr "type" "viscmp")]) -(define_expand "vcond" - [(match_operand:GCM 0 "register_operand" "") - (match_operand:GCM 1 "register_operand" "") - (match_operand:GCM 2 "register_operand" "") - (match_operator 3 "" - [(match_operand:GCM 4 "register_operand" "") - (match_operand:GCM 5 "register_operand" "")])] +(define_expand "vec_cmp" + [(set (match_operand:P 0 "register_operand" "") + (match_operator:P 1 "comparison_operator" + [(match_operand:FPCMP 2 "register_operand" "") + (match_operand:FPCMP 3 "register_operand" "")]))] "TARGET_VIS3" { - sparc_expand_vcond (mode, operands, UNSPEC_CMASK, UNSPEC_FCMP); - DONE; -}) + enum rtx_code code = GET_CODE (operands[1]); -(define_expand "vcondv8qiv8qi" - [(match_operand:V8QI 0 "register_operand" "") - (match_operand:V8QI 1 "register_operand" "") - (match_operand:V8QI 2 "register_operand" "") - (match_operator 3 "" - [(match_operand:V8QI 4 "register_operand" "") - (match_operand:V8QI 5 "register_operand" "")])] - "TARGET_VIS4" -{ - sparc_expand_vcond (V8QImode, operands, UNSPEC_CMASK8, UNSPEC_FCMP); - DONE; -}) + /* VIS 4 is required for ordering comparisons if the mode is V8QI. */ + if (mode == V8QImode && code != EQ && code != NE && !TARGET_VIS4) + FAIL; -(define_insn "fucmp8_vis" - [(set (match_operand:P 0 "register_operand" "=r") - (unspec:P [(gcond:V8QI (match_operand:V8QI 1 "register_operand" "e") - (match_operand:V8QI 2 "register_operand" "e"))] - UNSPEC_FUCMP))] - "TARGET_VIS3" - "fucmp8\t%1, %2, %0" - [(set_attr "type" "viscmp")]) + if (code == LT || code == GE) + { + PUT_CODE (operands[1], swap_condition (code)); + std::swap (operands[2], operands[3]); + } +}) -(define_insn "fpcmpu_vis" +(define_insn "fpcmpu_vis" [(set (match_operand:P 0 "register_operand" "=r") - (unspec:P [(gcond:GCM (match_operand:GCM 1 "register_operand" "e") - (match_operand:GCM 2 "register_operand" "e"))] - UNSPEC_FUCMP))] - "TARGET_VIS4" - "fpcmpu\t%1, %2, %0" + (fpcmpucond:P (match_operand:FPCMP 1 "register_operand" "e") + (match_operand:FPCMP 2 "register_operand" "e")))] + "TARGET_VIS3 && (mode == V8QImode || TARGET_VIS4)" + "fpcmpu\t%1, %2, %0" [(set_attr "type" "viscmp")]) -(define_expand "vcondu" - [(match_operand:GCM 0 "register_operand" "") - (match_operand:GCM 1 "register_operand" "") - (match_operand:GCM 2 "register_operand" "") - (match_operator 3 "" - [(match_operand:GCM 4 "register_operand" "") - (match_operand:GCM 5 "register_operand" "")])] - "TARGET_VIS4" +(define_expand "vec_cmpu" + [(set (match_operand:P 0 "register_operand" "") + (match_operator:P 1 "comparison_operator" + [(match_operand:FPCMP 2 "register_operand" "") + (match_operand:FPCMP 3 "register_operand" "")]))] + "TARGET_VIS3" { - sparc_expand_vcond (mode, operands, UNSPEC_CMASK, UNSPEC_FUCMP); - DONE; + enum rtx_code code = GET_CODE (operands[1]); + + /* VIS 4 is required for ordering comparisons if the mode is not V8QI. */ + if (mode != V8QImode && code != EQ && code != NE && !TARGET_VIS4) + FAIL; + + if (code == LTU || code == GEU) + { + PUT_CODE (operands[1], swap_condition (code)); + std::swap (operands[2], operands[3]); + } }) -(define_expand "vconduv8qiv8qi" - [(match_operand:V8QI 0 "register_operand" "") - (match_operand:V8QI 1 "register_operand" "") - (match_operand:V8QI 2 "register_operand" "") - (match_operator 3 "" - [(match_operand:V8QI 4 "register_operand" "") - (match_operand:V8QI 5 "register_operand" "")])] +(define_expand "vcond_mask_" + [(match_operand:FPCMP 0 "register_operand" "") + (match_operand:FPCMP 1 "register_operand" "") + (match_operand:FPCMP 2 "register_operand" "") + (match_operand:P 3 "register_operand" "")] "TARGET_VIS3" { - sparc_expand_vcond (V8QImode, operands, UNSPEC_CMASK8, UNSPEC_FUCMP); + sparc_expand_vcond_mask (mode, operands, UNSPEC_CMASK); DONE; }) @@ -9252,6 +9233,8 @@ (define_code_attr vis3_shift_patname [(ashift "ashl") (ss_ashift "ssashl") (lshiftrt "lshr") (ashiftrt "ashr")]) +(define_mode_iterator GCM [V4HI V2SI]) + (define_insn "v3" [(set (match_operand:GCM 0 "register_operand" "=") (vis3_shift:GCM (match_operand:GCM 1 "register_operand" "") @@ -9485,7 +9468,7 @@ ;; VIS4B instructions. -(define_mode_iterator DUMODE [V2SI V4HI V8QI]) +(define_mode_iterator DUMODE [V8QI V4HI V2SI]) (define_insn "dictunpack" [(set (match_operand:DUMODE 0 "register_operand" "=e") @@ -9497,48 +9480,44 @@ [(set_attr "type" "fga") (set_attr "subtype" "other")]) -(define_mode_iterator FPCSMODE [V2SI V4HI V8QI]) -(define_code_iterator fpcscond [le gt eq ne]) -(define_code_iterator fpcsucond [le gt]) - -(define_insn "fpcmpshl" +(define_insn "fpcmpshl" [(set (match_operand:P 0 "register_operand" "=r") - (unspec:P [(fpcscond:FPCSMODE (match_operand:FPCSMODE 1 "register_operand" "e") - (match_operand:FPCSMODE 2 "register_operand" "e")) + (unspec:P [(fpcmpcond:FPCMP (match_operand:FPCMP 1 "register_operand" "e") + (match_operand:FPCMP 2 "register_operand" "e")) (match_operand:SI 3 "imm2_operand" "q")] UNSPEC_FPCMPSHL))] "TARGET_VIS4B" - "fpcmpshl\t%1, %2, %3, %0" + "fpcmpshl\t%1, %2, %3, %0" [(set_attr "type" "viscmp")]) -(define_insn "fpcmpushl" +(define_insn "fpcmpushl" [(set (match_operand:P 0 "register_operand" "=r") - (unspec:P [(fpcsucond:FPCSMODE (match_operand:FPCSMODE 1 "register_operand" "e") - (match_operand:FPCSMODE 2 "register_operand" "e")) + (unspec:P [(fpcmpucond:FPCMP (match_operand:FPCMP 1 "register_operand" "e") + (match_operand:FPCMP 2 "register_operand" "e")) (match_operand:SI 3 "imm2_operand" "q")] - UNSPEC_FPUCMPSHL))] + UNSPEC_FPCMPUSHL))] "TARGET_VIS4B" - "fpcmpushl\t%1, %2, %3, %0" + "fpcmpushl\t%1, %2, %3, %0" [(set_attr "type" "viscmp")]) -(define_insn "fpcmpdeshl" +(define_insn "fpcmpdeshl" [(set (match_operand:P 0 "register_operand" "=r") - (unspec:P [(match_operand:FPCSMODE 1 "register_operand" "e") - (match_operand:FPCSMODE 2 "register_operand" "e") + (unspec:P [(match_operand:FPCMP 1 "register_operand" "e") + (match_operand:FPCMP 2 "register_operand" "e") (match_operand:SI 3 "imm2_operand" "q")] UNSPEC_FPCMPDESHL))] "TARGET_VIS4B" - "fpcmpdeshl\t%1, %2, %3, %0" + "fpcmpdeshl\t%1, %2, %3, %0" [(set_attr "type" "viscmp")]) -(define_insn "fpcmpurshl" +(define_insn "fpcmpurshl" [(set (match_operand:P 0 "register_operand" "=r") - (unspec:P [(match_operand:FPCSMODE 1 "register_operand" "e") - (match_operand:FPCSMODE 2 "register_operand" "e") + (unspec:P [(match_operand:FPCMP 1 "register_operand" "e") + (match_operand:FPCMP 2 "register_operand" "e") (match_operand:SI 3 "imm2_operand" "q")] UNSPEC_FPCMPURSHL))] "TARGET_VIS4B" - "fpcmpurshl\t%1, %2, %3, %0" + "fpcmpurshl\t%1, %2, %3, %0" [(set_attr "type" "viscmp")]) (include "sync.md") diff --git a/gcc/doc/md.texi b/gcc/doc/md.texi index c8f1424a0424..9b76609dee32 100644 --- a/gcc/doc/md.texi +++ b/gcc/doc/md.texi @@ -5388,7 +5388,7 @@ Similar to @code{vcond@var{m}@var{n}} but operand 3 holds a pre-computed result of vector comparison. @cindex @code{vcond_mask_len_@var{m}@var{n}} instruction pattern -@item @samp{vcond_mask_@var{m}@var{n}} +@item @samp{vcond_mask_len_@var{m}@var{n}} Set each element of operand 0 to the corresponding element of operand 2 or operand 3. Choose operand 2 if both the element index is less than operand 4 plus operand 5 and the corresponding element of operand 1 diff --git a/gcc/testsuite/gcc.target/sparc/20230328-1.c b/gcc/testsuite/gcc.target/sparc/20230328-1.c index becdc2ed3b32..49acf0b5d586 100644 --- a/gcc/testsuite/gcc.target/sparc/20230328-1.c +++ b/gcc/testsuite/gcc.target/sparc/20230328-1.c @@ -16,4 +16,4 @@ void foo (void) s.ub[i] = s.ub[i] > v; } -/* { dg-final { scan-assembler "fucmpgt8\t%" } } */ +/* { dg-final { scan-assembler "fpcmpugt8\t%" } } */ diff --git a/gcc/testsuite/gcc.target/sparc/20230328-4.c b/gcc/testsuite/gcc.target/sparc/20230328-4.c index f3e4ecef7b8f..d51eb06b9d04 100644 --- a/gcc/testsuite/gcc.target/sparc/20230328-4.c +++ b/gcc/testsuite/gcc.target/sparc/20230328-4.c @@ -16,4 +16,4 @@ void foo (void) s.ub[i] = s.ub[i] > v; } -/* { dg-final { scan-assembler "fcmpgt16\t%" } } */ +/* { dg-final { scan-assembler "fpcmpgt16\t%" } } */ diff --git a/gcc/testsuite/gcc.target/sparc/fcmp.c b/gcc/testsuite/gcc.target/sparc/fcmp.c index 959a674e1e77..b08a81ae452d 100644 --- a/gcc/testsuite/gcc.target/sparc/fcmp.c +++ b/gcc/testsuite/gcc.target/sparc/fcmp.c @@ -1,5 +1,6 @@ /* { dg-do compile } */ /* { dg-options "-mcpu=ultrasparc -mvis" } */ + typedef int vec32 __attribute__((vector_size(8))); typedef short vec16 __attribute__((vector_size(8))); @@ -43,11 +44,11 @@ long test_fcmpeq32 (vec32 a, vec32 b) return __builtin_vis_fcmpeq32 (a, b); } -/* { dg-final { scan-assembler "fcmple16\t%" } } */ -/* { dg-final { scan-assembler "fcmple32\t%" } } */ -/* { dg-final { scan-assembler "fcmpne16\t%" } } */ -/* { dg-final { scan-assembler "fcmpne32\t%" } } */ -/* { dg-final { scan-assembler "fcmpgt16\t%" } } */ -/* { dg-final { scan-assembler "fcmpgt32\t%" } } */ -/* { dg-final { scan-assembler "fcmpeq16\t%" } } */ -/* { dg-final { scan-assembler "fcmpeq32\t%" } } */ +/* { dg-final { scan-assembler "fpcmple16\t%" } } */ +/* { dg-final { scan-assembler "fpcmple32\t%" } } */ +/* { dg-final { scan-assembler "fpcmpne16\t%" } } */ +/* { dg-final { scan-assembler "fpcmpne32\t%" } } */ +/* { dg-final { scan-assembler "fpcmpgt16\t%" } } */ +/* { dg-final { scan-assembler "fpcmpgt32\t%" } } */ +/* { dg-final { scan-assembler "fpcmpeq16\t%" } } */ +/* { dg-final { scan-assembler "fpcmpeq32\t%" } } */ diff --git a/gcc/testsuite/gcc.target/sparc/fucmp.c b/gcc/testsuite/gcc.target/sparc/fucmp.c index 6e8f1b3418ef..c4542806e34e 100644 --- a/gcc/testsuite/gcc.target/sparc/fucmp.c +++ b/gcc/testsuite/gcc.target/sparc/fucmp.c @@ -1,5 +1,6 @@ /* { dg-do compile } */ /* { dg-options "-mvis3" } */ + typedef unsigned char vec8 __attribute__((vector_size(8))); long test_fucmple8 (vec8 a, vec8 b) @@ -22,7 +23,7 @@ long test_fucmpeq8 (vec8 a, vec8 b) return __builtin_vis_fucmpeq8 (a, b); } -/* { dg-final { scan-assembler "fucmple8\t%" } } */ -/* { dg-final { scan-assembler "fucmpne8\t%" } } */ -/* { dg-final { scan-assembler "fucmpgt8\t%" } } */ -/* { dg-final { scan-assembler "fucmpeq8\t%" } } */ +/* { dg-final { scan-assembler "fpcmpule8\t%" } } */ +/* { dg-final { scan-assembler "fpcmpne8\t%" } } */ +/* { dg-final { scan-assembler "fpcmpugt8\t%" } } */ +/* { dg-final { scan-assembler "fpcmpeq8\t%" } } */