From: Richard Earnshaw <rearnsha@arm.com>
Date: Sat, 9 Apr 2005 12:03:54 +0000 (+0000)
Subject: arm.c (FL_WBUF): Define.
X-Git-Tag: misc/cutover-cvs2svn~4227
X-Git-Url: http://git.ipfire.org/?a=commitdiff_plain;h=abac3b49c23d0c17ce227d4ae69d2fbd30535d5a;p=thirdparty%2Fgcc.git

arm.c (FL_WBUF): Define.

	* arm.c (FL_WBUF): Define.
	(arm_tune_strongarm): Renamed from arm_is_strong.  All uses changed.
	(arm_is_6_or_7): Delete.
	(arm_tune_wbuf): New.
	(arm_override_options): Set arm_tune_wbuf.
	* arm.h (arm_tune_strongarm): Renamed from arm_is_strong.
	(arm_is_6_or_7): Delete declaration.
	(arm_tune_wbuf): New declartion.
	* arm.md (is_strongarm): Derive from arm_tune_strongarm.
	(model_wbuf): Derive from arm_tune_wbuf.
	* arm-cores.def (arm600, arm610, arm620, arm700, arm700i, arm710)
	(arm720, arm710c, arm7100, arm7500, arm7500fe, arm710t, arm720t)
	(arm740t): Mark CPUs as having a write buffer.

From-SVN: r97894
---

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 5028522caf1a..6b36779dcf92 100644
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,19 @@
+2005-04-09  Richard Earnshaw <richard.earnshaw@arm.com>
+
+	* arm.c (FL_WBUF): Define.
+	(arm_tune_strongarm): Renamed from arm_is_strong.  All uses changed.
+	(arm_is_6_or_7): Delete.
+	(arm_tune_wbuf): New.
+	(arm_override_options): Set arm_tune_wbuf.
+	* arm.h (arm_tune_strongarm): Renamed from arm_is_strong.
+	(arm_is_6_or_7): Delete declaration.
+	(arm_tune_wbuf): New declartion.
+	* arm.md (is_strongarm): Derive from arm_tune_strongarm.
+	(model_wbuf): Derive from arm_tune_wbuf.
+	* arm-cores.def (arm600, arm610, arm620, arm700, arm700i, arm710)
+	(arm720, arm710c, arm7100, arm7500, arm7500fe, arm710t, arm720t)
+	(arm740t): Mark CPUs as having a write buffer.
+
 2005-04-09  Uros Bizjak  <uros@kss-loka.si>
 
 	* config/i386/i386.md (*fp_jcc_7_387): Use 'const0_operand' instead
diff --git a/gcc/config/arm/arm-cores.def b/gcc/config/arm/arm-cores.def
index abc52303ef0d..a18a09c56c99 100644
--- a/gcc/config/arm/arm-cores.def
+++ b/gcc/config/arm/arm-cores.def
@@ -43,22 +43,22 @@ ARM_CORE("arm3",   arm3,	2,	FL_CO_PROC | FL_MODE26, slowmul)
 /* V3 Architecture Processors */
 ARM_CORE("arm6",          arm6,		3,	FL_CO_PROC | FL_MODE26, slowmul)
 ARM_CORE("arm60",         arm60,	3,	FL_CO_PROC | FL_MODE26, slowmul)
-ARM_CORE("arm600",        arm600,	3,	FL_CO_PROC | FL_MODE26, slowmul)
-ARM_CORE("arm610",        arm610,	3,	             FL_MODE26, slowmul)
-ARM_CORE("arm620",        arm620,	3,	FL_CO_PROC | FL_MODE26, slowmul)
+ARM_CORE("arm600",        arm600,	3,	FL_CO_PROC | FL_MODE26 | FL_WBUF, slowmul)
+ARM_CORE("arm610",        arm610,	3,	             FL_MODE26 | FL_WBUF, slowmul)
+ARM_CORE("arm620",        arm620,	3,	FL_CO_PROC | FL_MODE26 | FL_WBUF, slowmul)
 ARM_CORE("arm7",          arm7,		3,	FL_CO_PROC | FL_MODE26, slowmul)
 ARM_CORE("arm7d",         arm7d,	3,	FL_CO_PROC | FL_MODE26, slowmul)
 ARM_CORE("arm7di",        arm7di,	3,	FL_CO_PROC | FL_MODE26, slowmul)
 ARM_CORE("arm70",         arm70,	3,	FL_CO_PROC | FL_MODE26, slowmul)
-ARM_CORE("arm700",        arm700,	3,	FL_CO_PROC | FL_MODE26, slowmul)
-ARM_CORE("arm700i",       arm700i,	3,	FL_CO_PROC | FL_MODE26, slowmul)
-ARM_CORE("arm710",        arm710,	3,	             FL_MODE26, slowmul)
-ARM_CORE("arm720",        arm720,	3,	             FL_MODE26, slowmul)
-ARM_CORE("arm710c",       arm710c,	3,	             FL_MODE26, slowmul)
-ARM_CORE("arm7100",       arm7100,	3,	             FL_MODE26, slowmul)
-ARM_CORE("arm7500",       arm7500,	3,	             FL_MODE26, slowmul)
+ARM_CORE("arm700",        arm700,	3,	FL_CO_PROC | FL_MODE26 | FL_WBUF, slowmul)
+ARM_CORE("arm700i",       arm700i,	3,	FL_CO_PROC | FL_MODE26 | FL_WBUF, slowmul)
+ARM_CORE("arm710",        arm710,	3,	             FL_MODE26 | FL_WBUF, slowmul)
+ARM_CORE("arm720",        arm720,	3,	             FL_MODE26 | FL_WBUF, slowmul)
+ARM_CORE("arm710c",       arm710c,	3,	             FL_MODE26 | FL_WBUF, slowmul)
+ARM_CORE("arm7100",       arm7100,	3,	             FL_MODE26 | FL_WBUF, slowmul)
+ARM_CORE("arm7500",       arm7500,	3,	             FL_MODE26 | FL_WBUF, slowmul)
 /* Doesn't have an external co-proc, but does have embedded fpa.  */
-ARM_CORE("arm7500fe",     arm7500fe,	3,	FL_CO_PROC | FL_MODE26, slowmul)
+ARM_CORE("arm7500fe",     arm7500fe,	3,	FL_CO_PROC | FL_MODE26 | FL_WBUF, slowmul)
 
 /* V3M Architecture Processors */
 /* arm7m doesn't exist on its own, but only with D, ("and", and I), but
@@ -76,11 +76,11 @@ ARM_CORE("strongarm1100", strongarm1100, 4,	             FL_MODE26 | FL_LDSCHED
 ARM_CORE("strongarm1110", strongarm1110, 4,	             FL_MODE26 | FL_LDSCHED | FL_STRONG, fastmul)
 
 /* V4T Architecture Processors */
-ARM_CORE("arm7tdmi",      arm7tdmi,	4T,	FL_CO_PROC            , fastmul)
-ARM_CORE("arm7tdmi-s",    arm7tdmis,	4T,	FL_CO_PROC            , fastmul)
-ARM_CORE("arm710t",       arm710t,	4T,	                      0 , fastmul)
-ARM_CORE("arm720t",       arm720t,	4T,	                      0 , fastmul)
-ARM_CORE("arm740t",       arm740t,	4T,	                      0 , fastmul)
+ARM_CORE("arm7tdmi",      arm7tdmi,	4T,	FL_CO_PROC          , fastmul)
+ARM_CORE("arm7tdmi-s",    arm7tdmis,	4T,	FL_CO_PROC          , fastmul)
+ARM_CORE("arm710t",       arm710t,	4T,	             FL_WBUF, fastmul)
+ARM_CORE("arm720t",       arm720t,	4T,	             FL_WBUF, fastmul)
+ARM_CORE("arm740t",       arm740t,	4T,	             FL_WBUF, fastmul)
 ARM_CORE("arm9",          arm9,		4T,	                         FL_LDSCHED, fastmul)
 ARM_CORE("arm9tdmi",      arm9tdmi,	4T,	                         FL_LDSCHED, fastmul)
 ARM_CORE("arm920",        arm920,	4T,	                         FL_LDSCHED, fastmul)
diff --git a/gcc/config/arm/arm.c b/gcc/config/arm/arm.c
index a1abe96a6e5a..13cf323d5618 100644
--- a/gcc/config/arm/arm.c
+++ b/gcc/config/arm/arm.c
@@ -386,6 +386,8 @@ static int thumb_call_reg_needed;
 #define FL_ARCH6      (1 << 12)       /* Architecture rel 6.  Adds
 					 media instructions.  */
 #define FL_VFPV2      (1 << 13)       /* Vector Floating Point V2.  */
+#define FL_WBUF	      (1 << 14)	      /* Schedule for write buffer ops.
+					 Note: ARM6 & 7 derivatives only.  */
 
 #define FL_IWMMXT     (1 << 29)	      /* XScale v2 or "Intel Wireless MMX technology".  */
 
@@ -438,7 +440,7 @@ int arm_arch6 = 0;
 int arm_ld_sched = 0;
 
 /* Nonzero if this chip is a StrongARM.  */
-int arm_is_strong = 0;
+int arm_tune_strongarm = 0;
 
 /* Nonzero if this chip is a Cirrus variant.  */
 int arm_arch_cirrus = 0;
@@ -452,8 +454,9 @@ int arm_arch_xscale = 0;
 /* Nonzero if tuning for XScale  */
 int arm_tune_xscale = 0;
 
-/* Nonzero if this chip is an ARM6 or an ARM7.  */
-int arm_is_6_or_7 = 0;
+/* Nonzero if we want to tune for stores that access the write-buffer. 
+   This typicallly means an ARM6 or ARM7 with MMU or MPU.  */
+int arm_tune_wbuf = 0;
 
 /* Nonzero if generating Thumb instructions.  */
 int thumb_code = 0;
@@ -980,10 +983,9 @@ arm_override_options (void)
   arm_arch_cirrus = (insn_flags & FL_CIRRUS) != 0;
 
   arm_ld_sched = (tune_flags & FL_LDSCHED) != 0;
-  arm_is_strong = (tune_flags & FL_STRONG) != 0;
+  arm_tune_strongarm = (tune_flags & FL_STRONG) != 0;
   thumb_code = (TARGET_ARM == 0);
-  arm_is_6_or_7 = (((tune_flags & (FL_MODE26 | FL_MODE32))
-		    && !(tune_flags & FL_ARCH4))) != 0;
+  arm_tune_wbuf = (tune_flags & FL_WBUF) != 0;
   arm_tune_xscale = (tune_flags & FL_XSCALE) != 0;
   arm_arch_iwmmxt = (insn_flags & FL_IWMMXT) != 0;
 
@@ -1182,7 +1184,7 @@ arm_override_options (void)
 
       /* StrongARM has early execution of branches, so a sequence
          that is worth skipping is shorter.  */
-      if (arm_is_strong)
+      if (arm_tune_strongarm)
         max_insns_skipped = 3;
     }
 
@@ -1396,7 +1398,7 @@ use_return_insn (int iscond, rtx sibling)
 
   /* On StrongARM, conditional returns are expensive if they aren't
      taken and multiple registers have been stacked.  */
-  if (iscond && arm_is_strong)
+  if (iscond && arm_tune_strongarm)
     {
       /* Conditional return when just the LR is stored is a simple
 	 conditional-load instruction, that's not expensive.  */
diff --git a/gcc/config/arm/arm.h b/gcc/config/arm/arm.h
index 088c003f524e..59ad92ad2544 100644
--- a/gcc/config/arm/arm.h
+++ b/gcc/config/arm/arm.h
@@ -525,7 +525,7 @@ extern int arm_ld_sched;
 extern int thumb_code;
 
 /* Nonzero if this chip is a StrongARM.  */
-extern int arm_is_strong;
+extern int arm_tune_strongarm;
 
 /* Nonzero if this chip is a Cirrus variant.  */
 extern int arm_arch_cirrus;
@@ -536,11 +536,11 @@ extern int arm_arch_iwmmxt;
 /* Nonzero if this chip is an XScale.  */
 extern int arm_arch_xscale;
 
-/* Nonzero if tuning for XScale  */
+/* Nonzero if tuning for XScale.  */
 extern int arm_tune_xscale;
 
-/* Nonzero if this chip is an ARM6 or an ARM7.  */
-extern int arm_is_6_or_7;
+/* Nonzero if tuning for stores via the write buffer.  */
+extern int arm_tune_wbuf;
 
 /* Nonzero if we should define __THUMB_INTERWORK__ in the
    preprocessor.
diff --git a/gcc/config/arm/arm.md b/gcc/config/arm/arm.md
index e94ceb81461c..6dc46aecb356 100644
--- a/gcc/config/arm/arm.md
+++ b/gcc/config/arm/arm.md
@@ -135,7 +135,7 @@
 
 ; IS_STRONGARM is set to 'yes' when compiling for StrongARM, it affects
 ; scheduling decisions for the load unit and the multiplier.
-(define_attr "is_strongarm" "no,yes" (const (symbol_ref "arm_is_strong")))
+(define_attr "is_strongarm" "no,yes" (const (symbol_ref "arm_tune_strongarm")))
 
 ; IS_XSCALE is set to 'yes' when compiling for XScale.
 (define_attr "is_xscale" "no,yes" (const (symbol_ref "arm_tune_xscale")))
@@ -267,7 +267,7 @@
 ; have one.  Later ones, such as StrongARM, have write-back caches, so don't
 ; suffer blockages enough to warrant modelling this (and it can adversely
 ; affect the schedule).
-(define_attr "model_wbuf" "no,yes" (const (symbol_ref "arm_is_6_or_7")))
+(define_attr "model_wbuf" "no,yes" (const (symbol_ref "arm_tune_wbuf")))
 
 ; WRITE_CONFLICT implies that a read following an unrelated write is likely
 ; to stall the processor.  Used with model_wbuf above.