From: Joseph Gravenor Date: Mon, 16 Sep 2019 19:13:33 +0000 (-0400) Subject: drm/amd/display: add guard for SMU ver, for 48mhz clk X-Git-Tag: v5.5-rc1~128^2~25^2~125 X-Git-Url: http://git.ipfire.org/?a=commitdiff_plain;h=ac81c2a75bcc9dce5ea80282b7d181e78b37c166;p=thirdparty%2Fkernel%2Flinux.git drm/amd/display: add guard for SMU ver, for 48mhz clk [why] dp_48m_refclk_driver_pwdn is persistent through S3 and S5. This was worked arround in SMU FW 55.21.0. Earlier FW don't have this fix so we will hang on reboot [how] add a guard for smu versions before SMU FW 55.21.0 Signed-off-by: Joseph Gravenor Signed-off-by: Alex Deucher --- diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c index a2a4c7ddc8562..68d38239304c3 100644 --- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c +++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c @@ -649,7 +649,7 @@ void rn_clk_mgr_construct( pp_smu->rn_funcs.set_wm_ranges(&pp_smu->rn_funcs.pp_smu, &ranges); } - if (!IS_FPGA_MAXIMUS_DC(ctx->dce_environment)) { + if (!IS_FPGA_MAXIMUS_DC(ctx->dce_environment) && clk_mgr->smu_ver >= 0x00371500) { /* enable powerfeatures when displaycount goes to 0 */ rn_vbios_smu_enable_48mhz_tmdp_refclk_pwrdwn(clk_mgr, !debug->disable_48mhz_pwrdwn); }