From: Greg Kroah-Hartman Date: Thu, 16 Aug 2012 23:31:21 +0000 (-0700) Subject: 3.5-stable patches X-Git-Tag: v3.5.3~22 X-Git-Url: http://git.ipfire.org/?a=commitdiff_plain;h=ad92594d6d952c93ca28dbf80016f114b744709a;p=thirdparty%2Fkernel%2Fstable-queue.git 3.5-stable patches added patches: drm-i915-correctly-order-the-ring-init-sequence.patch drm-i915-ignore-edp-bpc-settings-from-vbt.patch drm-i915-reorder-edp-disabling-to-fix-ivb-macbook-air.patch drm-radeon-do-not-reenable-crtc-after-moving-vram-start-address.patch drm-radeon-properly-handle-crtc-powergating.patch --- diff --git a/queue-3.5/drm-i915-correctly-order-the-ring-init-sequence.patch b/queue-3.5/drm-i915-correctly-order-the-ring-init-sequence.patch new file mode 100644 index 00000000000..d5c8cac565b --- /dev/null +++ b/queue-3.5/drm-i915-correctly-order-the-ring-init-sequence.patch @@ -0,0 +1,47 @@ +From 0d8957c8a90bbb5d34fab9a304459448a5131e06 Mon Sep 17 00:00:00 2001 +From: Daniel Vetter +Date: Tue, 7 Aug 2012 09:54:14 +0200 +Subject: drm/i915: correctly order the ring init sequence + +From: Daniel Vetter + +commit 0d8957c8a90bbb5d34fab9a304459448a5131e06 upstream. + +We may only start to set up the new register values after having +confirmed that the ring is truely off. Otherwise the hw might lose the +newly written register values. This is caught later on in the init +sequence, when we check whether the register writes have stuck. + +Reviewed-by: Jani Nikula +Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=50522 +Tested-by: Yang Guang +Signed-off-by: Daniel Vetter +Signed-off-by: Greg Kroah-Hartman + +--- + drivers/gpu/drm/i915/intel_ringbuffer.c | 7 +++++-- + 1 file changed, 5 insertions(+), 2 deletions(-) + +--- a/drivers/gpu/drm/i915/intel_ringbuffer.c ++++ b/drivers/gpu/drm/i915/intel_ringbuffer.c +@@ -280,8 +280,6 @@ static int init_ring_common(struct intel + I915_WRITE_HEAD(ring, 0); + ring->write_tail(ring, 0); + +- /* Initialize the ring. */ +- I915_WRITE_START(ring, obj->gtt_offset); + head = I915_READ_HEAD(ring) & HEAD_ADDR; + + /* G45 ring initialization fails to reset head to zero */ +@@ -307,6 +305,11 @@ static int init_ring_common(struct intel + } + } + ++ /* Initialize the ring. This must happen _after_ we've cleared the ring ++ * registers with the above sequence (the readback of the HEAD registers ++ * also enforces ordering), otherwise the hw might lose the new ring ++ * register values. */ ++ I915_WRITE_START(ring, obj->gtt_offset); + I915_WRITE_CTL(ring, + ((ring->size - PAGE_SIZE) & RING_NR_PAGES) + | RING_VALID); diff --git a/queue-3.5/drm-i915-ignore-edp-bpc-settings-from-vbt.patch b/queue-3.5/drm-i915-ignore-edp-bpc-settings-from-vbt.patch new file mode 100644 index 00000000000..44e53e10a70 --- /dev/null +++ b/queue-3.5/drm-i915-ignore-edp-bpc-settings-from-vbt.patch @@ -0,0 +1,63 @@ +From 4344b813f105a19f793f1fd93ad775b784648b95 Mon Sep 17 00:00:00 2001 +From: Daniel Vetter +Date: Fri, 10 Aug 2012 11:10:20 +0200 +Subject: drm/i915: ignore eDP bpc settings from vbt + +From: Daniel Vetter + +commit 4344b813f105a19f793f1fd93ad775b784648b95 upstream. + +This has originally been introduced to not oversubscribe the dp links +in + +commit 885a5fb5b120a5c7e0b3baad7b0feb5a89f76c18 +Author: Zhenyu Wang +Date: Tue Jan 12 05:38:31 2010 +0800 + + drm/i915: fix pixel color depth setting on eDP + +Since then we've fixed up the dp link bandwidth calculation code and +should now automatically fall back to 6bpc dithering. So this is +unnecessary. + +Furthermore it seems to break the new MacbookPro with retina display, +hence let's just rip this out. + +Reported-by: Benoit Gschwind +Cc: Benoit Gschwind +Cc: Francois Rigaut +Tested-by: Benoit Gschwind +Tested-by: Bernhard Froemel +Signed-off-by: Daniel Vetter +Signed-off-by: Greg Kroah-Hartman + +-- + +Testing feedback highgly welcome, and thanks for Benoit for finding +out that the bpc computations are busted. +-Daniel + +--- + drivers/gpu/drm/i915/intel_display.c | 11 ----------- + 1 file changed, 11 deletions(-) + +--- a/drivers/gpu/drm/i915/intel_display.c ++++ b/drivers/gpu/drm/i915/intel_display.c +@@ -3581,17 +3581,6 @@ static bool intel_choose_pipe_bpp_dither + continue; + } + +- if (intel_encoder->type == INTEL_OUTPUT_EDP) { +- /* Use VBT settings if we have an eDP panel */ +- unsigned int edp_bpc = dev_priv->edp.bpp / 3; +- +- if (edp_bpc < display_bpc) { +- DRM_DEBUG_KMS("clamping display bpc (was %d) to eDP (%d)\n", display_bpc, edp_bpc); +- display_bpc = edp_bpc; +- } +- continue; +- } +- + /* Not one of the known troublemakers, check the EDID */ + list_for_each_entry(connector, &dev->mode_config.connector_list, + head) { diff --git a/queue-3.5/drm-i915-reorder-edp-disabling-to-fix-ivb-macbook-air.patch b/queue-3.5/drm-i915-reorder-edp-disabling-to-fix-ivb-macbook-air.patch new file mode 100644 index 00000000000..026eb9be365 --- /dev/null +++ b/queue-3.5/drm-i915-reorder-edp-disabling-to-fix-ivb-macbook-air.patch @@ -0,0 +1,103 @@ +From 35a38556d900b9cb5dfa2529c93944b847f8a8a4 Mon Sep 17 00:00:00 2001 +From: Daniel Vetter +Date: Sun, 12 Aug 2012 22:17:14 +0200 +Subject: drm/i915: reorder edp disabling to fix ivb MacBook Air + +From: Daniel Vetter + +commit 35a38556d900b9cb5dfa2529c93944b847f8a8a4 upstream. + +eDP is tons of fun. It turns out that at least the new MacBook Air 5,1 +model absolutely doesn't like the new force vdd dance we've introduced +in + +commit 6cb49835da0426f69a2931bc2a0a8156344b0e41 +Author: Daniel Vetter +Date: Sun May 20 17:14:50 2012 +0200 + + drm/i915: enable vdd when switching off the eDP panel + +But that patch also tried to fix some neat edp sequence issue with the +force_vdd timings. Closer inspection reveals that we've raised +force_vdd only to do the aux channel communication dp_sink_dpms. If we +move the edp_panel_off below that, we don't need any force_vdd for the +disable sequence, which makes the Air happy. + +Unfortunately the reporter of the original bug that the above commit +fixed is travelling, so we can't test whether this regresses things. +But my theory is that since we don't check for any power-off -> +force_vdd-on delays in edp_panel_vdd_on, this was the actual +root-cause of this failure. With that force_vdd dance completely +eliminated, I'm hopeful the original bug stays fixed, too. + +For reference the old bug, which hopefully doesn't get broken by this: + +https://bugzilla.kernel.org/show_bug.cgi?id=43163 + +In any case, regression fixers win over plain bugfixes, so this needs +to go in asap. + +v2: The crucial pieces seems to be to clear the force_vdd flag +uncoditionally, too, in edp_panel_off. Looks like this is left behind +by the firmware somehow. + +v3: The Apple firmware seems to switch off the panel on it's own, hence +we still need to keep force_vdd on, but properly clear it when switching +the panel off. + +Bugzilla: https://bugzilla.kernel.org/show_bug.cgi?id=45671 +Tested-by: Roberto Romer +Tested-by: Daniel Wagner +Tested-by: Keith Packard +Cc: Keith Packard +Signed-off-by: Daniel Vetter +Signed-off-by: Greg Kroah-Hartman + +--- + drivers/gpu/drm/i915/intel_dp.c | 14 +++++++------- + 1 file changed, 7 insertions(+), 7 deletions(-) + +--- a/drivers/gpu/drm/i915/intel_dp.c ++++ b/drivers/gpu/drm/i915/intel_dp.c +@@ -1171,10 +1171,14 @@ static void ironlake_edp_panel_off(struc + WARN(!intel_dp->want_panel_vdd, "Need VDD to turn off panel\n"); + + pp = ironlake_get_pp_control(dev_priv); +- pp &= ~(POWER_TARGET_ON | PANEL_POWER_RESET | EDP_BLC_ENABLE); ++ /* We need to switch off panel power _and_ force vdd, for otherwise some ++ * panels get very unhappy and cease to work. */ ++ pp &= ~(POWER_TARGET_ON | EDP_FORCE_VDD | PANEL_POWER_RESET | EDP_BLC_ENABLE); + I915_WRITE(PCH_PP_CONTROL, pp); + POSTING_READ(PCH_PP_CONTROL); + ++ intel_dp->want_panel_vdd = false; ++ + ironlake_wait_panel_off(intel_dp); + } + +@@ -1284,11 +1288,9 @@ static void intel_dp_prepare(struct drm_ + * ensure that we have vdd while we switch off the panel. */ + ironlake_edp_panel_vdd_on(intel_dp); + ironlake_edp_backlight_off(intel_dp); +- ironlake_edp_panel_off(intel_dp); +- + intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON); ++ ironlake_edp_panel_off(intel_dp); + intel_dp_link_down(intel_dp); +- ironlake_edp_panel_vdd_off(intel_dp, false); + } + + static void intel_dp_commit(struct drm_encoder *encoder) +@@ -1323,11 +1325,9 @@ intel_dp_dpms(struct drm_encoder *encode + /* Switching the panel off requires vdd. */ + ironlake_edp_panel_vdd_on(intel_dp); + ironlake_edp_backlight_off(intel_dp); +- ironlake_edp_panel_off(intel_dp); +- + intel_dp_sink_dpms(intel_dp, mode); ++ ironlake_edp_panel_off(intel_dp); + intel_dp_link_down(intel_dp); +- ironlake_edp_panel_vdd_off(intel_dp, false); + + if (is_cpu_edp(intel_dp)) + ironlake_edp_pll_off(encoder); diff --git a/queue-3.5/drm-radeon-do-not-reenable-crtc-after-moving-vram-start-address.patch b/queue-3.5/drm-radeon-do-not-reenable-crtc-after-moving-vram-start-address.patch new file mode 100644 index 00000000000..732c2cd41f7 --- /dev/null +++ b/queue-3.5/drm-radeon-do-not-reenable-crtc-after-moving-vram-start-address.patch @@ -0,0 +1,171 @@ +From 81ee8fb6b52ec69eeed37fe7943446af1dccecc5 Mon Sep 17 00:00:00 2001 +From: Jerome Glisse +Date: Fri, 27 Jul 2012 16:32:24 -0400 +Subject: drm/radeon: do not reenable crtc after moving vram start address + +From: Jerome Glisse + +commit 81ee8fb6b52ec69eeed37fe7943446af1dccecc5 upstream. + +It seems we can not update the crtc scanout address. After disabling +crtc, update to base address do not take effect after crtc being +reenable leading to at least frame being scanout from the old crtc +base address. Disabling crtc display request lead to same behavior. + +So after changing the vram address if we don't keep crtc disabled +we will have the GPU trying to read some random system memory address +with some iommu this will broke the crtc engine and will lead to +broken display and iommu error message. + +So to avoid this, disable crtc. For flicker less boot we will need +to avoid moving the vram start address. + +This patch should also fix : + +https://bugs.freedesktop.org/show_bug.cgi?id=42373 + +Signed-off-by: Jerome Glisse +Signed-off-by: Greg Kroah-Hartman + +--- + drivers/gpu/drm/radeon/evergreen.c | 57 ----------------------------------- + drivers/gpu/drm/radeon/radeon_asic.h | 8 +--- + drivers/gpu/drm/radeon/rv515.c | 13 ------- + 3 files changed, 2 insertions(+), 76 deletions(-) + +--- a/drivers/gpu/drm/radeon/evergreen.c ++++ b/drivers/gpu/drm/radeon/evergreen.c +@@ -1117,24 +1117,8 @@ void evergreen_agp_enable(struct radeon_ + + void evergreen_mc_stop(struct radeon_device *rdev, struct evergreen_mc_save *save) + { +- save->vga_control[0] = RREG32(D1VGA_CONTROL); +- save->vga_control[1] = RREG32(D2VGA_CONTROL); + save->vga_render_control = RREG32(VGA_RENDER_CONTROL); + save->vga_hdp_control = RREG32(VGA_HDP_CONTROL); +- save->crtc_control[0] = RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET); +- save->crtc_control[1] = RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET); +- if (rdev->num_crtc >= 4) { +- save->vga_control[2] = RREG32(EVERGREEN_D3VGA_CONTROL); +- save->vga_control[3] = RREG32(EVERGREEN_D4VGA_CONTROL); +- save->crtc_control[2] = RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET); +- save->crtc_control[3] = RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET); +- } +- if (rdev->num_crtc >= 6) { +- save->vga_control[4] = RREG32(EVERGREEN_D5VGA_CONTROL); +- save->vga_control[5] = RREG32(EVERGREEN_D6VGA_CONTROL); +- save->crtc_control[4] = RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET); +- save->crtc_control[5] = RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET); +- } + + /* Stop all video */ + WREG32(VGA_RENDER_CONTROL, 0); +@@ -1245,47 +1229,6 @@ void evergreen_mc_resume(struct radeon_d + /* Unlock host access */ + WREG32(VGA_HDP_CONTROL, save->vga_hdp_control); + mdelay(1); +- /* Restore video state */ +- WREG32(D1VGA_CONTROL, save->vga_control[0]); +- WREG32(D2VGA_CONTROL, save->vga_control[1]); +- if (rdev->num_crtc >= 4) { +- WREG32(EVERGREEN_D3VGA_CONTROL, save->vga_control[2]); +- WREG32(EVERGREEN_D4VGA_CONTROL, save->vga_control[3]); +- } +- if (rdev->num_crtc >= 6) { +- WREG32(EVERGREEN_D5VGA_CONTROL, save->vga_control[4]); +- WREG32(EVERGREEN_D6VGA_CONTROL, save->vga_control[5]); +- } +- WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC0_REGISTER_OFFSET, 1); +- WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC1_REGISTER_OFFSET, 1); +- if (rdev->num_crtc >= 4) { +- WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC2_REGISTER_OFFSET, 1); +- WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC3_REGISTER_OFFSET, 1); +- } +- if (rdev->num_crtc >= 6) { +- WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC4_REGISTER_OFFSET, 1); +- WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC5_REGISTER_OFFSET, 1); +- } +- WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET, save->crtc_control[0]); +- WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET, save->crtc_control[1]); +- if (rdev->num_crtc >= 4) { +- WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET, save->crtc_control[2]); +- WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET, save->crtc_control[3]); +- } +- if (rdev->num_crtc >= 6) { +- WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET, save->crtc_control[4]); +- WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET, save->crtc_control[5]); +- } +- WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC0_REGISTER_OFFSET, 0); +- WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC1_REGISTER_OFFSET, 0); +- if (rdev->num_crtc >= 4) { +- WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC2_REGISTER_OFFSET, 0); +- WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC3_REGISTER_OFFSET, 0); +- } +- if (rdev->num_crtc >= 6) { +- WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC4_REGISTER_OFFSET, 0); +- WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC5_REGISTER_OFFSET, 0); +- } + WREG32(VGA_RENDER_CONTROL, save->vga_render_control); + } + +--- a/drivers/gpu/drm/radeon/radeon_asic.h ++++ b/drivers/gpu/drm/radeon/radeon_asic.h +@@ -256,13 +256,10 @@ extern int rs690_mc_wait_for_idle(struct + * rv515 + */ + struct rv515_mc_save { +- u32 d1vga_control; +- u32 d2vga_control; + u32 vga_render_control; + u32 vga_hdp_control; +- u32 d1crtc_control; +- u32 d2crtc_control; + }; ++ + int rv515_init(struct radeon_device *rdev); + void rv515_fini(struct radeon_device *rdev); + uint32_t rv515_mc_rreg(struct radeon_device *rdev, uint32_t reg); +@@ -389,11 +386,10 @@ void r700_cp_fini(struct radeon_device * + * evergreen + */ + struct evergreen_mc_save { +- u32 vga_control[6]; + u32 vga_render_control; + u32 vga_hdp_control; +- u32 crtc_control[6]; + }; ++ + void evergreen_pcie_gart_tlb_flush(struct radeon_device *rdev); + int evergreen_init(struct radeon_device *rdev); + void evergreen_fini(struct radeon_device *rdev); +--- a/drivers/gpu/drm/radeon/rv515.c ++++ b/drivers/gpu/drm/radeon/rv515.c +@@ -281,12 +281,8 @@ int rv515_debugfs_ga_info_init(struct ra + + void rv515_mc_stop(struct radeon_device *rdev, struct rv515_mc_save *save) + { +- save->d1vga_control = RREG32(R_000330_D1VGA_CONTROL); +- save->d2vga_control = RREG32(R_000338_D2VGA_CONTROL); + save->vga_render_control = RREG32(R_000300_VGA_RENDER_CONTROL); + save->vga_hdp_control = RREG32(R_000328_VGA_HDP_CONTROL); +- save->d1crtc_control = RREG32(R_006080_D1CRTC_CONTROL); +- save->d2crtc_control = RREG32(R_006880_D2CRTC_CONTROL); + + /* Stop all video */ + WREG32(R_0068E8_D2CRTC_UPDATE_LOCK, 0); +@@ -311,15 +307,6 @@ void rv515_mc_resume(struct radeon_devic + /* Unlock host access */ + WREG32(R_000328_VGA_HDP_CONTROL, save->vga_hdp_control); + mdelay(1); +- /* Restore video state */ +- WREG32(R_000330_D1VGA_CONTROL, save->d1vga_control); +- WREG32(R_000338_D2VGA_CONTROL, save->d2vga_control); +- WREG32(R_0060E8_D1CRTC_UPDATE_LOCK, 1); +- WREG32(R_0068E8_D2CRTC_UPDATE_LOCK, 1); +- WREG32(R_006080_D1CRTC_CONTROL, save->d1crtc_control); +- WREG32(R_006880_D2CRTC_CONTROL, save->d2crtc_control); +- WREG32(R_0060E8_D1CRTC_UPDATE_LOCK, 0); +- WREG32(R_0068E8_D2CRTC_UPDATE_LOCK, 0); + WREG32(R_000300_VGA_RENDER_CONTROL, save->vga_render_control); + } + diff --git a/queue-3.5/drm-radeon-properly-handle-crtc-powergating.patch b/queue-3.5/drm-radeon-properly-handle-crtc-powergating.patch new file mode 100644 index 00000000000..8fa662cdf42 --- /dev/null +++ b/queue-3.5/drm-radeon-properly-handle-crtc-powergating.patch @@ -0,0 +1,114 @@ +From 6c0ae2ab85fc4a95cae82047a7db1f688a7737ab Mon Sep 17 00:00:00 2001 +From: Alex Deucher +Date: Thu, 26 Jul 2012 13:38:52 -0400 +Subject: drm/radeon: properly handle crtc powergating + +From: Alex Deucher + +commit 6c0ae2ab85fc4a95cae82047a7db1f688a7737ab upstream. + +Need to make sure the crtc is gated on before modesetting. +Explicitly gate the crtc on in prepare() and set a flag +so that the dpms functions don't gate it off during +mode set. + +Noticed by sylware on IRC. + +Signed-off-by: Alex Deucher +Signed-off-by: Greg Kroah-Hartman + +--- + drivers/gpu/drm/radeon/atombios_crtc.c | 14 ++++++++++++-- + drivers/gpu/drm/radeon/radeon_legacy_crtc.c | 4 ++++ + drivers/gpu/drm/radeon/radeon_mode.h | 1 + + 3 files changed, 17 insertions(+), 2 deletions(-) + +--- a/drivers/gpu/drm/radeon/atombios_crtc.c ++++ b/drivers/gpu/drm/radeon/atombios_crtc.c +@@ -259,7 +259,7 @@ void atombios_crtc_dpms(struct drm_crtc + /* adjust pm to dpms changes BEFORE enabling crtcs */ + radeon_pm_compute_clocks(rdev); + /* disable crtc pair power gating before programming */ +- if (ASIC_IS_DCE6(rdev)) ++ if (ASIC_IS_DCE6(rdev) && !radeon_crtc->in_mode_set) + atombios_powergate_crtc(crtc, ATOM_DISABLE); + atombios_enable_crtc(crtc, ATOM_ENABLE); + if (ASIC_IS_DCE3(rdev) && !ASIC_IS_DCE6(rdev)) +@@ -279,7 +279,7 @@ void atombios_crtc_dpms(struct drm_crtc + atombios_enable_crtc(crtc, ATOM_DISABLE); + radeon_crtc->enabled = false; + /* power gating is per-pair */ +- if (ASIC_IS_DCE6(rdev)) { ++ if (ASIC_IS_DCE6(rdev) && !radeon_crtc->in_mode_set) { + struct drm_crtc *other_crtc; + struct radeon_crtc *other_radeon_crtc; + list_for_each_entry(other_crtc, &rdev->ddev->mode_config.crtc_list, head) { +@@ -1639,18 +1639,28 @@ static bool atombios_crtc_mode_fixup(str + static void atombios_crtc_prepare(struct drm_crtc *crtc) + { + struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); ++ struct drm_device *dev = crtc->dev; ++ struct radeon_device *rdev = dev->dev_private; + ++ radeon_crtc->in_mode_set = true; + /* pick pll */ + radeon_crtc->pll_id = radeon_atom_pick_pll(crtc); + ++ /* disable crtc pair power gating before programming */ ++ if (ASIC_IS_DCE6(rdev)) ++ atombios_powergate_crtc(crtc, ATOM_DISABLE); ++ + atombios_lock_crtc(crtc, ATOM_ENABLE); + atombios_crtc_dpms(crtc, DRM_MODE_DPMS_OFF); + } + + static void atombios_crtc_commit(struct drm_crtc *crtc) + { ++ struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); ++ + atombios_crtc_dpms(crtc, DRM_MODE_DPMS_ON); + atombios_lock_crtc(crtc, ATOM_DISABLE); ++ radeon_crtc->in_mode_set = false; + } + + static void atombios_crtc_disable(struct drm_crtc *crtc) +--- a/drivers/gpu/drm/radeon/radeon_legacy_crtc.c ++++ b/drivers/gpu/drm/radeon/radeon_legacy_crtc.c +@@ -1025,9 +1025,11 @@ static int radeon_crtc_mode_set(struct d + + static void radeon_crtc_prepare(struct drm_crtc *crtc) + { ++ struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); + struct drm_device *dev = crtc->dev; + struct drm_crtc *crtci; + ++ radeon_crtc->in_mode_set = true; + /* + * The hardware wedges sometimes if you reconfigure one CRTC + * whilst another is running (see fdo bug #24611). +@@ -1038,6 +1040,7 @@ static void radeon_crtc_prepare(struct d + + static void radeon_crtc_commit(struct drm_crtc *crtc) + { ++ struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); + struct drm_device *dev = crtc->dev; + struct drm_crtc *crtci; + +@@ -1048,6 +1051,7 @@ static void radeon_crtc_commit(struct dr + if (crtci->enabled) + radeon_crtc_dpms(crtci, DRM_MODE_DPMS_ON); + } ++ radeon_crtc->in_mode_set = false; + } + + static const struct drm_crtc_helper_funcs legacy_helper_funcs = { +--- a/drivers/gpu/drm/radeon/radeon_mode.h ++++ b/drivers/gpu/drm/radeon/radeon_mode.h +@@ -275,6 +275,7 @@ struct radeon_crtc { + u16 lut_r[256], lut_g[256], lut_b[256]; + bool enabled; + bool can_tile; ++ bool in_mode_set; + uint32_t crtc_offset; + struct drm_gem_object *cursor_bo; + uint64_t cursor_addr; diff --git a/queue-3.5/series b/queue-3.5/series index ba381c02461..e1c00b89b6a 100644 --- a/queue-3.5/series +++ b/queue-3.5/series @@ -7,3 +7,8 @@ fuse-verify-all-ioctl-retry-iov-elements.patch xen-p2m-reserve-8mb-of-_brk-space-for-p2m-leafs-when-populating-back.patch drm-i915-prefer-wide-slow-to-fast-narrow-in-dp-configs.patch drm-nvd0-disp-mask-off-high-16-bit-of-negative-cursor-x-coordinate.patch +drm-i915-correctly-order-the-ring-init-sequence.patch +drm-i915-ignore-edp-bpc-settings-from-vbt.patch +drm-i915-reorder-edp-disabling-to-fix-ivb-macbook-air.patch +drm-radeon-properly-handle-crtc-powergating.patch +drm-radeon-do-not-reenable-crtc-after-moving-vram-start-address.patch