From: Greg Kroah-Hartman Date: Mon, 20 Mar 2017 16:40:46 +0000 (+0100) Subject: 4.10-stable patches X-Git-Tag: v4.4.56~5 X-Git-Url: http://git.ipfire.org/?a=commitdiff_plain;h=ada132d31f7d1d4df4f93c2c11842538737d3217;p=thirdparty%2Fkernel%2Fstable-queue.git 4.10-stable patches added patches: arm64-kvm-vhe-clear-hcr_tge-when-invalidating-guest-tlbs.patch drm-i915-gen9-enable-hotplug-detection-early.patch drm-i915-lspcon-enable-aux-interrupts-for-resume-time-initialization.patch drm-i915-lspcon-fix-resume-time-initialization-due-to-unasserted-hpd.patch irqchip-gicv3-its-add-workaround-for-qdf2400-its-erratum-0065.patch --- diff --git a/queue-4.10/arm64-kvm-vhe-clear-hcr_tge-when-invalidating-guest-tlbs.patch b/queue-4.10/arm64-kvm-vhe-clear-hcr_tge-when-invalidating-guest-tlbs.patch new file mode 100644 index 00000000000..57a7cc25abb --- /dev/null +++ b/queue-4.10/arm64-kvm-vhe-clear-hcr_tge-when-invalidating-guest-tlbs.patch @@ -0,0 +1,138 @@ +From 68925176296a8b995e503349200e256674bfe5ac Mon Sep 17 00:00:00 2001 +From: Marc Zyngier +Date: Fri, 17 Feb 2017 14:32:18 +0000 +Subject: arm64: KVM: VHE: Clear HCR_TGE when invalidating guest TLBs + +From: Marc Zyngier + +commit 68925176296a8b995e503349200e256674bfe5ac upstream. + +When invalidating guest TLBs, special care must be taken to +actually shoot the guest TLBs and not the host ones if we're +running on a VHE system. This is controlled by the HCR_EL2.TGE +bit, which we forget to clear before invalidating TLBs. + +Address the issue by introducing two wrappers (__tlb_switch_to_guest +and __tlb_switch_to_host) that take care of both the VTTBR_EL2 +and HCR_EL2.TGE switching. + +Reported-by: Tomasz Nowicki +Tested-by: Tomasz Nowicki +Reviewed-by: Christoffer Dall +Signed-off-by: Marc Zyngier +Signed-off-by: Greg Kroah-Hartman + +--- + arch/arm64/kvm/hyp/tlb.c | 64 ++++++++++++++++++++++++++++++++++++++++------- + 1 file changed, 55 insertions(+), 9 deletions(-) + +--- a/arch/arm64/kvm/hyp/tlb.c ++++ b/arch/arm64/kvm/hyp/tlb.c +@@ -17,14 +17,62 @@ + + #include + ++static void __hyp_text __tlb_switch_to_guest_vhe(struct kvm *kvm) ++{ ++ u64 val; ++ ++ /* ++ * With VHE enabled, we have HCR_EL2.{E2H,TGE} = {1,1}, and ++ * most TLB operations target EL2/EL0. In order to affect the ++ * guest TLBs (EL1/EL0), we need to change one of these two ++ * bits. Changing E2H is impossible (goodbye TTBR1_EL2), so ++ * let's flip TGE before executing the TLB operation. ++ */ ++ write_sysreg(kvm->arch.vttbr, vttbr_el2); ++ val = read_sysreg(hcr_el2); ++ val &= ~HCR_TGE; ++ write_sysreg(val, hcr_el2); ++ isb(); ++} ++ ++static void __hyp_text __tlb_switch_to_guest_nvhe(struct kvm *kvm) ++{ ++ write_sysreg(kvm->arch.vttbr, vttbr_el2); ++ isb(); ++} ++ ++static hyp_alternate_select(__tlb_switch_to_guest, ++ __tlb_switch_to_guest_nvhe, ++ __tlb_switch_to_guest_vhe, ++ ARM64_HAS_VIRT_HOST_EXTN); ++ ++static void __hyp_text __tlb_switch_to_host_vhe(struct kvm *kvm) ++{ ++ /* ++ * We're done with the TLB operation, let's restore the host's ++ * view of HCR_EL2. ++ */ ++ write_sysreg(0, vttbr_el2); ++ write_sysreg(HCR_HOST_VHE_FLAGS, hcr_el2); ++} ++ ++static void __hyp_text __tlb_switch_to_host_nvhe(struct kvm *kvm) ++{ ++ write_sysreg(0, vttbr_el2); ++} ++ ++static hyp_alternate_select(__tlb_switch_to_host, ++ __tlb_switch_to_host_nvhe, ++ __tlb_switch_to_host_vhe, ++ ARM64_HAS_VIRT_HOST_EXTN); ++ + void __hyp_text __kvm_tlb_flush_vmid_ipa(struct kvm *kvm, phys_addr_t ipa) + { + dsb(ishst); + + /* Switch to requested VMID */ + kvm = kern_hyp_va(kvm); +- write_sysreg(kvm->arch.vttbr, vttbr_el2); +- isb(); ++ __tlb_switch_to_guest()(kvm); + + /* + * We could do so much better if we had the VA as well. +@@ -45,7 +93,7 @@ void __hyp_text __kvm_tlb_flush_vmid_ipa + dsb(ish); + isb(); + +- write_sysreg(0, vttbr_el2); ++ __tlb_switch_to_host()(kvm); + } + + void __hyp_text __kvm_tlb_flush_vmid(struct kvm *kvm) +@@ -54,14 +102,13 @@ void __hyp_text __kvm_tlb_flush_vmid(str + + /* Switch to requested VMID */ + kvm = kern_hyp_va(kvm); +- write_sysreg(kvm->arch.vttbr, vttbr_el2); +- isb(); ++ __tlb_switch_to_guest()(kvm); + + asm volatile("tlbi vmalls12e1is" : : ); + dsb(ish); + isb(); + +- write_sysreg(0, vttbr_el2); ++ __tlb_switch_to_host()(kvm); + } + + void __hyp_text __kvm_tlb_flush_local_vmid(struct kvm_vcpu *vcpu) +@@ -69,14 +116,13 @@ void __hyp_text __kvm_tlb_flush_local_vm + struct kvm *kvm = kern_hyp_va(kern_hyp_va(vcpu)->kvm); + + /* Switch to requested VMID */ +- write_sysreg(kvm->arch.vttbr, vttbr_el2); +- isb(); ++ __tlb_switch_to_guest()(kvm); + + asm volatile("tlbi vmalle1" : : ); + dsb(nsh); + isb(); + +- write_sysreg(0, vttbr_el2); ++ __tlb_switch_to_host()(kvm); + } + + void __hyp_text __kvm_flush_vm_context(void) diff --git a/queue-4.10/drm-i915-gen9-enable-hotplug-detection-early.patch b/queue-4.10/drm-i915-gen9-enable-hotplug-detection-early.patch new file mode 100644 index 00000000000..fc4bb5fdf04 --- /dev/null +++ b/queue-4.10/drm-i915-gen9-enable-hotplug-detection-early.patch @@ -0,0 +1,162 @@ +From 2a57d9cce1c08578097d965468e37f06d71fa495 Mon Sep 17 00:00:00 2001 +From: Imre Deak +Date: Fri, 27 Jan 2017 11:39:18 +0200 +Subject: drm/i915/gen9+: Enable hotplug detection early +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +From: Imre Deak + +commit 2a57d9cce1c08578097d965468e37f06d71fa495 upstream. + +For LSPCON resume time initialization we need to sample the +corresponding pin's HPD level, but this is only available when HPD +detection is enabled. Currently we enable detection only when enabling +HPD interrupts which is too late, so bring the enabling of detection +earlier. + +This is needed by the next patch. + +Cc: Shashank Sharma +Cc: Jani Nikula +Cc: Ville Syrjälä +Cc: Daniel Vetter +Reviewed-by: Shashank Sharma +Link: http://patchwork.freedesktop.org/patch/msgid/1485509961-9010-2-git-send-email-imre.deak@intel.com +Signed-off-by: Jani Nikula +(rebased onto v4.10.4 due to missing s/IS_BROXTON/IS_GEN9_LP/ upstream change) +(corrected stable tag) +Signed-off-by: Imre Deak +Signed-off-by: Greg Kroah-Hartman +--- + drivers/gpu/drm/i915/i915_irq.c | 69 ++++++++++++++++++++++++++++------------ + 1 file changed, 50 insertions(+), 19 deletions(-) + +--- a/drivers/gpu/drm/i915/i915_irq.c ++++ b/drivers/gpu/drm/i915/i915_irq.c +@@ -3089,19 +3089,16 @@ static void ibx_hpd_irq_setup(struct drm + I915_WRITE(PCH_PORT_HOTPLUG, hotplug); + } + +-static void spt_hpd_irq_setup(struct drm_i915_private *dev_priv) ++static void spt_hpd_detection_setup(struct drm_i915_private *dev_priv) + { +- u32 hotplug_irqs, hotplug, enabled_irqs; +- +- hotplug_irqs = SDE_HOTPLUG_MASK_SPT; +- enabled_irqs = intel_hpd_enabled_irqs(dev_priv, hpd_spt); +- +- ibx_display_interrupt_update(dev_priv, hotplug_irqs, enabled_irqs); ++ u32 hotplug; + + /* Enable digital hotplug on the PCH */ + hotplug = I915_READ(PCH_PORT_HOTPLUG); +- hotplug |= PORTD_HOTPLUG_ENABLE | PORTC_HOTPLUG_ENABLE | +- PORTB_HOTPLUG_ENABLE | PORTA_HOTPLUG_ENABLE; ++ hotplug |= PORTA_HOTPLUG_ENABLE | ++ PORTB_HOTPLUG_ENABLE | ++ PORTC_HOTPLUG_ENABLE | ++ PORTD_HOTPLUG_ENABLE; + I915_WRITE(PCH_PORT_HOTPLUG, hotplug); + + hotplug = I915_READ(PCH_PORT_HOTPLUG2); +@@ -3109,6 +3106,18 @@ static void spt_hpd_irq_setup(struct drm + I915_WRITE(PCH_PORT_HOTPLUG2, hotplug); + } + ++static void spt_hpd_irq_setup(struct drm_i915_private *dev_priv) ++{ ++ u32 hotplug_irqs, enabled_irqs; ++ ++ hotplug_irqs = SDE_HOTPLUG_MASK_SPT; ++ enabled_irqs = intel_hpd_enabled_irqs(dev_priv, hpd_spt); ++ ++ ibx_display_interrupt_update(dev_priv, hotplug_irqs, enabled_irqs); ++ ++ spt_hpd_detection_setup(dev_priv); ++} ++ + static void ilk_hpd_irq_setup(struct drm_i915_private *dev_priv) + { + u32 hotplug_irqs, hotplug, enabled_irqs; +@@ -3143,18 +3152,15 @@ static void ilk_hpd_irq_setup(struct drm + ibx_hpd_irq_setup(dev_priv); + } + +-static void bxt_hpd_irq_setup(struct drm_i915_private *dev_priv) ++static void __bxt_hpd_detection_setup(struct drm_i915_private *dev_priv, ++ u32 enabled_irqs) + { +- u32 hotplug_irqs, hotplug, enabled_irqs; +- +- enabled_irqs = intel_hpd_enabled_irqs(dev_priv, hpd_bxt); +- hotplug_irqs = BXT_DE_PORT_HOTPLUG_MASK; +- +- bdw_update_port_irq(dev_priv, hotplug_irqs, enabled_irqs); ++ u32 hotplug; + + hotplug = I915_READ(PCH_PORT_HOTPLUG); +- hotplug |= PORTC_HOTPLUG_ENABLE | PORTB_HOTPLUG_ENABLE | +- PORTA_HOTPLUG_ENABLE; ++ hotplug |= PORTA_HOTPLUG_ENABLE | ++ PORTB_HOTPLUG_ENABLE | ++ PORTC_HOTPLUG_ENABLE; + + DRM_DEBUG_KMS("Invert bit setting: hp_ctl:%x hp_port:%x\n", + hotplug, enabled_irqs); +@@ -3164,7 +3170,6 @@ static void bxt_hpd_irq_setup(struct drm + * For BXT invert bit has to be set based on AOB design + * for HPD detection logic, update it based on VBT fields. + */ +- + if ((enabled_irqs & BXT_DE_PORT_HP_DDIA) && + intel_bios_is_port_hpd_inverted(dev_priv, PORT_A)) + hotplug |= BXT_DDIA_HPD_INVERT; +@@ -3178,6 +3183,23 @@ static void bxt_hpd_irq_setup(struct drm + I915_WRITE(PCH_PORT_HOTPLUG, hotplug); + } + ++static void bxt_hpd_detection_setup(struct drm_i915_private *dev_priv) ++{ ++ __bxt_hpd_detection_setup(dev_priv, BXT_DE_PORT_HOTPLUG_MASK); ++} ++ ++static void bxt_hpd_irq_setup(struct drm_i915_private *dev_priv) ++{ ++ u32 hotplug_irqs, enabled_irqs; ++ ++ enabled_irqs = intel_hpd_enabled_irqs(dev_priv, hpd_bxt); ++ hotplug_irqs = BXT_DE_PORT_HOTPLUG_MASK; ++ ++ bdw_update_port_irq(dev_priv, hotplug_irqs, enabled_irqs); ++ ++ __bxt_hpd_detection_setup(dev_priv, enabled_irqs); ++} ++ + static void ibx_irq_postinstall(struct drm_device *dev) + { + struct drm_i915_private *dev_priv = to_i915(dev); +@@ -3193,6 +3215,12 @@ static void ibx_irq_postinstall(struct d + + gen5_assert_iir_is_zero(dev_priv, SDEIIR); + I915_WRITE(SDEIMR, ~mask); ++ ++ if (HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv) || ++ HAS_PCH_LPT(dev_priv)) ++ ; /* TODO: Enable HPD detection on older PCH platforms too */ ++ else ++ spt_hpd_detection_setup(dev_priv); + } + + static void gen5_gt_irq_postinstall(struct drm_device *dev) +@@ -3404,6 +3432,9 @@ static void gen8_de_irq_postinstall(stru + + GEN5_IRQ_INIT(GEN8_DE_PORT_, ~de_port_masked, de_port_enables); + GEN5_IRQ_INIT(GEN8_DE_MISC_, ~de_misc_masked, de_misc_masked); ++ ++ if (IS_BROXTON(dev_priv)) ++ bxt_hpd_detection_setup(dev_priv); + } + + static int gen8_irq_postinstall(struct drm_device *dev) diff --git a/queue-4.10/drm-i915-lspcon-enable-aux-interrupts-for-resume-time-initialization.patch b/queue-4.10/drm-i915-lspcon-enable-aux-interrupts-for-resume-time-initialization.patch new file mode 100644 index 00000000000..b69a0b2b964 --- /dev/null +++ b/queue-4.10/drm-i915-lspcon-enable-aux-interrupts-for-resume-time-initialization.patch @@ -0,0 +1,64 @@ +From 908764f6d0bd1ba496cb8da33b9b98297ed27351 Mon Sep 17 00:00:00 2001 +From: Imre Deak +Date: Tue, 29 Nov 2016 21:40:29 +0200 +Subject: drm/i915/lspcon: Enable AUX interrupts for resume time initialization +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +From: Imre Deak + +commit 908764f6d0bd1ba496cb8da33b9b98297ed27351 upstream. + +For LSPCON initialization during system resume we need AUX +functionality, but we call the corresponding encoder reset hook with all +interrupts disabled. Without interrupts we'll do a poll-wait for AUX +transfer completions, which adds a significant delay if the transfers +timeout/need to be retried for some reason. + +Fix this by enabling interrupts before calling the reset hooks. Note +that while this will enable AUX interrupts it will keep HPD interrupts +disabled, in a similar way to the init time output setup code. + +This issue existed since LSPCON support was added. + +v2: +- Rebased on drm-tip. + +Cc: Shashank Sharma +Reviewed-by: Ville Syrjälä +Tested-by: David Weinehall +Link: http://patchwork.freedesktop.org/patch/msgid/1480448429-27739-1-git-send-email-imre.deak@intel.com +(rebased onto v4.10.4 due to missing s/dev/dev_priv/ upstream change) +(corrected stable tag) +Signed-off-by: Imre Deak +Signed-off-by: Greg Kroah-Hartman +--- + drivers/gpu/drm/i915/i915_drv.c | 5 ++++- + 1 file changed, 4 insertions(+), 1 deletion(-) + +--- a/drivers/gpu/drm/i915/i915_drv.c ++++ b/drivers/gpu/drm/i915/i915_drv.c +@@ -1573,18 +1573,21 @@ static int i915_drm_resume(struct drm_de + intel_opregion_setup(dev_priv); + + intel_init_pch_refclk(dev); +- drm_mode_config_reset(dev); + + /* + * Interrupts have to be enabled before any batches are run. If not the + * GPU will hang. i915_gem_init_hw() will initiate batches to + * update/restore the context. + * ++ * drm_mode_config_reset() needs AUX interrupts. ++ * + * Modeset enabling in intel_modeset_init_hw() also needs working + * interrupts. + */ + intel_runtime_pm_enable_interrupts(dev_priv); + ++ drm_mode_config_reset(dev); ++ + mutex_lock(&dev->struct_mutex); + if (i915_gem_init_hw(dev)) { + DRM_ERROR("failed to re-initialize GPU, declaring wedged!\n"); diff --git a/queue-4.10/drm-i915-lspcon-fix-resume-time-initialization-due-to-unasserted-hpd.patch b/queue-4.10/drm-i915-lspcon-fix-resume-time-initialization-due-to-unasserted-hpd.patch new file mode 100644 index 00000000000..4f71b4b25df --- /dev/null +++ b/queue-4.10/drm-i915-lspcon-fix-resume-time-initialization-due-to-unasserted-hpd.patch @@ -0,0 +1,80 @@ +From 4b84b4a5507913ee0da27b1f1b27671937839de6 Mon Sep 17 00:00:00 2001 +From: Imre Deak +Date: Fri, 27 Jan 2017 11:39:19 +0200 +Subject: drm/i915/lspcon: Fix resume time initialization due to unasserted HPD +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +From: Imre Deak + +commit 4b84b4a5507913ee0da27b1f1b27671937839de6 upstream. + +During system resume time initialization the HPD level on LSPCON ports +can stay low for an extended amount of time, leading to failed AUX +transfers and LSPCON initialization. Fix this by waiting for HPD to get +asserted. + +Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=99178 +Cc: Shashank Sharma +Cc: Jani Nikula +Cc: Ville Syrjälä +Cc: Daniel Vetter +Reviewed-by: Shashank Sharma +Link: http://patchwork.freedesktop.org/patch/msgid/1485509961-9010-3-git-send-email-imre.deak@intel.com +Signed-off-by: Jani Nikula +(corrected stable tag) +Signed-off-by: Imre Deak +Signed-off-by: Greg Kroah-Hartman + +--- + drivers/gpu/drm/i915/intel_dp.c | 4 ++-- + drivers/gpu/drm/i915/intel_drv.h | 2 ++ + drivers/gpu/drm/i915/intel_lspcon.c | 5 ++++- + 3 files changed, 8 insertions(+), 3 deletions(-) + +--- a/drivers/gpu/drm/i915/intel_dp.c ++++ b/drivers/gpu/drm/i915/intel_dp.c +@@ -4289,8 +4289,8 @@ static bool bxt_digital_port_connected(s + * + * Return %true if @port is connected, %false otherwise. + */ +-static bool intel_digital_port_connected(struct drm_i915_private *dev_priv, +- struct intel_digital_port *port) ++bool intel_digital_port_connected(struct drm_i915_private *dev_priv, ++ struct intel_digital_port *port) + { + if (HAS_PCH_IBX(dev_priv)) + return ibx_digital_port_connected(dev_priv, port); +--- a/drivers/gpu/drm/i915/intel_drv.h ++++ b/drivers/gpu/drm/i915/intel_drv.h +@@ -1451,6 +1451,8 @@ bool intel_dp_read_dpcd(struct intel_dp + bool __intel_dp_read_desc(struct intel_dp *intel_dp, + struct intel_dp_desc *desc); + bool intel_dp_read_desc(struct intel_dp *intel_dp); ++bool intel_digital_port_connected(struct drm_i915_private *dev_priv, ++ struct intel_digital_port *port); + + /* intel_dp_aux_backlight.c */ + int intel_dp_aux_init_backlight_funcs(struct intel_connector *intel_connector); +--- a/drivers/gpu/drm/i915/intel_lspcon.c ++++ b/drivers/gpu/drm/i915/intel_lspcon.c +@@ -100,6 +100,8 @@ static bool lspcon_probe(struct intel_ls + static void lspcon_resume_in_pcon_wa(struct intel_lspcon *lspcon) + { + struct intel_dp *intel_dp = lspcon_to_intel_dp(lspcon); ++ struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); ++ struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev); + unsigned long start = jiffies; + + if (!lspcon->desc_valid) +@@ -115,7 +117,8 @@ static void lspcon_resume_in_pcon_wa(str + if (!__intel_dp_read_desc(intel_dp, &desc)) + return; + +- if (!memcmp(&intel_dp->desc, &desc, sizeof(desc))) { ++ if (intel_digital_port_connected(dev_priv, dig_port) && ++ !memcmp(&intel_dp->desc, &desc, sizeof(desc))) { + DRM_DEBUG_KMS("LSPCON recovering in PCON mode after %u ms\n", + jiffies_to_msecs(jiffies - start)); + return; diff --git a/queue-4.10/irqchip-gicv3-its-add-workaround-for-qdf2400-its-erratum-0065.patch b/queue-4.10/irqchip-gicv3-its-add-workaround-for-qdf2400-its-erratum-0065.patch new file mode 100644 index 00000000000..6c49d106e14 --- /dev/null +++ b/queue-4.10/irqchip-gicv3-its-add-workaround-for-qdf2400-its-erratum-0065.patch @@ -0,0 +1,132 @@ +From 90922a2d03d84de36bf8a9979d62580102f31a92 Mon Sep 17 00:00:00 2001 +From: Shanker Donthineni +Date: Tue, 7 Mar 2017 08:20:38 -0600 +Subject: irqchip/gicv3-its: Add workaround for QDF2400 ITS erratum 0065 + +From: Shanker Donthineni + +commit 90922a2d03d84de36bf8a9979d62580102f31a92 upstream. + +On Qualcomm Datacenter Technologies QDF2400 SoCs, the ITS hardware +implementation uses 16Bytes for Interrupt Translation Entry (ITE), +but reports an incorrect value of 8Bytes in GITS_TYPER.ITTE_size. + +It might cause kernel memory corruption depending on the number +of MSI(x) that are configured and the amount of memory that has +been allocated for ITEs in its_create_device(). + +This patch fixes the potential memory corruption by setting the +correct ITE size to 16Bytes. + +Cc: stable@vger.kernel.org +Signed-off-by: Shanker Donthineni +Signed-off-by: Marc Zyngier +Signed-off-by: Greg Kroah-Hartman + +--- + Documentation/arm64/silicon-errata.txt | 44 +++++++++++++++++---------------- + arch/arm64/Kconfig | 10 +++++++ + drivers/irqchip/irq-gic-v3-its.c | 16 ++++++++++++ + 3 files changed, 49 insertions(+), 21 deletions(-) + +--- a/Documentation/arm64/silicon-errata.txt ++++ b/Documentation/arm64/silicon-errata.txt +@@ -42,24 +42,26 @@ file acts as a registry of software work + will be updated when new workarounds are committed and backported to + stable kernels. + +-| Implementor | Component | Erratum ID | Kconfig | +-+----------------+-----------------+-----------------+-------------------------+ +-| ARM | Cortex-A53 | #826319 | ARM64_ERRATUM_826319 | +-| ARM | Cortex-A53 | #827319 | ARM64_ERRATUM_827319 | +-| ARM | Cortex-A53 | #824069 | ARM64_ERRATUM_824069 | +-| ARM | Cortex-A53 | #819472 | ARM64_ERRATUM_819472 | +-| ARM | Cortex-A53 | #845719 | ARM64_ERRATUM_845719 | +-| ARM | Cortex-A53 | #843419 | ARM64_ERRATUM_843419 | +-| ARM | Cortex-A57 | #832075 | ARM64_ERRATUM_832075 | +-| ARM | Cortex-A57 | #852523 | N/A | +-| ARM | Cortex-A57 | #834220 | ARM64_ERRATUM_834220 | +-| ARM | Cortex-A72 | #853709 | N/A | +-| ARM | MMU-500 | #841119,#826419 | N/A | +-| | | | | +-| Cavium | ThunderX ITS | #22375, #24313 | CAVIUM_ERRATUM_22375 | +-| Cavium | ThunderX ITS | #23144 | CAVIUM_ERRATUM_23144 | +-| Cavium | ThunderX GICv3 | #23154 | CAVIUM_ERRATUM_23154 | +-| Cavium | ThunderX Core | #27456 | CAVIUM_ERRATUM_27456 | +-| Cavium | ThunderX SMMUv2 | #27704 | N/A | +-| | | | | +-| Freescale/NXP | LS2080A/LS1043A | A-008585 | FSL_ERRATUM_A008585 | ++| Implementor | Component | Erratum ID | Kconfig | +++----------------+-----------------+-----------------+-----------------------------+ ++| ARM | Cortex-A53 | #826319 | ARM64_ERRATUM_826319 | ++| ARM | Cortex-A53 | #827319 | ARM64_ERRATUM_827319 | ++| ARM | Cortex-A53 | #824069 | ARM64_ERRATUM_824069 | ++| ARM | Cortex-A53 | #819472 | ARM64_ERRATUM_819472 | ++| ARM | Cortex-A53 | #845719 | ARM64_ERRATUM_845719 | ++| ARM | Cortex-A53 | #843419 | ARM64_ERRATUM_843419 | ++| ARM | Cortex-A57 | #832075 | ARM64_ERRATUM_832075 | ++| ARM | Cortex-A57 | #852523 | N/A | ++| ARM | Cortex-A57 | #834220 | ARM64_ERRATUM_834220 | ++| ARM | Cortex-A72 | #853709 | N/A | ++| ARM | MMU-500 | #841119,#826419 | N/A | ++| | | | | ++| Cavium | ThunderX ITS | #22375, #24313 | CAVIUM_ERRATUM_22375 | ++| Cavium | ThunderX ITS | #23144 | CAVIUM_ERRATUM_23144 | ++| Cavium | ThunderX GICv3 | #23154 | CAVIUM_ERRATUM_23154 | ++| Cavium | ThunderX Core | #27456 | CAVIUM_ERRATUM_27456 | ++| Cavium | ThunderX SMMUv2 | #27704 | N/A | ++| | | | | ++| Freescale/NXP | LS2080A/LS1043A | A-008585 | FSL_ERRATUM_A008585 | ++| | | | | ++| Qualcomm Tech. | QDF2400 ITS | E0065 | QCOM_QDF2400_ERRATUM_0065 | +--- a/arch/arm64/Kconfig ++++ b/arch/arm64/Kconfig +@@ -479,6 +479,16 @@ config CAVIUM_ERRATUM_27456 + + If unsure, say Y. + ++config QCOM_QDF2400_ERRATUM_0065 ++ bool "QDF2400 E0065: Incorrect GITS_TYPER.ITT_Entry_size" ++ default y ++ help ++ On Qualcomm Datacenter Technologies QDF2400 SoC, ITS hardware reports ++ ITE size incorrectly. The GITS_TYPER.ITT_Entry_size field should have ++ been indicated as 16Bytes (0xf), not 8Bytes (0x7). ++ ++ If unsure, say Y. ++ + endmenu + + +--- a/drivers/irqchip/irq-gic-v3-its.c ++++ b/drivers/irqchip/irq-gic-v3-its.c +@@ -1597,6 +1597,14 @@ static void __maybe_unused its_enable_qu + its->flags |= ITS_FLAGS_WORKAROUND_CAVIUM_23144; + } + ++static void __maybe_unused its_enable_quirk_qdf2400_e0065(void *data) ++{ ++ struct its_node *its = data; ++ ++ /* On QDF2400, the size of the ITE is 16Bytes */ ++ its->ite_size = 16; ++} ++ + static const struct gic_quirk its_quirks[] = { + #ifdef CONFIG_CAVIUM_ERRATUM_22375 + { +@@ -1614,6 +1622,14 @@ static const struct gic_quirk its_quirks + .init = its_enable_quirk_cavium_23144, + }, + #endif ++#ifdef CONFIG_QCOM_QDF2400_ERRATUM_0065 ++ { ++ .desc = "ITS: QDF2400 erratum 0065", ++ .iidr = 0x00001070, /* QDF2400 ITS rev 1.x */ ++ .mask = 0xffffffff, ++ .init = its_enable_quirk_qdf2400_e0065, ++ }, ++#endif + { + } + }; diff --git a/queue-4.10/series b/queue-4.10/series index 31ece9e0e7f..c3a9ada4821 100644 --- a/queue-4.10/series +++ b/queue-4.10/series @@ -46,3 +46,8 @@ net-use-net-count-to-check-whether-a-netns-is-alive-or-not.patch dccp-tcp-fix-routing-redirect-race.patch tun-fix-premature-pollout-notification-on-tun-devices.patch dccp-fix-memory-leak-during-tear-down-of-unsuccessful-connection-request.patch +arm64-kvm-vhe-clear-hcr_tge-when-invalidating-guest-tlbs.patch +irqchip-gicv3-its-add-workaround-for-qdf2400-its-erratum-0065.patch +drm-i915-lspcon-enable-aux-interrupts-for-resume-time-initialization.patch +drm-i915-gen9-enable-hotplug-detection-early.patch +drm-i915-lspcon-fix-resume-time-initialization-due-to-unasserted-hpd.patch