From: Nathan Froyd <froydnj@codesourcery.com>
Date: Tue, 23 Feb 2010 20:21:31 +0000 (-0800)
Subject: target-ppc: fix SPE evsplat* instructions
X-Git-Tag: v0.13.0-rc0~1253
X-Git-Url: http://git.ipfire.org/?a=commitdiff_plain;h=ae01847f9cbbf9b80252cd36ec645ee821809037;p=thirdparty%2Fqemu.git

target-ppc: fix SPE evsplat* instructions

The shifts in the gen_evsplat* functions were expecting rA to be masked,
not extracted, and so used the wrong shift amounts to sign-extend or pad
with zeroes.

Signed-off-by: Nathan Froyd <froydnj@codesourcery.com>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
---

diff --git a/target-ppc/translate.c b/target-ppc/translate.c
index d4e81ce89ba..0b11fda880d 100644
--- a/target-ppc/translate.c
+++ b/target-ppc/translate.c
@@ -7001,7 +7001,7 @@ static inline void gen_evmergelohi(DisasContext *ctx)
 }
 static inline void gen_evsplati(DisasContext *ctx)
 {
-    uint64_t imm = ((int32_t)(rA(ctx->opcode) << 11)) >> 27;
+    uint64_t imm = ((int32_t)(rA(ctx->opcode) << 27)) >> 27;
 
 #if defined(TARGET_PPC64)
     tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], (imm << 32) | imm);
@@ -7012,7 +7012,7 @@ static inline void gen_evsplati(DisasContext *ctx)
 }
 static inline void gen_evsplatfi(DisasContext *ctx)
 {
-    uint64_t imm = rA(ctx->opcode) << 11;
+    uint64_t imm = rA(ctx->opcode) << 27;
 
 #if defined(TARGET_PPC64)
     tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], (imm << 32) | imm);