From: Greg Kroah-Hartman Date: Sun, 28 May 2023 14:44:04 +0000 (+0100) Subject: 5.15-stable patches X-Git-Tag: review~39 X-Git-Url: http://git.ipfire.org/?a=commitdiff_plain;h=ae7acc1769308447a075794a7b98dbdf6ac6896f;p=thirdparty%2Fkernel%2Fstable-queue.git 5.15-stable patches added patches: perf-x86-uncore-correct-the-number-of-chas-on-spr.patch x86-topology-fix-erroneous-smp_num_siblings-on-intel-hybrid-platforms.patch --- diff --git a/queue-5.15/perf-x86-uncore-correct-the-number-of-chas-on-spr.patch b/queue-5.15/perf-x86-uncore-correct-the-number-of-chas-on-spr.patch new file mode 100644 index 00000000000..80d1408c843 --- /dev/null +++ b/queue-5.15/perf-x86-uncore-correct-the-number-of-chas-on-spr.patch @@ -0,0 +1,58 @@ +From 38776cc45eb7603df4735a0410f42cffff8e71a1 Mon Sep 17 00:00:00 2001 +From: Kan Liang +Date: Mon, 8 May 2023 07:02:06 -0700 +Subject: perf/x86/uncore: Correct the number of CHAs on SPR + +From: Kan Liang + +commit 38776cc45eb7603df4735a0410f42cffff8e71a1 upstream. + +The number of CHAs from the discovery table on some SPR variants is +incorrect, because of a firmware issue. An accurate number can be read +from the MSR UNC_CBO_CONFIG. + +Fixes: 949b11381f81 ("perf/x86/intel/uncore: Add Sapphire Rapids server CHA support") +Reported-by: Stephane Eranian +Signed-off-by: Kan Liang +Signed-off-by: Peter Zijlstra (Intel) +Tested-by: Stephane Eranian +Cc: stable@vger.kernel.org +Link: https://lore.kernel.org/r/20230508140206.283708-1-kan.liang@linux.intel.com +Signed-off-by: Greg Kroah-Hartman +--- + arch/x86/events/intel/uncore_snbep.c | 11 +++++++++++ + 1 file changed, 11 insertions(+) + +--- a/arch/x86/events/intel/uncore_snbep.c ++++ b/arch/x86/events/intel/uncore_snbep.c +@@ -5822,6 +5822,7 @@ static struct intel_uncore_type spr_unco + }; + + #define UNCORE_SPR_NUM_UNCORE_TYPES 12 ++#define UNCORE_SPR_CHA 0 + #define UNCORE_SPR_IIO 1 + #define UNCORE_SPR_IMC 6 + +@@ -6064,12 +6065,22 @@ static int uncore_type_max_boxes(struct + return max + 1; + } + ++#define SPR_MSR_UNC_CBO_CONFIG 0x2FFE ++ + void spr_uncore_cpu_init(void) + { ++ struct intel_uncore_type *type; ++ u64 num_cbo; ++ + uncore_msr_uncores = uncore_get_uncores(UNCORE_ACCESS_MSR, + UNCORE_SPR_MSR_EXTRA_UNCORES, + spr_msr_uncores); + ++ type = uncore_find_type_by_id(uncore_msr_uncores, UNCORE_SPR_CHA); ++ if (type) { ++ rdmsrl(SPR_MSR_UNC_CBO_CONFIG, num_cbo); ++ type->num_boxes = num_cbo; ++ } + spr_uncore_iio_free_running.num_boxes = uncore_type_max_boxes(uncore_msr_uncores, UNCORE_SPR_IIO); + } + diff --git a/queue-5.15/series b/queue-5.15/series index 636c16a01c5..2a0d6804378 100644 --- a/queue-5.15/series +++ b/queue-5.15/series @@ -23,3 +23,5 @@ dt-binding-cdns-usb3-fix-cdns-on-chip-buff-size-type.patch x86-mm-avoid-incomplete-global-invlpg-flushes.patch selftests-memfd-fix-unknown-type-name-build-failure.patch parisc-fix-flush_dcache_page-for-usage-from-irq-context.patch +perf-x86-uncore-correct-the-number-of-chas-on-spr.patch +x86-topology-fix-erroneous-smp_num_siblings-on-intel-hybrid-platforms.patch diff --git a/queue-5.15/x86-topology-fix-erroneous-smp_num_siblings-on-intel-hybrid-platforms.patch b/queue-5.15/x86-topology-fix-erroneous-smp_num_siblings-on-intel-hybrid-platforms.patch new file mode 100644 index 00000000000..85cad4c3d76 --- /dev/null +++ b/queue-5.15/x86-topology-fix-erroneous-smp_num_siblings-on-intel-hybrid-platforms.patch @@ -0,0 +1,90 @@ +From edc0a2b5957652f4685ef3516f519f84807087db Mon Sep 17 00:00:00 2001 +From: Zhang Rui +Date: Thu, 23 Mar 2023 09:56:40 +0800 +Subject: x86/topology: Fix erroneous smp_num_siblings on Intel Hybrid platforms + +From: Zhang Rui + +commit edc0a2b5957652f4685ef3516f519f84807087db upstream. + +Traditionally, all CPUs in a system have identical numbers of SMT +siblings. That changes with hybrid processors where some logical CPUs +have a sibling and others have none. + +Today, the CPU boot code sets the global variable smp_num_siblings when +every CPU thread is brought up. The last thread to boot will overwrite +it with the number of siblings of *that* thread. That last thread to +boot will "win". If the thread is a Pcore, smp_num_siblings == 2. If it +is an Ecore, smp_num_siblings == 1. + +smp_num_siblings describes if the *system* supports SMT. It should +specify the maximum number of SMT threads among all cores. + +Ensure that smp_num_siblings represents the system-wide maximum number +of siblings by always increasing its value. Never allow it to decrease. + +On MeteorLake-P platform, this fixes a problem that the Ecore CPUs are +not updated in any cpu sibling map because the system is treated as an +UP system when probing Ecore CPUs. + +Below shows part of the CPU topology information before and after the +fix, for both Pcore and Ecore CPU (cpu0 is Pcore, cpu 12 is Ecore). +... +-/sys/devices/system/cpu/cpu0/topology/package_cpus:000fff +-/sys/devices/system/cpu/cpu0/topology/package_cpus_list:0-11 ++/sys/devices/system/cpu/cpu0/topology/package_cpus:3fffff ++/sys/devices/system/cpu/cpu0/topology/package_cpus_list:0-21 +... +-/sys/devices/system/cpu/cpu12/topology/package_cpus:001000 +-/sys/devices/system/cpu/cpu12/topology/package_cpus_list:12 ++/sys/devices/system/cpu/cpu12/topology/package_cpus:3fffff ++/sys/devices/system/cpu/cpu12/topology/package_cpus_list:0-21 + +Notice that the "before" 'package_cpus_list' has only one CPU. This +means that userspace tools like lscpu will see a little laptop like +an 11-socket system: + +-Core(s) per socket: 1 +-Socket(s): 11 ++Core(s) per socket: 16 ++Socket(s): 1 + +This is also expected to make the scheduler do rather wonky things +too. + +[ dhansen: remove CPUID detail from changelog, add end user effects ] + +CC: stable@kernel.org +Fixes: bbb65d2d365e ("x86: use cpuid vector 0xb when available for detecting cpu topology") +Fixes: 95f3d39ccf7a ("x86/cpu/topology: Provide detect_extended_topology_early()") +Suggested-by: Len Brown +Signed-off-by: Zhang Rui +Signed-off-by: Dave Hansen +Acked-by: Peter Zijlstra (Intel) +Link: https://lore.kernel.org/all/20230323015640.27906-1-rui.zhang%40intel.com +Signed-off-by: Greg Kroah-Hartman +--- + arch/x86/kernel/cpu/topology.c | 5 +++-- + 1 file changed, 3 insertions(+), 2 deletions(-) + +--- a/arch/x86/kernel/cpu/topology.c ++++ b/arch/x86/kernel/cpu/topology.c +@@ -79,7 +79,7 @@ int detect_extended_topology_early(struc + * initial apic id, which also represents 32-bit extended x2apic id. + */ + c->initial_apicid = edx; +- smp_num_siblings = LEVEL_MAX_SIBLINGS(ebx); ++ smp_num_siblings = max_t(int, smp_num_siblings, LEVEL_MAX_SIBLINGS(ebx)); + #endif + return 0; + } +@@ -109,7 +109,8 @@ int detect_extended_topology(struct cpui + */ + cpuid_count(leaf, SMT_LEVEL, &eax, &ebx, &ecx, &edx); + c->initial_apicid = edx; +- core_level_siblings = smp_num_siblings = LEVEL_MAX_SIBLINGS(ebx); ++ core_level_siblings = LEVEL_MAX_SIBLINGS(ebx); ++ smp_num_siblings = max_t(int, smp_num_siblings, LEVEL_MAX_SIBLINGS(ebx)); + core_plus_mask_width = ht_mask_width = BITS_SHIFT_NEXT_LEVEL(eax); + die_level_siblings = LEVEL_MAX_SIBLINGS(ebx); + pkg_mask_width = die_plus_mask_width = BITS_SHIFT_NEXT_LEVEL(eax);