From: Florian Krohm Date: Wed, 12 Mar 2025 22:36:33 +0000 (+0000) Subject: s390x: Remove macro definitions for hardware facilities X-Git-Tag: VALGRIND_3_25_0~105 X-Git-Url: http://git.ipfire.org/?a=commitdiff_plain;h=aee4a0a72e9a0dc49af18806643a49749db7eb5c;p=thirdparty%2Fvalgrind.git s390x: Remove macro definitions for hardware facilities Remove the facility-bit macros S390_FAC_... They are guaranteed to never change and are used only in m_machine.c Part of fixing https://bugs.kde.org/show_bug.cgi?id=496950 --- diff --git a/VEX/pub/libvex_s390x_common.h b/VEX/pub/libvex_s390x_common.h index dda5ffd31..ea6a59d27 100644 --- a/VEX/pub/libvex_s390x_common.h +++ b/VEX/pub/libvex_s390x_common.h @@ -68,43 +68,6 @@ #define S390_INNERLOOP_FRAME_SIZE ((8+1+1)*8 + 160) -/*--------------------------------------------------------------*/ -/*--- Facility bits ---*/ -/*--------------------------------------------------------------*/ - -/* The value of the macro is the number of the facility bit as per POP. */ -#define S390_FAC_MSA 17 // message-security-assist -#define S390_FAC_LDISP 18 // long displacement -#define S390_FAC_HFPMAS 20 // HFP multiply-and-add-subtract -#define S390_FAC_EIMM 21 // extended immediate -#define S390_FAC_HFPUNX 23 // HFP unnormalized extension -#define S390_FAC_ETF2 24 // ETF2-enhancement -#define S390_FAC_STCKF 25 // store clock fast insn -#define S390_FAC_PENH 26 // parsing-enhancement -#define S390_FAC_ETF3 30 // ETF3-enhancement -#define S390_FAC_XCPUT 31 // extract-CPU-time -#define S390_FAC_GIE 34 // general insn extension -#define S390_FAC_EXEXT 35 // execute extension -#define S390_FAC_FPEXT 37 // floating-point extension -#define S390_FAC_FPSE 41 // floating-point support enhancement -#define S390_FAC_DFP 42 // decimal floating point -#define S390_FAC_PFPO 44 // perform floating point operation insn -#define S390_FAC_HIGHW 45 // high-word extension -#define S390_FAC_LSC 45 // load/store on condition -#define S390_FAC_DFPZC 48 // DFP zoned-conversion -#define S390_FAC_MISC 49 // miscellaneous insn -#define S390_FAC_CTREXE 50 // constrained transactional execution -#define S390_FAC_LSC2 53 // load/store on condition 2 and load and zero rightmost byte -#define S390_FAC_MSA5 57 // message-security-assist 5 -#define S390_FAC_MI2 58 // miscellaneous-instruction-extensions 2 -#define S390_FAC_TREXE 73 // transactional execution -#define S390_FAC_MSA4 77 // message-security-assist 4 -#define S390_FAC_VX 129 // vector facility -#define S390_FAC_VXE 135 // vector enhancements facility 1 -#define S390_FAC_VXE2 148 // vector enhancements facility 2 -#define S390_FAC_DFLT 151 // deflate-conversion facility -#define S390_FAC_NNPA 165 // NNPA facility - /*--------------------------------------------------------------*/ /*--- Extensions ---*/ /*--------------------------------------------------------------*/ diff --git a/coregrind/m_machine.c b/coregrind/m_machine.c index dec4f2373..3b3671455 100644 --- a/coregrind/m_machine.c +++ b/coregrind/m_machine.c @@ -1620,23 +1620,23 @@ Bool VG_(machine_get_hwcaps)( void ) UInt hwcaps_bit; const HChar name[6]; // may need adjustment for new facility names } fac_hwcaps[] = { - { False, S390_FAC_EIMM, VEX_HWCAPS_S390X_EIMM, "EIMM" }, - { False, S390_FAC_GIE, VEX_HWCAPS_S390X_GIE, "GIE" }, - { False, S390_FAC_DFP, VEX_HWCAPS_S390X_DFP, "DFP" }, - { False, S390_FAC_FPSE, VEX_HWCAPS_S390X_FGX, "FGX" }, - { False, S390_FAC_ETF2, VEX_HWCAPS_S390X_ETF2, "ETF2" }, - { False, S390_FAC_ETF3, VEX_HWCAPS_S390X_ETF3, "ETF3" }, - { False, S390_FAC_STCKF, VEX_HWCAPS_S390X_STCKF, "STCKF" }, - { False, S390_FAC_FPEXT, VEX_HWCAPS_S390X_FPEXT, "FPEXT" }, - { False, S390_FAC_LSC, VEX_HWCAPS_S390X_LSC, "LSC" }, - { False, S390_FAC_PFPO, VEX_HWCAPS_S390X_PFPO, "PFPO" }, - { False, S390_FAC_VX, VEX_HWCAPS_S390X_VX, "VX" }, - { False, S390_FAC_MSA5, VEX_HWCAPS_S390X_MSA5, "MSA5" }, - { False, S390_FAC_MI2, VEX_HWCAPS_S390X_MI2, "MI2" }, - { False, S390_FAC_LSC2, VEX_HWCAPS_S390X_LSC2, "LSC2" }, - { False, S390_FAC_VXE, VEX_HWCAPS_S390X_VXE, "VXE" }, - { False, S390_FAC_DFLT, VEX_HWCAPS_S390X_DFLT, "DFLT" }, - { False, S390_FAC_NNPA, VEX_HWCAPS_S390X_NNPA, "NNPA" }, + { False, 21, VEX_HWCAPS_S390X_EIMM, "EIMM" }, + { False, 34, VEX_HWCAPS_S390X_GIE, "GIE" }, + { False, 42, VEX_HWCAPS_S390X_DFP, "DFP" }, + { False, 41, VEX_HWCAPS_S390X_FGX, "FGX" }, + { False, 24, VEX_HWCAPS_S390X_ETF2, "ETF2" }, + { False, 30, VEX_HWCAPS_S390X_ETF3, "ETF3" }, + { False, 25, VEX_HWCAPS_S390X_STCKF, "STCKF" }, + { False, 37, VEX_HWCAPS_S390X_FPEXT, "FPEXT" }, + { False, 45, VEX_HWCAPS_S390X_LSC, "LSC" }, + { False, 44, VEX_HWCAPS_S390X_PFPO, "PFPO" }, + { False, 129, VEX_HWCAPS_S390X_VX, "VX" }, + { False, 57, VEX_HWCAPS_S390X_MSA5, "MSA5" }, + { False, 58, VEX_HWCAPS_S390X_MI2, "MI2" }, + { False, 53, VEX_HWCAPS_S390X_LSC2, "LSC2" }, + { False, 135, VEX_HWCAPS_S390X_VXE, "VXE" }, + { False, 151, VEX_HWCAPS_S390X_DFLT, "DFLT" }, + { False, 165, VEX_HWCAPS_S390X_NNPA, "NNPA" }, }; /* Set hwcaps according to the detected facilities */