From: Greg Kroah-Hartman Date: Thu, 21 Aug 2025 13:09:37 +0000 (+0200) Subject: 6.16-stable patches X-Git-Tag: v6.16.3~99 X-Git-Url: http://git.ipfire.org/?a=commitdiff_plain;h=b008d0f6684761ff20888b004c017c77e239b9a8;p=thirdparty%2Fkernel%2Fstable-queue.git 6.16-stable patches added patches: apparmor-fix-8-byte-alignment-for-initial-dfa-blob-streams.patch arm64-dts-apple-t8012-j132-include-touchbar-framebuffer-node.patch arm64-dts-exynos-gs101-ufs-add-dma-coherent-property.patch arm64-dts-exynos7870-add-quirk-to-disable-usb2-lpm-in-gadget-mode.patch arm64-dts-exynos7870-j6lte-reduce-memory-ranges-to-base-amount.patch arm64-dts-exynos7870-on7xelte-reduce-memory-ranges-to-base-amount.patch arm64-dts-rockchip-add-hdmi-phy-pll-clock-source-to-vop2-on-rk3576.patch arm64-dts-rockchip-enable-hdmi-phy-clk-provider-on-rk3576.patch arm64-dts-rockchip-remove-workaround-that-prevented-turing-rk1-gpu-power-regulator-control.patch arm64-dts-ti-k3-am62-main-remove-emmc-high-speed-ddr-support.patch arm64-dts-ti-k3-am62-move-emmc-pinmux-to-top-level-board-file.patch arm64-dts-ti-k3-am62-verdin-enable-pull-ups-on-i2c-buses.patch arm64-dts-ti-k3-am62a7-sk-fix-pinmux-for-main_uart1.patch arm64-dts-ti-k3-pinctrl-enable-schmitt-trigger-by-default.patch ata-libata-scsi-fix-ata_to_sense_error-status-handling.patch ata-libata-scsi-fix-cdl-control.patch ata-libata-scsi-return-aborted-command-when-missing-sense-and-result-tf.patch dt-bindings-display-sprd-sharkl3-dpu-fix-missing-clocks-constraints.patch dt-bindings-display-sprd-sharkl3-dsi-host-fix-missing-clocks-constraints.patch dt-bindings-display-vop2-add-optional-pll-clock-property-for-rk3576.patch scsi-dt-bindings-mediatek-ufs-add-ufs-disable-mcq-flag-for-ufs-host.patch scsi-mpi3mr-fix-race-between-config-read-submit-and-interrupt-completion.patch scsi-ufs-exynos-fix-programming-of-hci_utrl_nexus_type.patch scsi-ufs-ufs-pci-fix-default-runtime-and-system-pm-levels.patch scsi-ufs-ufs-pci-fix-hibernate-state-transition-for-intel-mtl-like-host-controllers.patch --- diff --git a/queue-6.16/apparmor-fix-8-byte-alignment-for-initial-dfa-blob-streams.patch b/queue-6.16/apparmor-fix-8-byte-alignment-for-initial-dfa-blob-streams.patch new file mode 100644 index 0000000000..719d7392ff --- /dev/null +++ b/queue-6.16/apparmor-fix-8-byte-alignment-for-initial-dfa-blob-streams.patch @@ -0,0 +1,50 @@ +From c567de2c4f5fe6e079672e074e1bc6122bf7e444 Mon Sep 17 00:00:00 2001 +From: Helge Deller +Date: Sat, 31 May 2025 17:08:21 +0200 +Subject: apparmor: Fix 8-byte alignment for initial dfa blob streams + +From: Helge Deller + +commit c567de2c4f5fe6e079672e074e1bc6122bf7e444 upstream. + +The dfa blob stream for the aa_dfa_unpack() function is expected to be aligned +on a 8 byte boundary. + +The static nulldfa_src[] and stacksplitdfa_src[] arrays store the initial +apparmor dfa blob streams, but since they are declared as an array-of-chars +the compiler and linker will only ensure a "char" (1-byte) alignment. + +Add an __aligned(8) annotation to the arrays to tell the linker to always +align them on a 8-byte boundary. This avoids runtime warnings at startup on +alignment-sensitive platforms like parisc such as: + + Kernel: unaligned access to 0x7f2a584a in aa_dfa_unpack+0x124/0x788 (iir 0xca0109f) + Kernel: unaligned access to 0x7f2a584e in aa_dfa_unpack+0x210/0x788 (iir 0xca8109c) + Kernel: unaligned access to 0x7f2a586a in aa_dfa_unpack+0x278/0x788 (iir 0xcb01090) + +Signed-off-by: Helge Deller +Cc: stable@vger.kernel.org +Fixes: 98b824ff8984 ("apparmor: refcount the pdb") +Signed-off-by: John Johansen +Signed-off-by: Greg Kroah-Hartman +--- + security/apparmor/lsm.c | 4 ++-- + 1 file changed, 2 insertions(+), 2 deletions(-) + +--- a/security/apparmor/lsm.c ++++ b/security/apparmor/lsm.c +@@ -2149,12 +2149,12 @@ static int __init apparmor_nf_ip_init(vo + __initcall(apparmor_nf_ip_init); + #endif + +-static char nulldfa_src[] = { ++static char nulldfa_src[] __aligned(8) = { + #include "nulldfa.in" + }; + static struct aa_dfa *nulldfa; + +-static char stacksplitdfa_src[] = { ++static char stacksplitdfa_src[] __aligned(8) = { + #include "stacksplitdfa.in" + }; + struct aa_dfa *stacksplitdfa; diff --git a/queue-6.16/arm64-dts-apple-t8012-j132-include-touchbar-framebuffer-node.patch b/queue-6.16/arm64-dts-apple-t8012-j132-include-touchbar-framebuffer-node.patch new file mode 100644 index 0000000000..ca4372716d --- /dev/null +++ b/queue-6.16/arm64-dts-apple-t8012-j132-include-touchbar-framebuffer-node.patch @@ -0,0 +1,38 @@ +From ef68a0e1087882850628000f28078e1c4df917ee Mon Sep 17 00:00:00 2001 +From: Nick Chan +Date: Fri, 20 Jun 2025 18:35:36 +0800 +Subject: arm64: dts: apple: t8012-j132: Include touchbar framebuffer node + +From: Nick Chan + +commit ef68a0e1087882850628000f28078e1c4df917ee upstream. + +Apple T2 MacBookPro15,2 (j132) has a touchbar so include the framebuffer +node. + +Cc: stable@vger.kernel.org +Fixes: 4efbcb623e9bc ("arm64: dts: apple: Add T2 devices") +Signed-off-by: Nick Chan +Link: https://lore.kernel.org/stable/20250620-j132-fb-v1-1-bc6937baf0b9%40gmail.com +Link: https://lore.kernel.org/r/20250620-j132-fb-v2-1-65f100182085@gmail.com +Signed-off-by: Sven Peter +Signed-off-by: Greg Kroah-Hartman +--- + arch/arm64/boot/dts/apple/t8012-j132.dts | 1 + + 1 file changed, 1 insertion(+) + +diff --git a/arch/arm64/boot/dts/apple/t8012-j132.dts b/arch/arm64/boot/dts/apple/t8012-j132.dts +index 778a69be18dd..7dcac51703ff 100644 +--- a/arch/arm64/boot/dts/apple/t8012-j132.dts ++++ b/arch/arm64/boot/dts/apple/t8012-j132.dts +@@ -7,6 +7,7 @@ + /dts-v1/; + + #include "t8012-jxxx.dtsi" ++#include "t8012-touchbar.dtsi" + + / { + model = "Apple T2 MacBookPro15,2 (j132)"; +-- +2.50.1 + diff --git a/queue-6.16/arm64-dts-exynos-gs101-ufs-add-dma-coherent-property.patch b/queue-6.16/arm64-dts-exynos-gs101-ufs-add-dma-coherent-property.patch new file mode 100644 index 0000000000..c104970985 --- /dev/null +++ b/queue-6.16/arm64-dts-exynos-gs101-ufs-add-dma-coherent-property.patch @@ -0,0 +1,43 @@ +From 4292564c71cffd8094abcc52dd4840870d05cd30 Mon Sep 17 00:00:00 2001 +From: Peter Griffin +Date: Fri, 14 Mar 2025 15:38:02 +0000 +Subject: arm64: dts: exynos: gs101: ufs: add dma-coherent property +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +From: Peter Griffin + +commit 4292564c71cffd8094abcc52dd4840870d05cd30 upstream. + +ufs-exynos driver configures the sysreg shareability as +cacheable for gs101 so we need to set the dma-coherent +property so the descriptors are also allocated cacheable. + +This fixes the UFS stability issues we have seen with +the upstream UFS driver on gs101. + +Fixes: 4c65d7054b4c ("arm64: dts: exynos: gs101: Add ufs and ufs-phy dt nodes") +Cc: stable@vger.kernel.org +Suggested-by: Will McVicker +Signed-off-by: Peter Griffin +Tested-by: Will McVicker +Tested-by: André Draszik +Reviewed-by: André Draszik +Link: https://lore.kernel.org/r/20250314-ufs-dma-coherent-v1-1-bdf9f9be2919@linaro.org +Signed-off-by: Krzysztof Kozlowski +Signed-off-by: Greg Kroah-Hartman +--- + arch/arm64/boot/dts/exynos/google/gs101.dtsi | 1 + + 1 file changed, 1 insertion(+) + +--- a/arch/arm64/boot/dts/exynos/google/gs101.dtsi ++++ b/arch/arm64/boot/dts/exynos/google/gs101.dtsi +@@ -1371,6 +1371,7 @@ + <&cmu_hsi2 CLK_GOUT_HSI2_SYSREG_HSI2_PCLK>; + clock-names = "core_clk", "sclk_unipro_main", "fmp", + "aclk", "pclk", "sysreg"; ++ dma-coherent; + freq-table-hz = <0 0>, <0 0>, <0 0>, <0 0>, <0 0>, <0 0>; + pinctrl-0 = <&ufs_rst_n &ufs_refclk_out>; + pinctrl-names = "default"; diff --git a/queue-6.16/arm64-dts-exynos7870-add-quirk-to-disable-usb2-lpm-in-gadget-mode.patch b/queue-6.16/arm64-dts-exynos7870-add-quirk-to-disable-usb2-lpm-in-gadget-mode.patch new file mode 100644 index 0000000000..2e734d2977 --- /dev/null +++ b/queue-6.16/arm64-dts-exynos7870-add-quirk-to-disable-usb2-lpm-in-gadget-mode.patch @@ -0,0 +1,42 @@ +From e9355e894aebcbeacffd284644749190cc5f33a4 Mon Sep 17 00:00:00 2001 +From: Kaustabh Chakraborty +Date: Thu, 26 Jun 2025 13:02:56 +0530 +Subject: arm64: dts: exynos7870: add quirk to disable USB2 LPM in gadget mode + +From: Kaustabh Chakraborty + +commit e9355e894aebcbeacffd284644749190cc5f33a4 upstream. + +In gadget mode, USB connections are sluggish. The device won't send +packets to the host unless the host sends packets to the device. For +instance, SSH-ing through the USB network would apparently not work +unless you're flood-pinging the device's IP. + +Add the property snps,usb2-gadget-lpm-disable to the dwc3 node, which +seems to solve this issue. + +Fixes: d6f3a7f91fdb ("arm64: dts: exynos: add initial devicetree support for exynos7870") +Cc: stable@vger.kernel.org # v6.16 +Signed-off-by: Kaustabh Chakraborty +Link: https://lore.kernel.org/r/20250626-exynos7870-dts-fixes-v1-1-349987874d9a@disroot.org +Signed-off-by: Krzysztof Kozlowski +Signed-off-by: Greg Kroah-Hartman +--- + arch/arm64/boot/dts/exynos/exynos7870.dtsi | 1 + + 1 file changed, 1 insertion(+) + +diff --git a/arch/arm64/boot/dts/exynos/exynos7870.dtsi b/arch/arm64/boot/dts/exynos/exynos7870.dtsi +index 5cba8c9bb403..d5d347623b90 100644 +--- a/arch/arm64/boot/dts/exynos/exynos7870.dtsi ++++ b/arch/arm64/boot/dts/exynos/exynos7870.dtsi +@@ -327,6 +327,7 @@ + phys = <&usbdrd_phy 0>; + + usb-role-switch; ++ snps,usb2-gadget-lpm-disable; + }; + }; + +-- +2.50.1 + diff --git a/queue-6.16/arm64-dts-exynos7870-j6lte-reduce-memory-ranges-to-base-amount.patch b/queue-6.16/arm64-dts-exynos7870-j6lte-reduce-memory-ranges-to-base-amount.patch new file mode 100644 index 0000000000..24fbb1b3e3 --- /dev/null +++ b/queue-6.16/arm64-dts-exynos7870-j6lte-reduce-memory-ranges-to-base-amount.patch @@ -0,0 +1,44 @@ +From 49a27c6c392dec46c826ee586f7ec8973acaeed7 Mon Sep 17 00:00:00 2001 +From: Kaustabh Chakraborty +Date: Thu, 26 Jun 2025 13:02:58 +0530 +Subject: arm64: dts: exynos7870-j6lte: reduce memory ranges to base amount + +From: Kaustabh Chakraborty + +commit 49a27c6c392dec46c826ee586f7ec8973acaeed7 upstream. + +The device is available in multiple variants with differing RAM +capacities. The memory range defined in the 0x80000000 bank exceeds the +address range of the memory controller, which eventually leads to ARM +SError crashes. Reduce the bank size to a value which is available to +all devices. + +The bootloader must be responsible for identifying the RAM capacity and +editing the memory node accordingly. + +Fixes: d6f3a7f91fdb ("arm64: dts: exynos: add initial devicetree support for exynos7870") +Cc: stable@vger.kernel.org # v6.16 +Signed-off-by: Kaustabh Chakraborty +Link: https://lore.kernel.org/r/20250626-exynos7870-dts-fixes-v1-3-349987874d9a@disroot.org +Signed-off-by: Krzysztof Kozlowski +Signed-off-by: Greg Kroah-Hartman +--- + arch/arm64/boot/dts/exynos/exynos7870-j6lte.dts | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/arch/arm64/boot/dts/exynos/exynos7870-j6lte.dts b/arch/arm64/boot/dts/exynos/exynos7870-j6lte.dts +index 61eec1aff32e..b8ce433b93b1 100644 +--- a/arch/arm64/boot/dts/exynos/exynos7870-j6lte.dts ++++ b/arch/arm64/boot/dts/exynos/exynos7870-j6lte.dts +@@ -89,7 +89,7 @@ + memory@40000000 { + device_type = "memory"; + reg = <0x0 0x40000000 0x3d800000>, +- <0x0 0x80000000 0x7d800000>; ++ <0x0 0x80000000 0x40000000>; + }; + + pwrseq_mmc1: pwrseq-mmc1 { +-- +2.50.1 + diff --git a/queue-6.16/arm64-dts-exynos7870-on7xelte-reduce-memory-ranges-to-base-amount.patch b/queue-6.16/arm64-dts-exynos7870-on7xelte-reduce-memory-ranges-to-base-amount.patch new file mode 100644 index 0000000000..1ad31bb0c0 --- /dev/null +++ b/queue-6.16/arm64-dts-exynos7870-on7xelte-reduce-memory-ranges-to-base-amount.patch @@ -0,0 +1,44 @@ +From 2bdfa35a7bb6e3a319e7a290baa44720bc96e5e4 Mon Sep 17 00:00:00 2001 +From: Kaustabh Chakraborty +Date: Thu, 26 Jun 2025 13:02:57 +0530 +Subject: arm64: dts: exynos7870-on7xelte: reduce memory ranges to base amount + +From: Kaustabh Chakraborty + +commit 2bdfa35a7bb6e3a319e7a290baa44720bc96e5e4 upstream. + +The device is available in multiple variants with differing RAM +capacities. The memory range defined in the 0x80000000 bank exceeds the +address range of the memory controller, which eventually leads to ARM +SError crashes. Reduce the bank size to a value which is available to +all devices. + +The bootloader must be responsible for identifying the RAM capacity and +editing the memory node accordingly. + +Fixes: d6f3a7f91fdb ("arm64: dts: exynos: add initial devicetree support for exynos7870") +Cc: stable@vger.kernel.org # v6.16 +Signed-off-by: Kaustabh Chakraborty +Link: https://lore.kernel.org/r/20250626-exynos7870-dts-fixes-v1-2-349987874d9a@disroot.org +Signed-off-by: Krzysztof Kozlowski +Signed-off-by: Greg Kroah-Hartman +--- + arch/arm64/boot/dts/exynos/exynos7870-on7xelte.dts | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/arch/arm64/boot/dts/exynos/exynos7870-on7xelte.dts b/arch/arm64/boot/dts/exynos/exynos7870-on7xelte.dts +index eb97dcc41542..b1d9eff5a827 100644 +--- a/arch/arm64/boot/dts/exynos/exynos7870-on7xelte.dts ++++ b/arch/arm64/boot/dts/exynos/exynos7870-on7xelte.dts +@@ -78,7 +78,7 @@ + memory@40000000 { + device_type = "memory"; + reg = <0x0 0x40000000 0x3e400000>, +- <0x0 0x80000000 0xbe400000>; ++ <0x0 0x80000000 0x80000000>; + }; + + pwrseq_mmc1: pwrseq-mmc1 { +-- +2.50.1 + diff --git a/queue-6.16/arm64-dts-rockchip-add-hdmi-phy-pll-clock-source-to-vop2-on-rk3576.patch b/queue-6.16/arm64-dts-rockchip-add-hdmi-phy-pll-clock-source-to-vop2-on-rk3576.patch new file mode 100644 index 0000000000..4737927986 --- /dev/null +++ b/queue-6.16/arm64-dts-rockchip-add-hdmi-phy-pll-clock-source-to-vop2-on-rk3576.patch @@ -0,0 +1,62 @@ +From 4ab8b8ac952fb08d03655e1da0cfee07589e428f Mon Sep 17 00:00:00 2001 +From: Cristian Ciocaltea +Date: Thu, 12 Jun 2025 00:47:49 +0300 +Subject: arm64: dts: rockchip: Add HDMI PHY PLL clock source to VOP2 on rk3576 + +From: Cristian Ciocaltea + +commit 4ab8b8ac952fb08d03655e1da0cfee07589e428f upstream. + +Since commit c871a311edf0 ("phy: rockchip: samsung-hdptx: Setup TMDS +char rate via phy_configure_opts_hdmi"), the workaround of passing the +rate from DW HDMI QP bridge driver via phy_set_bus_width() became +partially broken, as it cannot reliably handle mode switches anymore. + +Attempting to fix this up at PHY level would not only introduce +additional hacks, but it would also fail to adequately resolve the +display issues that are a consequence of the system CRU limitations. + +Instead, proceed with the solution already implemented for RK3588: make +use of the HDMI PHY PLL as a better suited DCLK source for VOP2. This +will not only address the aforementioned problem, but it should also +facilitate the proper operation of display modes up to 4K@60Hz. + +It's worth noting that anything above 4K@30Hz still requires high TMDS +clock ratio and scrambling support, which hasn't been mainlined yet. + +Fixes: d74b842cab08 ("arm64: dts: rockchip: Add vop for rk3576") +Cc: stable@vger.kernel.org +Signed-off-by: Cristian Ciocaltea +Tested-By: Detlev Casanova +Tested-by: Nicolas Frattaroli +Link: https://lore.kernel.org/r/20250612-rk3576-hdmitx-fix-v1-3-4b11007d8675@collabora.com +Signed-off-by: Heiko Stuebner +Signed-off-by: Greg Kroah-Hartman +--- + arch/arm64/boot/dts/rockchip/rk3576.dtsi | 6 ++++-- + 1 file changed, 4 insertions(+), 2 deletions(-) + +diff --git a/arch/arm64/boot/dts/rockchip/rk3576.dtsi b/arch/arm64/boot/dts/rockchip/rk3576.dtsi +index 9fc18384f609..1fec0ecea91d 100644 +--- a/arch/arm64/boot/dts/rockchip/rk3576.dtsi ++++ b/arch/arm64/boot/dts/rockchip/rk3576.dtsi +@@ -1155,12 +1155,14 @@ + <&cru HCLK_VOP>, + <&cru DCLK_VP0>, + <&cru DCLK_VP1>, +- <&cru DCLK_VP2>; ++ <&cru DCLK_VP2>, ++ <&hdptxphy>; + clock-names = "aclk", + "hclk", + "dclk_vp0", + "dclk_vp1", +- "dclk_vp2"; ++ "dclk_vp2", ++ "pll_hdmiphy0"; + iommus = <&vop_mmu>; + power-domains = <&power RK3576_PD_VOP>; + rockchip,grf = <&sys_grf>; +-- +2.50.1 + diff --git a/queue-6.16/arm64-dts-rockchip-enable-hdmi-phy-clk-provider-on-rk3576.patch b/queue-6.16/arm64-dts-rockchip-enable-hdmi-phy-clk-provider-on-rk3576.patch new file mode 100644 index 0000000000..105f6999a1 --- /dev/null +++ b/queue-6.16/arm64-dts-rockchip-enable-hdmi-phy-clk-provider-on-rk3576.patch @@ -0,0 +1,37 @@ +From aba7987a536cee67fb0cb724099096fd8f8f5350 Mon Sep 17 00:00:00 2001 +From: Cristian Ciocaltea +Date: Thu, 12 Jun 2025 00:47:48 +0300 +Subject: arm64: dts: rockchip: Enable HDMI PHY clk provider on rk3576 + +From: Cristian Ciocaltea + +commit aba7987a536cee67fb0cb724099096fd8f8f5350 upstream. + +As with the RK3588 SoC, the HDMI PHY PLL on RK3576 can be used as a more +accurate pixel clock source for VOP2, which is actually mandatory to +ensure proper support for display modes handling. + +Add the missing #clock-cells property to allow using the clock provider +functionality of HDMI PHY. + +Fixes: ad0ea230ab2a ("arm64: dts: rockchip: Add hdmi for rk3576") +Cc: stable@vger.kernel.org +Signed-off-by: Cristian Ciocaltea +Tested-by: Nicolas Frattaroli +Link: https://lore.kernel.org/r/20250612-rk3576-hdmitx-fix-v1-2-4b11007d8675@collabora.com +Signed-off-by: Heiko Stuebner +Signed-off-by: Greg Kroah-Hartman +--- + arch/arm64/boot/dts/rockchip/rk3576.dtsi | 1 + + 1 file changed, 1 insertion(+) + +--- a/arch/arm64/boot/dts/rockchip/rk3576.dtsi ++++ b/arch/arm64/boot/dts/rockchip/rk3576.dtsi +@@ -2393,6 +2393,7 @@ + reg = <0x0 0x2b000000 0x0 0x2000>; + clocks = <&cru CLK_PHY_REF_SRC>, <&cru PCLK_HDPTX_APB>; + clock-names = "ref", "apb"; ++ #clock-cells = <0>; + resets = <&cru SRST_P_HDPTX_APB>, <&cru SRST_HDPTX_INIT>, + <&cru SRST_HDPTX_CMN>, <&cru SRST_HDPTX_LANE>; + reset-names = "apb", "init", "cmn", "lane"; diff --git a/queue-6.16/arm64-dts-rockchip-remove-workaround-that-prevented-turing-rk1-gpu-power-regulator-control.patch b/queue-6.16/arm64-dts-rockchip-remove-workaround-that-prevented-turing-rk1-gpu-power-regulator-control.patch new file mode 100644 index 0000000000..8466724434 --- /dev/null +++ b/queue-6.16/arm64-dts-rockchip-remove-workaround-that-prevented-turing-rk1-gpu-power-regulator-control.patch @@ -0,0 +1,56 @@ +From de5b39d16318f9345f1ba7c1b684ba0c1cb6fdad Mon Sep 17 00:00:00 2001 +From: Sam Edwards +Date: Sun, 8 Jun 2025 11:48:55 -0700 +Subject: arm64: dts: rockchip: Remove workaround that prevented Turing RK1 GPU power regulator control + +From: Sam Edwards + +commit de5b39d16318f9345f1ba7c1b684ba0c1cb6fdad upstream. + +The RK3588 GPU power domain cannot be activated unless the external +power regulator is already on. When GPU support was added to this DT, +we had no way to represent this requirement, so `regulator-always-on` +was added to the `vdd_gpu_s0` regulator in order to ensure stability. +A later patch series (see "Fixes:" commit) resolved this shortcoming, +but that commit left the workaround -- and rendered the comment above +it no longer correct. + +Remove the workaround to allow the GPU power regulator to power off, now +that the DT includes the necessary information to power it back on +correctly. + +Fixes: f94500eb7328b ("arm64: dts: rockchip: Add GPU power domain regulator dependency for RK3588") +Signed-off-by: Sam Edwards +Cc: stable@vger.kernel.org +Link: https://lore.kernel.org/r/20250608184855.130206-1-CFSworks@gmail.com +Signed-off-by: Heiko Stuebner +Signed-off-by: Greg Kroah-Hartman +--- + arch/arm64/boot/dts/rockchip/rk3588-turing-rk1.dtsi | 11 ----------- + 1 file changed, 11 deletions(-) + +diff --git a/arch/arm64/boot/dts/rockchip/rk3588-turing-rk1.dtsi b/arch/arm64/boot/dts/rockchip/rk3588-turing-rk1.dtsi +index 60ad272982ad..6daea8961fdd 100644 +--- a/arch/arm64/boot/dts/rockchip/rk3588-turing-rk1.dtsi ++++ b/arch/arm64/boot/dts/rockchip/rk3588-turing-rk1.dtsi +@@ -398,17 +398,6 @@ + + regulators { + vdd_gpu_s0: vdd_gpu_mem_s0: dcdc-reg1 { +- /* +- * RK3588's GPU power domain cannot be enabled +- * without this regulator active, but it +- * doesn't have to be on when the GPU PD is +- * disabled. Because the PD binding does not +- * currently allow us to express this +- * relationship, we have no choice but to do +- * this instead: +- */ +- regulator-always-on; +- + regulator-boot-on; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <950000>; +-- +2.50.1 + diff --git a/queue-6.16/arm64-dts-ti-k3-am62-main-remove-emmc-high-speed-ddr-support.patch b/queue-6.16/arm64-dts-ti-k3-am62-main-remove-emmc-high-speed-ddr-support.patch new file mode 100644 index 0000000000..0c2e2286a8 --- /dev/null +++ b/queue-6.16/arm64-dts-ti-k3-am62-main-remove-emmc-high-speed-ddr-support.patch @@ -0,0 +1,34 @@ +From 265f70af805f33a0dfc90f50cc0f116f702c3811 Mon Sep 17 00:00:00 2001 +From: Judith Mendez +Date: Mon, 7 Jul 2025 14:12:50 -0500 +Subject: arm64: dts: ti: k3-am62-main: Remove eMMC High Speed DDR support + +From: Judith Mendez + +commit 265f70af805f33a0dfc90f50cc0f116f702c3811 upstream. + +For eMMC, High Speed DDR mode is not supported [0], so remove +mmc-ddr-1_8v flag which adds the capability. + +[0] https://www.ti.com/lit/gpn/am625 + +Fixes: c37c58fdeb8a ("arm64: dts: ti: k3-am62: Add more peripheral nodes") +Cc: stable@vger.kernel.org +Signed-off-by: Judith Mendez +Link: https://lore.kernel.org/r/20250707191250.3953990-1-jm@ti.com +Signed-off-by: Vignesh Raghavendra +Signed-off-by: Greg Kroah-Hartman +--- + arch/arm64/boot/dts/ti/k3-am62-main.dtsi | 1 - + 1 file changed, 1 deletion(-) + +--- a/arch/arm64/boot/dts/ti/k3-am62-main.dtsi ++++ b/arch/arm64/boot/dts/ti/k3-am62-main.dtsi +@@ -553,7 +553,6 @@ + clocks = <&k3_clks 57 5>, <&k3_clks 57 6>; + clock-names = "clk_ahb", "clk_xin"; + bus-width = <8>; +- mmc-ddr-1_8v; + mmc-hs200-1_8v; + ti,clkbuf-sel = <0x7>; + ti,otap-del-sel-legacy = <0x0>; diff --git a/queue-6.16/arm64-dts-ti-k3-am62-move-emmc-pinmux-to-top-level-board-file.patch b/queue-6.16/arm64-dts-ti-k3-am62-move-emmc-pinmux-to-top-level-board-file.patch new file mode 100644 index 0000000000..9307daf891 --- /dev/null +++ b/queue-6.16/arm64-dts-ti-k3-am62-move-emmc-pinmux-to-top-level-board-file.patch @@ -0,0 +1,149 @@ +From a0b8da04153eb61cc2eaeeea5cc404e91e557f6b Mon Sep 17 00:00:00 2001 +From: Judith Mendez +Date: Mon, 7 Jul 2025 14:08:30 -0500 +Subject: arm64: dts: ti: k3-am62*: Move eMMC pinmux to top level board file + +From: Judith Mendez + +commit a0b8da04153eb61cc2eaeeea5cc404e91e557f6b upstream. + +This moves pinmux child nodes for sdhci0 node from k3-am62x-sk-common +to each top level board file. This is needed since we require internal +pullups for AM62x SK and not for AM62 LP SK since it has external +pullups on DATA 1-7. + +Internal pulls are required for AM62 SK as per JESD84 spec +recommendation to prevent unconnected lines floating. + +Fixes: d19a66ae488a ("arm64: dts: ti: k3-am625-sk: Enable on board peripherals") +Cc: stable@vger.kernel.org +Signed-off-by: Judith Mendez +Link: https://lore.kernel.org/r/20250707190830.3951619-1-jm@ti.com +Signed-off-by: Vignesh Raghavendra +Signed-off-by: Greg Kroah-Hartman +--- + arch/arm64/boot/dts/ti/k3-am62-lp-sk.dts | 24 ++++++++++++++++++++++++ + arch/arm64/boot/dts/ti/k3-am625-sk.dts | 24 ++++++++++++++++++++++++ + arch/arm64/boot/dts/ti/k3-am62x-sk-common.dtsi | 24 ------------------------ + 3 files changed, 48 insertions(+), 24 deletions(-) + +--- a/arch/arm64/boot/dts/ti/k3-am62-lp-sk.dts ++++ b/arch/arm64/boot/dts/ti/k3-am62-lp-sk.dts +@@ -74,6 +74,22 @@ + }; + + &main_pmx0 { ++ main_mmc0_pins_default: main-mmc0-default-pins { ++ bootph-all; ++ pinctrl-single,pins = < ++ AM62X_IOPAD(0x220, PIN_INPUT, 0) /* (V3) MMC0_CMD */ ++ AM62X_IOPAD(0x218, PIN_INPUT, 0) /* (Y1) MMC0_CLK */ ++ AM62X_IOPAD(0x214, PIN_INPUT, 0) /* (V2) MMC0_DAT0 */ ++ AM62X_IOPAD(0x210, PIN_INPUT, 0) /* (V1) MMC0_DAT1 */ ++ AM62X_IOPAD(0x20c, PIN_INPUT, 0) /* (W2) MMC0_DAT2 */ ++ AM62X_IOPAD(0x208, PIN_INPUT, 0) /* (W1) MMC0_DAT3 */ ++ AM62X_IOPAD(0x204, PIN_INPUT, 0) /* (Y2) MMC0_DAT4 */ ++ AM62X_IOPAD(0x200, PIN_INPUT, 0) /* (W3) MMC0_DAT5 */ ++ AM62X_IOPAD(0x1fc, PIN_INPUT, 0) /* (W4) MMC0_DAT6 */ ++ AM62X_IOPAD(0x1f8, PIN_INPUT, 0) /* (V4) MMC0_DAT7 */ ++ >; ++ }; ++ + vddshv_sdio_pins_default: vddshv-sdio-default-pins { + pinctrl-single,pins = < + AM62X_IOPAD(0x07c, PIN_OUTPUT, 7) /* (M19) GPMC0_CLK.GPIO0_31 */ +@@ -144,6 +160,14 @@ + }; + }; + ++&sdhci0 { ++ bootph-all; ++ non-removable; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&main_mmc0_pins_default>; ++ status = "okay"; ++}; ++ + &sdhci1 { + vmmc-supply = <&vdd_mmc1>; + vqmmc-supply = <&vddshv_sdio>; +--- a/arch/arm64/boot/dts/ti/k3-am625-sk.dts ++++ b/arch/arm64/boot/dts/ti/k3-am625-sk.dts +@@ -106,6 +106,22 @@ + }; + + &main_pmx0 { ++ main_mmc0_pins_default: main-mmc0-default-pins { ++ bootph-all; ++ pinctrl-single,pins = < ++ AM62X_IOPAD(0x220, PIN_INPUT, 0) /* (Y3) MMC0_CMD */ ++ AM62X_IOPAD(0x218, PIN_INPUT, 0) /* (AB1) MMC0_CLK */ ++ AM62X_IOPAD(0x214, PIN_INPUT, 0) /* (AA2) MMC0_DAT0 */ ++ AM62X_IOPAD(0x210, PIN_INPUT_PULLUP, 0) /* (AA1) MMC0_DAT1 */ ++ AM62X_IOPAD(0x20c, PIN_INPUT_PULLUP, 0) /* (AA3) MMC0_DAT2 */ ++ AM62X_IOPAD(0x208, PIN_INPUT_PULLUP, 0) /* (Y4) MMC0_DAT3 */ ++ AM62X_IOPAD(0x204, PIN_INPUT_PULLUP, 0) /* (AB2) MMC0_DAT4 */ ++ AM62X_IOPAD(0x200, PIN_INPUT_PULLUP, 0) /* (AC1) MMC0_DAT5 */ ++ AM62X_IOPAD(0x1fc, PIN_INPUT_PULLUP, 0) /* (AD2) MMC0_DAT6 */ ++ AM62X_IOPAD(0x1f8, PIN_INPUT_PULLUP, 0) /* (AC2) MMC0_DAT7 */ ++ >; ++ }; ++ + main_rgmii2_pins_default: main-rgmii2-default-pins { + bootph-all; + pinctrl-single,pins = < +@@ -195,6 +211,14 @@ + }; + }; + ++&sdhci0 { ++ bootph-all; ++ non-removable; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&main_mmc0_pins_default>; ++ status = "okay"; ++}; ++ + &sdhci1 { + vmmc-supply = <&vdd_mmc1>; + vqmmc-supply = <&vdd_sd_dv>; +--- a/arch/arm64/boot/dts/ti/k3-am62x-sk-common.dtsi ++++ b/arch/arm64/boot/dts/ti/k3-am62x-sk-common.dtsi +@@ -203,22 +203,6 @@ + >; + }; + +- main_mmc0_pins_default: main-mmc0-default-pins { +- bootph-all; +- pinctrl-single,pins = < +- AM62X_IOPAD(0x220, PIN_INPUT, 0) /* (Y3/V3) MMC0_CMD */ +- AM62X_IOPAD(0x218, PIN_INPUT, 0) /* (AB1/Y1) MMC0_CLK */ +- AM62X_IOPAD(0x214, PIN_INPUT, 0) /* (AA2/V2) MMC0_DAT0 */ +- AM62X_IOPAD(0x210, PIN_INPUT, 0) /* (AA1/V1) MMC0_DAT1 */ +- AM62X_IOPAD(0x20c, PIN_INPUT, 0) /* (AA3/W2) MMC0_DAT2 */ +- AM62X_IOPAD(0x208, PIN_INPUT, 0) /* (Y4/W1) MMC0_DAT3 */ +- AM62X_IOPAD(0x204, PIN_INPUT, 0) /* (AB2/Y2) MMC0_DAT4 */ +- AM62X_IOPAD(0x200, PIN_INPUT, 0) /* (AC1/W3) MMC0_DAT5 */ +- AM62X_IOPAD(0x1fc, PIN_INPUT, 0) /* (AD2/W4) MMC0_DAT6 */ +- AM62X_IOPAD(0x1f8, PIN_INPUT, 0) /* (AC2/V4) MMC0_DAT7 */ +- >; +- }; +- + main_mmc1_pins_default: main-mmc1-default-pins { + bootph-all; + pinctrl-single,pins = < +@@ -457,14 +441,6 @@ + clock-frequency = <400000>; + }; + +-&sdhci0 { +- bootph-all; +- status = "okay"; +- non-removable; +- pinctrl-names = "default"; +- pinctrl-0 = <&main_mmc0_pins_default>; +-}; +- + &sdhci1 { + /* SD/MMC */ + bootph-all; diff --git a/queue-6.16/arm64-dts-ti-k3-am62-verdin-enable-pull-ups-on-i2c-buses.patch b/queue-6.16/arm64-dts-ti-k3-am62-verdin-enable-pull-ups-on-i2c-buses.patch new file mode 100644 index 0000000000..c0e12e1fdf --- /dev/null +++ b/queue-6.16/arm64-dts-ti-k3-am62-verdin-enable-pull-ups-on-i2c-buses.patch @@ -0,0 +1,58 @@ +From bdf4252f736cc1d2a8e3e633c70fe6c728f0756e Mon Sep 17 00:00:00 2001 +From: Emanuele Ghidoli +Date: Wed, 28 May 2025 13:07:37 +0200 +Subject: arm64: dts: ti: k3-am62-verdin: Enable pull-ups on I2C buses + +From: Emanuele Ghidoli + +commit bdf4252f736cc1d2a8e3e633c70fe6c728f0756e upstream. + +Enable internal bias pull-ups on the SoC-side I2C buses that do not have +external pull resistors populated on the SoM. This ensures proper +default line levels. + +Cc: stable@vger.kernel.org +Fixes: 316b80246b16 ("arm64: dts: ti: add verdin am62") +Signed-off-by: Emanuele Ghidoli +Reviewed-by: Francesco Dolcini +Link: https://lore.kernel.org/r/20250528110741.262336-1-ghidoliemanuele@gmail.com +Signed-off-by: Vignesh Raghavendra +Signed-off-by: Greg Kroah-Hartman +--- + arch/arm64/boot/dts/ti/k3-am62-verdin.dtsi | 12 ++++++------ + 1 file changed, 6 insertions(+), 6 deletions(-) + +--- a/arch/arm64/boot/dts/ti/k3-am62-verdin.dtsi ++++ b/arch/arm64/boot/dts/ti/k3-am62-verdin.dtsi +@@ -507,16 +507,16 @@ + /* Verdin I2C_2_DSI */ + pinctrl_i2c2: main-i2c2-default-pins { + pinctrl-single,pins = < +- AM62X_IOPAD(0x00b0, PIN_INPUT, 1) /* (K22) GPMC0_CSn2.I2C2_SCL */ /* SODIMM 55 */ +- AM62X_IOPAD(0x00b4, PIN_INPUT, 1) /* (K24) GPMC0_CSn3.I2C2_SDA */ /* SODIMM 53 */ ++ AM62X_IOPAD(0x00b0, PIN_INPUT_PULLUP, 1) /* (K22) GPMC0_CSn2.I2C2_SCL */ /* SODIMM 55 */ ++ AM62X_IOPAD(0x00b4, PIN_INPUT_PULLUP, 1) /* (K24) GPMC0_CSn3.I2C2_SDA */ /* SODIMM 53 */ + >; + }; + + /* Verdin I2C_4_CSI */ + pinctrl_i2c3: main-i2c3-default-pins { + pinctrl-single,pins = < +- AM62X_IOPAD(0x01d0, PIN_INPUT, 2) /* (A15) UART0_CTSn.I2C3_SCL */ /* SODIMM 95 */ +- AM62X_IOPAD(0x01d4, PIN_INPUT, 2) /* (B15) UART0_RTSn.I2C3_SDA */ /* SODIMM 93 */ ++ AM62X_IOPAD(0x01d0, PIN_INPUT_PULLUP, 2) /* (A15) UART0_CTSn.I2C3_SCL */ /* SODIMM 95 */ ++ AM62X_IOPAD(0x01d4, PIN_INPUT_PULLUP, 2) /* (B15) UART0_RTSn.I2C3_SDA */ /* SODIMM 93 */ + >; + }; + +@@ -786,8 +786,8 @@ + /* Verdin I2C_3_HDMI */ + pinctrl_mcu_i2c0: mcu-i2c0-default-pins { + pinctrl-single,pins = < +- AM62X_MCU_IOPAD(0x0044, PIN_INPUT, 0) /* (A8) MCU_I2C0_SCL */ /* SODIMM 59 */ +- AM62X_MCU_IOPAD(0x0048, PIN_INPUT, 0) /* (D10) MCU_I2C0_SDA */ /* SODIMM 57 */ ++ AM62X_MCU_IOPAD(0x0044, PIN_INPUT_PULLUP, 0) /* (A8) MCU_I2C0_SCL */ /* SODIMM 59 */ ++ AM62X_MCU_IOPAD(0x0048, PIN_INPUT_PULLUP, 0) /* (D10) MCU_I2C0_SDA */ /* SODIMM 57 */ + >; + }; + diff --git a/queue-6.16/arm64-dts-ti-k3-am62a7-sk-fix-pinmux-for-main_uart1.patch b/queue-6.16/arm64-dts-ti-k3-am62a7-sk-fix-pinmux-for-main_uart1.patch new file mode 100644 index 0000000000..9149491079 --- /dev/null +++ b/queue-6.16/arm64-dts-ti-k3-am62a7-sk-fix-pinmux-for-main_uart1.patch @@ -0,0 +1,38 @@ +From 8e44ac61abaae56fc6eb537a04ed78b458c5b984 Mon Sep 17 00:00:00 2001 +From: Hong Guan +Date: Mon, 7 Jul 2025 11:55:13 -0500 +Subject: arm64: dts: ti: k3-am62a7-sk: fix pinmux for main_uart1 + +From: Hong Guan + +commit 8e44ac61abaae56fc6eb537a04ed78b458c5b984 upstream. + +main_uart1 reserved for TIFS firmware traces is routed to the +onboard FT4232 via a FET switch which is connected to pin A21 and +B21 of the SoC and not E17 and C17. Fix it. + +Fixes: cf39ff15cc01a ("arm64: dts: ti: k3-am62a7-sk: Describe main_uart1 and wkup_uart") +Cc: stable@vger.kernel.org +Signed-off-by: Hong Guan +[bb@ti.com: expanded commit message] +Signed-off-by: Bryan Brattlof +Link: https://lore.kernel.org/r/20250707-uart-fixes-v1-1-8164147218b0@ti.com +Signed-off-by: Vignesh Raghavendra +Signed-off-by: Greg Kroah-Hartman +--- + arch/arm64/boot/dts/ti/k3-am62a7-sk.dts | 4 ++-- + 1 file changed, 2 insertions(+), 2 deletions(-) + +--- a/arch/arm64/boot/dts/ti/k3-am62a7-sk.dts ++++ b/arch/arm64/boot/dts/ti/k3-am62a7-sk.dts +@@ -301,8 +301,8 @@ + + main_uart1_pins_default: main-uart1-default-pins { + pinctrl-single,pins = < +- AM62AX_IOPAD(0x01e8, PIN_INPUT, 1) /* (C17) I2C1_SCL.UART1_RXD */ +- AM62AX_IOPAD(0x01ec, PIN_OUTPUT, 1) /* (E17) I2C1_SDA.UART1_TXD */ ++ AM62AX_IOPAD(0x01ac, PIN_INPUT, 2) /* (B21) MCASP0_AFSR.UART1_RXD */ ++ AM62AX_IOPAD(0x01b0, PIN_OUTPUT, 2) /* (A21) MCASP0_ACLKR.UART1_TXD */ + AM62AX_IOPAD(0x0194, PIN_INPUT, 2) /* (C19) MCASP0_AXR3.UART1_CTSn */ + AM62AX_IOPAD(0x0198, PIN_OUTPUT, 2) /* (B19) MCASP0_AXR2.UART1_RTSn */ + >; diff --git a/queue-6.16/arm64-dts-ti-k3-pinctrl-enable-schmitt-trigger-by-default.patch b/queue-6.16/arm64-dts-ti-k3-pinctrl-enable-schmitt-trigger-by-default.patch new file mode 100644 index 0000000000..e3e1d82adb --- /dev/null +++ b/queue-6.16/arm64-dts-ti-k3-pinctrl-enable-schmitt-trigger-by-default.patch @@ -0,0 +1,69 @@ +From 5b272127884bded21576a6ddceca13725a351c63 Mon Sep 17 00:00:00 2001 +From: Alexander Sverdlin +Date: Tue, 1 Jul 2025 12:54:35 +0200 +Subject: arm64: dts: ti: k3-pinctrl: Enable Schmitt Trigger by default + +From: Alexander Sverdlin + +commit 5b272127884bded21576a6ddceca13725a351c63 upstream. + +Switch Schmitt Trigger functions for PIN_INPUT* macros by default. This is +HW PoR configuration, the slew rate requirements without ST enabled are +pretty tough for these devices. We've noticed spurious GPIO interrupts even +with noise-free edges but not meeting slew rate requirements (3.3E+6 V/s +for 3.3v LVCMOS). + +It's not obvious why one might want to disable the PoR-enabled ST on any +pin. Just enable it by default. As it's not possible to provide OR-able +macros to disable the ST, shall anyone require it, provide a set of +new macros with _NOST suffix. + +Fixes: fe49f2d776f7 ("arm64: dts: ti: Use local header for pinctrl register values") +Cc: stable@vger.kernel.org +Signed-off-by: Alexander Sverdlin +Link: https://lore.kernel.org/r/20250701105437.3539924-1-alexander.sverdlin@siemens.com +[vigneshr@ti.com: Add Fixes tag] +Signed-off-by: Vignesh Raghavendra +Signed-off-by: Greg Kroah-Hartman +--- + arch/arm64/boot/dts/ti/k3-pinctrl.h | 15 ++++++++++++--- + 1 file changed, 12 insertions(+), 3 deletions(-) + +--- a/arch/arm64/boot/dts/ti/k3-pinctrl.h ++++ b/arch/arm64/boot/dts/ti/k3-pinctrl.h +@@ -8,6 +8,7 @@ + #ifndef DTS_ARM64_TI_K3_PINCTRL_H + #define DTS_ARM64_TI_K3_PINCTRL_H + ++#define ST_EN_SHIFT (14) + #define PULLUDEN_SHIFT (16) + #define PULLTYPESEL_SHIFT (17) + #define RXACTIVE_SHIFT (18) +@@ -19,6 +20,10 @@ + #define DS_PULLUD_EN_SHIFT (27) + #define DS_PULLTYPE_SEL_SHIFT (28) + ++/* Schmitt trigger configuration */ ++#define ST_DISABLE (0 << ST_EN_SHIFT) ++#define ST_ENABLE (1 << ST_EN_SHIFT) ++ + #define PULL_DISABLE (1 << PULLUDEN_SHIFT) + #define PULL_ENABLE (0 << PULLUDEN_SHIFT) + +@@ -32,9 +37,13 @@ + #define PIN_OUTPUT (INPUT_DISABLE | PULL_DISABLE) + #define PIN_OUTPUT_PULLUP (INPUT_DISABLE | PULL_UP) + #define PIN_OUTPUT_PULLDOWN (INPUT_DISABLE | PULL_DOWN) +-#define PIN_INPUT (INPUT_EN | PULL_DISABLE) +-#define PIN_INPUT_PULLUP (INPUT_EN | PULL_UP) +-#define PIN_INPUT_PULLDOWN (INPUT_EN | PULL_DOWN) ++#define PIN_INPUT (INPUT_EN | ST_ENABLE | PULL_DISABLE) ++#define PIN_INPUT_PULLUP (INPUT_EN | ST_ENABLE | PULL_UP) ++#define PIN_INPUT_PULLDOWN (INPUT_EN | ST_ENABLE | PULL_DOWN) ++/* Input configurations with Schmitt Trigger disabled */ ++#define PIN_INPUT_NOST (INPUT_EN | PULL_DISABLE) ++#define PIN_INPUT_PULLUP_NOST (INPUT_EN | PULL_UP) ++#define PIN_INPUT_PULLDOWN_NOST (INPUT_EN | PULL_DOWN) + + #define PIN_DEBOUNCE_DISABLE (0 << DEBOUNCE_SHIFT) + #define PIN_DEBOUNCE_CONF1 (1 << DEBOUNCE_SHIFT) diff --git a/queue-6.16/ata-libata-scsi-fix-ata_to_sense_error-status-handling.patch b/queue-6.16/ata-libata-scsi-fix-ata_to_sense_error-status-handling.patch new file mode 100644 index 0000000000..aec31b6711 --- /dev/null +++ b/queue-6.16/ata-libata-scsi-fix-ata_to_sense_error-status-handling.patch @@ -0,0 +1,90 @@ +From cf3fc037623c54de48d2ec1a1ee686e2d1de2d45 Mon Sep 17 00:00:00 2001 +From: Damien Le Moal +Date: Tue, 29 Jul 2025 18:28:07 +0900 +Subject: ata: libata-scsi: Fix ata_to_sense_error() status handling + +From: Damien Le Moal + +commit cf3fc037623c54de48d2ec1a1ee686e2d1de2d45 upstream. + +Commit 8ae720449fca ("libata: whitespace fixes in ata_to_sense_error()") +inadvertantly added the entry 0x40 (ATA_DRDY) to the stat_table array in +the function ata_to_sense_error(). This entry ties a failed qc which has +a status filed equal to ATA_DRDY to the sense key ILLEGAL REQUEST with +the additional sense code UNALIGNED WRITE COMMAND. This entry will be +used to generate a failed qc sense key and sense code when the qc is +missing sense data and there is no match for the qc error field in the +sense_table array of ata_to_sense_error(). + +As a result, for a failed qc for which we failed to get sense data (e.g. +read log 10h failed if qc is an NCQ command, or REQUEST SENSE EXT +command failed for the non-ncq case, the user very often end up seeing +the completely misleading "unaligned write command" error, even if qc +was not a write command. E.g.: + +sd 0:0:0:0: [sda] tag#12 FAILED Result: hostbyte=DID_OK driverbyte=DRIVER_OK cmd_age=0s +sd 0:0:0:0: [sda] tag#12 Sense Key : Illegal Request [current] +sd 0:0:0:0: [sda] tag#12 Add. Sense: Unaligned write command +sd 0:0:0:0: [sda] tag#12 CDB: Read(10) 28 00 00 00 10 00 00 00 08 00 +I/O error, dev sda, sector 4096 op 0x0:(READ) flags 0x80700 phys_seg 1 prio class 0 + +Fix this by removing the ATA_DRDY entry from the stat_table array so +that we default to always returning ABORTED COMMAND without any +additional sense code, since we do not know any better. The entry 0x08 +(ATA_DRQ) is also removed since signaling ABORTED COMMAND with a parity +error is also misleading (as a parity error would likely be signaled +through a bus error). So for this case, also default to returning +ABORTED COMMAND without any additional sense code. With this, the +previous example error case becomes: + +sd 0:0:0:0: [sda] tag#17 FAILED Result: hostbyte=DID_OK driverbyte=DRIVER_OK cmd_age=0s +sd 0:0:0:0: [sda] tag#17 Sense Key : Aborted Command [current] +sd 0:0:0:0: [sda] tag#17 Add. Sense: No additional sense information +sd 0:0:0:0: [sda] tag#17 CDB: Read(10) 28 00 00 00 10 00 00 00 08 00 +I/O error, dev sda, sector 4096 op 0x0:(READ) flags 0x80700 phys_seg 1 prio class 0 + +Together with these fixes, refactor stat_table to make it more readable +by putting the entries comments in front of the entries and using the +defined status bits macros instead of hardcoded values. + +Reported-by: Lorenz Brun +Reported-by: Brandon Schwartz +Fixes: 8ae720449fca ("libata: whitespace fixes in ata_to_sense_error()") +Cc: stable@vger.kernel.org +Signed-off-by: Damien Le Moal +Reviewed-by: Hannes Reinecke +Reviewed-by: Martin K. Petersen +Signed-off-by: Greg Kroah-Hartman +--- + drivers/ata/libata-scsi.c | 20 ++++++++------------ + 1 file changed, 8 insertions(+), 12 deletions(-) + +--- a/drivers/ata/libata-scsi.c ++++ b/drivers/ata/libata-scsi.c +@@ -859,18 +859,14 @@ static void ata_to_sense_error(u8 drv_st + {0xFF, 0xFF, 0xFF, 0xFF}, // END mark + }; + static const unsigned char stat_table[][4] = { +- /* Must be first because BUSY means no other bits valid */ +- {0x80, ABORTED_COMMAND, 0x47, 0x00}, +- // Busy, fake parity for now +- {0x40, ILLEGAL_REQUEST, 0x21, 0x04}, +- // Device ready, unaligned write command +- {0x20, HARDWARE_ERROR, 0x44, 0x00}, +- // Device fault, internal target failure +- {0x08, ABORTED_COMMAND, 0x47, 0x00}, +- // Timed out in xfer, fake parity for now +- {0x04, RECOVERED_ERROR, 0x11, 0x00}, +- // Recovered ECC error Medium error, recovered +- {0xFF, 0xFF, 0xFF, 0xFF}, // END mark ++ /* Busy: must be first because BUSY means no other bits valid */ ++ { ATA_BUSY, ABORTED_COMMAND, 0x00, 0x00 }, ++ /* Device fault: INTERNAL TARGET FAILURE */ ++ { ATA_DF, HARDWARE_ERROR, 0x44, 0x00 }, ++ /* Corrected data error */ ++ { ATA_CORR, RECOVERED_ERROR, 0x00, 0x00 }, ++ ++ { 0xFF, 0xFF, 0xFF, 0xFF }, /* END mark */ + }; + + /* diff --git a/queue-6.16/ata-libata-scsi-fix-cdl-control.patch b/queue-6.16/ata-libata-scsi-fix-cdl-control.patch new file mode 100644 index 0000000000..7b4158f489 --- /dev/null +++ b/queue-6.16/ata-libata-scsi-fix-cdl-control.patch @@ -0,0 +1,62 @@ +From 58768b0563916ddcb73d8ed26ede664915f8df31 Mon Sep 17 00:00:00 2001 +From: Igor Pylypiv +Date: Wed, 13 Aug 2025 19:22:56 -0700 +Subject: ata: libata-scsi: Fix CDL control + +From: Igor Pylypiv + +commit 58768b0563916ddcb73d8ed26ede664915f8df31 upstream. + +Delete extra checks for the ATA_DFLAG_CDL_ENABLED flag that prevent +SET FEATURES command from being issued to a drive when NCQ commands +are active. + +ata_mselect_control_ata_feature() sets / clears the ATA_DFLAG_CDL_ENABLED +flag during the translation of MODE SELECT to SET FEATURES. If SET FEATURES +gets deferred due to outstanding NCQ commands, the original MODE SELECT +command will be re-queued. When the re-queued MODE SELECT goes through +the ata_mselect_control_ata_feature() translation again, SET FEATURES +will not be issued because ATA_DFLAG_CDL_ENABLED has been already set or +cleared by the initial translation of MODE SELECT. + +The ATA_DFLAG_CDL_ENABLED checks in ata_mselect_control_ata_feature() +are safe to remove because scsi_cdl_enable() implements a similar logic +that avoids enabling CDL if it has been enabled already. + +Fixes: 17e897a45675 ("ata: libata-scsi: Improve CDL control") +Cc: stable@vger.kernel.org +Signed-off-by: Igor Pylypiv +Reviewed-by: Niklas Cassel +Signed-off-by: Damien Le Moal +Signed-off-by: Greg Kroah-Hartman +--- + drivers/ata/libata-scsi.c | 11 +++-------- + 1 file changed, 3 insertions(+), 8 deletions(-) + +--- a/drivers/ata/libata-scsi.c ++++ b/drivers/ata/libata-scsi.c +@@ -3905,21 +3905,16 @@ static int ata_mselect_control_ata_featu + /* Check cdl_ctrl */ + switch (buf[0] & 0x03) { + case 0: +- /* Disable CDL if it is enabled */ +- if (!(dev->flags & ATA_DFLAG_CDL_ENABLED)) +- return 0; ++ /* Disable CDL */ + ata_dev_dbg(dev, "Disabling CDL\n"); + cdl_action = 0; + dev->flags &= ~ATA_DFLAG_CDL_ENABLED; + break; + case 0x02: + /* +- * Enable CDL if not already enabled. Since this is mutually +- * exclusive with NCQ priority, allow this only if NCQ priority +- * is disabled. ++ * Enable CDL. Since CDL is mutually exclusive with NCQ ++ * priority, allow this only if NCQ priority is disabled. + */ +- if (dev->flags & ATA_DFLAG_CDL_ENABLED) +- return 0; + if (dev->flags & ATA_DFLAG_NCQ_PRIO_ENABLED) { + ata_dev_err(dev, + "NCQ priority must be disabled to enable CDL\n"); diff --git a/queue-6.16/ata-libata-scsi-return-aborted-command-when-missing-sense-and-result-tf.patch b/queue-6.16/ata-libata-scsi-return-aborted-command-when-missing-sense-and-result-tf.patch new file mode 100644 index 0000000000..85e81b2135 --- /dev/null +++ b/queue-6.16/ata-libata-scsi-return-aborted-command-when-missing-sense-and-result-tf.patch @@ -0,0 +1,73 @@ +From d2be9ea9a75550a35c5127a6c2633658bc38c76b Mon Sep 17 00:00:00 2001 +From: Damien Le Moal +Date: Tue, 29 Jul 2025 19:37:12 +0900 +Subject: ata: libata-scsi: Return aborted command when missing sense and result TF + +From: Damien Le Moal + +commit d2be9ea9a75550a35c5127a6c2633658bc38c76b upstream. + +ata_gen_ata_sense() is always called for a failed qc missing sense data +so that a sense key, code and code qualifier can be generated using +ata_to_sense_error() from the qc status and error fields of its result +task file. However, if the qc does not have its result task file filled, +ata_gen_ata_sense() returns early without setting a sense key. + +Improve this by defaulting to returning ABORTED COMMAND without any +additional sense code, since we do not know the reason for the failure. +The same fix is also applied in ata_gen_passthru_sense() with the +additional check that the qc failed (qc->err_mask is set). + +Fixes: 816be86c7993 ("ata: libata-scsi: Check ATA_QCFLAG_RTF_FILLED before using result_tf") +Cc: stable@vger.kernel.org +Signed-off-by: Damien Le Moal +Reviewed-by: Hannes Reinecke +Reviewed-by: Martin K. Petersen +Signed-off-by: Greg Kroah-Hartman +--- + drivers/ata/libata-scsi.c | 18 +++++++++++------- + 1 file changed, 11 insertions(+), 7 deletions(-) + +--- a/drivers/ata/libata-scsi.c ++++ b/drivers/ata/libata-scsi.c +@@ -938,6 +938,8 @@ static void ata_gen_passthru_sense(struc + if (!(qc->flags & ATA_QCFLAG_RTF_FILLED)) { + ata_dev_dbg(dev, + "missing result TF: can't generate ATA PT sense data\n"); ++ if (qc->err_mask) ++ ata_scsi_set_sense(dev, cmd, ABORTED_COMMAND, 0, 0); + return; + } + +@@ -992,8 +994,8 @@ static void ata_gen_ata_sense(struct ata + + if (!(qc->flags & ATA_QCFLAG_RTF_FILLED)) { + ata_dev_dbg(dev, +- "missing result TF: can't generate sense data\n"); +- return; ++ "Missing result TF: reporting aborted command\n"); ++ goto aborted; + } + + /* Use ata_to_sense_error() to map status register bits +@@ -1004,13 +1006,15 @@ static void ata_gen_ata_sense(struct ata + ata_to_sense_error(tf->status, tf->error, + &sense_key, &asc, &ascq); + ata_scsi_set_sense(dev, cmd, sense_key, asc, ascq); +- } else { +- /* Could not decode error */ +- ata_dev_warn(dev, "could not decode error status 0x%x err_mask 0x%x\n", +- tf->status, qc->err_mask); +- ata_scsi_set_sense(dev, cmd, ABORTED_COMMAND, 0, 0); + return; + } ++ ++ /* Could not decode error */ ++ ata_dev_warn(dev, ++ "Could not decode error 0x%x, status 0x%x (err_mask=0x%x)\n", ++ tf->error, tf->status, qc->err_mask); ++aborted: ++ ata_scsi_set_sense(dev, cmd, ABORTED_COMMAND, 0, 0); + } + + void ata_scsi_sdev_config(struct scsi_device *sdev) diff --git a/queue-6.16/dt-bindings-display-sprd-sharkl3-dpu-fix-missing-clocks-constraints.patch b/queue-6.16/dt-bindings-display-sprd-sharkl3-dpu-fix-missing-clocks-constraints.patch new file mode 100644 index 0000000000..5938139a18 --- /dev/null +++ b/queue-6.16/dt-bindings-display-sprd-sharkl3-dpu-fix-missing-clocks-constraints.patch @@ -0,0 +1,34 @@ +From 934da599e694d476f493d3927a30414e98a81561 Mon Sep 17 00:00:00 2001 +From: Krzysztof Kozlowski +Date: Sun, 20 Jul 2025 14:30:04 +0200 +Subject: dt-bindings: display: sprd,sharkl3-dpu: Fix missing clocks constraints + +From: Krzysztof Kozlowski + +commit 934da599e694d476f493d3927a30414e98a81561 upstream. + +'minItems' alone does not impose upper bound, unlike 'maxItems' which +implies lower bound. Add missing clock constraint so the list will have +exact number of items (clocks). + +Fixes: 8cae15c60cf0 ("dt-bindings: display: add Unisoc's dpu bindings") +Cc: stable@vger.kernel.org +Signed-off-by: Krzysztof Kozlowski +Link: https://lore.kernel.org/r/20250720123003.37662-3-krzysztof.kozlowski@linaro.org +Signed-off-by: Rob Herring (Arm) +Signed-off-by: Greg Kroah-Hartman +--- + Documentation/devicetree/bindings/display/sprd/sprd,sharkl3-dpu.yaml | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +--- a/Documentation/devicetree/bindings/display/sprd/sprd,sharkl3-dpu.yaml ++++ b/Documentation/devicetree/bindings/display/sprd/sprd,sharkl3-dpu.yaml +@@ -25,7 +25,7 @@ properties: + maxItems: 1 + + clocks: +- minItems: 2 ++ maxItems: 2 + + clock-names: + items: diff --git a/queue-6.16/dt-bindings-display-sprd-sharkl3-dsi-host-fix-missing-clocks-constraints.patch b/queue-6.16/dt-bindings-display-sprd-sharkl3-dsi-host-fix-missing-clocks-constraints.patch new file mode 100644 index 0000000000..1c3f0ddaf9 --- /dev/null +++ b/queue-6.16/dt-bindings-display-sprd-sharkl3-dsi-host-fix-missing-clocks-constraints.patch @@ -0,0 +1,34 @@ +From 2558df8c13ae3bd6c303b28f240ceb0189519c91 Mon Sep 17 00:00:00 2001 +From: Krzysztof Kozlowski +Date: Sun, 20 Jul 2025 14:30:05 +0200 +Subject: dt-bindings: display: sprd,sharkl3-dsi-host: Fix missing clocks constraints + +From: Krzysztof Kozlowski + +commit 2558df8c13ae3bd6c303b28f240ceb0189519c91 upstream. + +'minItems' alone does not impose upper bound, unlike 'maxItems' which +implies lower bound. Add missing clock constraint so the list will have +exact number of items (clocks). + +Fixes: 2295bbd35edb ("dt-bindings: display: add Unisoc's mipi dsi controller bindings") +Cc: stable@vger.kernel.org +Signed-off-by: Krzysztof Kozlowski +Link: https://lore.kernel.org/r/20250720123003.37662-4-krzysztof.kozlowski@linaro.org +Signed-off-by: Rob Herring (Arm) +Signed-off-by: Greg Kroah-Hartman +--- + Documentation/devicetree/bindings/display/sprd/sprd,sharkl3-dsi-host.yaml | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +--- a/Documentation/devicetree/bindings/display/sprd/sprd,sharkl3-dsi-host.yaml ++++ b/Documentation/devicetree/bindings/display/sprd/sprd,sharkl3-dsi-host.yaml +@@ -20,7 +20,7 @@ properties: + maxItems: 2 + + clocks: +- minItems: 1 ++ maxItems: 1 + + clock-names: + items: diff --git a/queue-6.16/dt-bindings-display-vop2-add-optional-pll-clock-property-for-rk3576.patch b/queue-6.16/dt-bindings-display-vop2-add-optional-pll-clock-property-for-rk3576.patch new file mode 100644 index 0000000000..d0bcfc3fde --- /dev/null +++ b/queue-6.16/dt-bindings-display-vop2-add-optional-pll-clock-property-for-rk3576.patch @@ -0,0 +1,121 @@ +From 3832dc42aed9b047ccecebf5917d008bd2dac940 Mon Sep 17 00:00:00 2001 +From: Cristian Ciocaltea +Date: Thu, 12 Jun 2025 00:47:47 +0300 +Subject: dt-bindings: display: vop2: Add optional PLL clock property for rk3576 + +From: Cristian Ciocaltea + +commit 3832dc42aed9b047ccecebf5917d008bd2dac940 upstream. + +As with the RK3588 SoC, RK3576 also allows the use of HDMI PHY PLL as an +alternative and more accurate pixel clock source for VOP2. + +Document the optional PLL clock property. + +Moreover, given that this is part of a series intended to address some +recent display problems, provide the appropriate tags to facilitate +backporting. + +Fixes: c3b7c5a4d7c1 ("dt-bindings: display: vop2: Add rk3576 support") +Cc: stable@vger.kernel.org +Signed-off-by: Cristian Ciocaltea +Reviewed-by: "Rob Herring (Arm)" +Tested-by: Nicolas Frattaroli +Signed-off-by: Heiko Stuebner +Link: https://lore.kernel.org/r/20250612-rk3576-hdmitx-fix-v1-1-4b11007d8675@collabora.com +Signed-off-by: Greg Kroah-Hartman +--- + Documentation/devicetree/bindings/display/rockchip/rockchip-vop2.yaml | 56 +++++++--- + 1 file changed, 44 insertions(+), 12 deletions(-) + +--- a/Documentation/devicetree/bindings/display/rockchip/rockchip-vop2.yaml ++++ b/Documentation/devicetree/bindings/display/rockchip/rockchip-vop2.yaml +@@ -64,10 +64,10 @@ properties: + - description: Pixel clock for video port 0. + - description: Pixel clock for video port 1. + - description: Pixel clock for video port 2. +- - description: Pixel clock for video port 3. +- - description: Peripheral(vop grf/dsi) clock. +- - description: Alternative pixel clock provided by HDMI0 PHY PLL. +- - description: Alternative pixel clock provided by HDMI1 PHY PLL. ++ - {} ++ - {} ++ - {} ++ - {} + + clock-names: + minItems: 5 +@@ -77,10 +77,10 @@ properties: + - const: dclk_vp0 + - const: dclk_vp1 + - const: dclk_vp2 +- - const: dclk_vp3 +- - const: pclk_vop +- - const: pll_hdmiphy0 +- - const: pll_hdmiphy1 ++ - {} ++ - {} ++ - {} ++ - {} + + rockchip,grf: + $ref: /schemas/types.yaml#/definitions/phandle +@@ -175,10 +175,24 @@ allOf: + then: + properties: + clocks: +- maxItems: 5 ++ minItems: 5 ++ items: ++ - {} ++ - {} ++ - {} ++ - {} ++ - {} ++ - description: Alternative pixel clock provided by HDMI PHY PLL. + + clock-names: +- maxItems: 5 ++ minItems: 5 ++ items: ++ - {} ++ - {} ++ - {} ++ - {} ++ - {} ++ - const: pll_hdmiphy0 + + interrupts: + minItems: 4 +@@ -208,11 +222,29 @@ allOf: + properties: + clocks: + minItems: 7 +- maxItems: 9 ++ items: ++ - {} ++ - {} ++ - {} ++ - {} ++ - {} ++ - description: Pixel clock for video port 3. ++ - description: Peripheral(vop grf/dsi) clock. ++ - description: Alternative pixel clock provided by HDMI0 PHY PLL. ++ - description: Alternative pixel clock provided by HDMI1 PHY PLL. + + clock-names: + minItems: 7 +- maxItems: 9 ++ items: ++ - {} ++ - {} ++ - {} ++ - {} ++ - {} ++ - const: dclk_vp3 ++ - const: pclk_vop ++ - const: pll_hdmiphy0 ++ - const: pll_hdmiphy1 + + interrupts: + maxItems: 1 diff --git a/queue-6.16/scsi-dt-bindings-mediatek-ufs-add-ufs-disable-mcq-flag-for-ufs-host.patch b/queue-6.16/scsi-dt-bindings-mediatek-ufs-add-ufs-disable-mcq-flag-for-ufs-host.patch new file mode 100644 index 0000000000..c8e56cbbe6 --- /dev/null +++ b/queue-6.16/scsi-dt-bindings-mediatek-ufs-add-ufs-disable-mcq-flag-for-ufs-host.patch @@ -0,0 +1,40 @@ +From 794ff7a0a6e76af93c5ec09a49b86fe73373ca59 Mon Sep 17 00:00:00 2001 +From: Macpaul Lin +Date: Tue, 22 Jul 2025 16:57:18 +0800 +Subject: scsi: dt-bindings: mediatek,ufs: Add ufs-disable-mcq flag for UFS host + +From: Macpaul Lin + +commit 794ff7a0a6e76af93c5ec09a49b86fe73373ca59 upstream. + +Add the 'mediatek,ufs-disable-mcq' property to the UFS device-tree +bindings. This flag corresponds to the UFS_MTK_CAP_DISABLE_MCQ host +capability recently introduced in the UFS host driver, allowing it to +disable the Multiple Circular Queue (MCQ) feature when present. The +binding schema has also been updated to resolve DTBS check errors. + +Cc: stable@vger.kernel.org +Fixes: 46bd3e31d74b ("scsi: ufs: mediatek: Add UFS_MTK_CAP_DISABLE_MCQ") +Signed-off-by: Macpaul Lin +Link: https://lore.kernel.org/r/20250722085721.2062657-2-macpaul.lin@mediatek.com +Reviewed-by: Rob Herring (Arm) +Reviewed-by: Peter Wang +Signed-off-by: Martin K. Petersen +Signed-off-by: Greg Kroah-Hartman +--- + Documentation/devicetree/bindings/ufs/mediatek,ufs.yaml | 4 ++++ + 1 file changed, 4 insertions(+) + +--- a/Documentation/devicetree/bindings/ufs/mediatek,ufs.yaml ++++ b/Documentation/devicetree/bindings/ufs/mediatek,ufs.yaml +@@ -33,6 +33,10 @@ properties: + + vcc-supply: true + ++ mediatek,ufs-disable-mcq: ++ $ref: /schemas/types.yaml#/definitions/flag ++ description: The mask to disable MCQ (Multi-Circular Queue) for UFS host. ++ + required: + - compatible + - clocks diff --git a/queue-6.16/scsi-mpi3mr-fix-race-between-config-read-submit-and-interrupt-completion.patch b/queue-6.16/scsi-mpi3mr-fix-race-between-config-read-submit-and-interrupt-completion.patch new file mode 100644 index 0000000000..8f73ffd8cd --- /dev/null +++ b/queue-6.16/scsi-mpi3mr-fix-race-between-config-read-submit-and-interrupt-completion.patch @@ -0,0 +1,40 @@ +From e6327c4acf925bb6d6d387d76fc3bd94471e10d8 Mon Sep 17 00:00:00 2001 +From: Ranjan Kumar +Date: Sat, 28 Jun 2025 01:15:36 +0530 +Subject: scsi: mpi3mr: Fix race between config read submit and interrupt completion + +From: Ranjan Kumar + +commit e6327c4acf925bb6d6d387d76fc3bd94471e10d8 upstream. + +The "is_waiting" flag was updated after calling complete(), which could +lead to a race where the waiting thread wakes up before the flag is +cleared. This may cause a missed wakeup or stale state check. + +Reorder the operations to update "is_waiting" before signaling completion +to ensure consistent state. + +Fixes: 824a156633df ("scsi: mpi3mr: Base driver code") +Cc: stable@vger.kernel.org +Co-developed-by: Chandrakanth Patil +Signed-off-by: Chandrakanth Patil +Signed-off-by: Ranjan Kumar +Link: https://lore.kernel.org/r/20250627194539.48851-2-ranjan.kumar@broadcom.com +Signed-off-by: Martin K. Petersen +Signed-off-by: Greg Kroah-Hartman +--- + drivers/scsi/mpi3mr/mpi3mr_fw.c | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +--- a/drivers/scsi/mpi3mr/mpi3mr_fw.c ++++ b/drivers/scsi/mpi3mr/mpi3mr_fw.c +@@ -428,8 +428,8 @@ static void mpi3mr_process_admin_reply_d + MPI3MR_SENSE_BUF_SZ); + } + if (cmdptr->is_waiting) { +- complete(&cmdptr->done); + cmdptr->is_waiting = 0; ++ complete(&cmdptr->done); + } else if (cmdptr->callback) + cmdptr->callback(mrioc, cmdptr); + } diff --git a/queue-6.16/scsi-ufs-exynos-fix-programming-of-hci_utrl_nexus_type.patch b/queue-6.16/scsi-ufs-exynos-fix-programming-of-hci_utrl_nexus_type.patch new file mode 100644 index 0000000000..224ebb18e5 --- /dev/null +++ b/queue-6.16/scsi-ufs-exynos-fix-programming-of-hci_utrl_nexus_type.patch @@ -0,0 +1,56 @@ +From 01aad16c2257ab8ff33b152b972c9f2e1af47912 Mon Sep 17 00:00:00 2001 +From: =?UTF-8?q?Andr=C3=A9=20Draszik?= +Date: Mon, 7 Jul 2025 18:05:27 +0100 +Subject: scsi: ufs: exynos: Fix programming of HCI_UTRL_NEXUS_TYPE +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +From: André Draszik + +commit 01aad16c2257ab8ff33b152b972c9f2e1af47912 upstream. + +On Google gs101, the number of UTP transfer request slots (nutrs) is 32, +and in this case the driver ends up programming the UTRL_NEXUS_TYPE +incorrectly as 0. + +This is because the left hand side of the shift is 1, which is of type +int, i.e. 31 bits wide. Shifting by more than that width results in +undefined behaviour. + +Fix this by switching to the BIT() macro, which applies correct type +casting as required. This ensures the correct value is written to +UTRL_NEXUS_TYPE (0xffffffff on gs101), and it also fixes a UBSAN shift +warning: + + UBSAN: shift-out-of-bounds in drivers/ufs/host/ufs-exynos.c:1113:21 + shift exponent 32 is too large for 32-bit type 'int' + +For consistency, apply the same change to the nutmrs / UTMRL_NEXUS_TYPE +write. + +Fixes: 55f4b1f73631 ("scsi: ufs: ufs-exynos: Add UFS host support for Exynos SoCs") +Cc: stable@vger.kernel.org +Signed-off-by: André Draszik +Link: https://lore.kernel.org/r/20250707-ufs-exynos-shift-v1-1-1418e161ae40@linaro.org +Reviewed-by: Bart Van Assche +Reviewed-by: Peter Griffin +Signed-off-by: Martin K. Petersen +Signed-off-by: Greg Kroah-Hartman +--- + drivers/ufs/host/ufs-exynos.c | 4 ++-- + 1 file changed, 2 insertions(+), 2 deletions(-) + +--- a/drivers/ufs/host/ufs-exynos.c ++++ b/drivers/ufs/host/ufs-exynos.c +@@ -1110,8 +1110,8 @@ static int exynos_ufs_post_link(struct u + hci_writel(ufs, val, HCI_TXPRDT_ENTRY_SIZE); + + hci_writel(ufs, ilog2(DATA_UNIT_SIZE), HCI_RXPRDT_ENTRY_SIZE); +- hci_writel(ufs, (1 << hba->nutrs) - 1, HCI_UTRL_NEXUS_TYPE); +- hci_writel(ufs, (1 << hba->nutmrs) - 1, HCI_UTMRL_NEXUS_TYPE); ++ hci_writel(ufs, BIT(hba->nutrs) - 1, HCI_UTRL_NEXUS_TYPE); ++ hci_writel(ufs, BIT(hba->nutmrs) - 1, HCI_UTMRL_NEXUS_TYPE); + hci_writel(ufs, 0xf, HCI_AXIDMA_RWDATA_BURST_LEN); + + if (ufs->opts & EXYNOS_UFS_OPT_SKIP_CONNECTION_ESTAB) diff --git a/queue-6.16/scsi-ufs-ufs-pci-fix-default-runtime-and-system-pm-levels.patch b/queue-6.16/scsi-ufs-ufs-pci-fix-default-runtime-and-system-pm-levels.patch new file mode 100644 index 0000000000..07da79537b --- /dev/null +++ b/queue-6.16/scsi-ufs-ufs-pci-fix-default-runtime-and-system-pm-levels.patch @@ -0,0 +1,62 @@ +From 6de7435e6b81fe52c0ab4c7e181f6b5decd18eb1 Mon Sep 17 00:00:00 2001 +From: Adrian Hunter +Date: Wed, 23 Jul 2025 19:58:50 +0300 +Subject: scsi: ufs: ufs-pci: Fix default runtime and system PM levels + +From: Adrian Hunter + +commit 6de7435e6b81fe52c0ab4c7e181f6b5decd18eb1 upstream. + +Intel MTL-like host controllers support auto-hibernate. Using +auto-hibernate with manual (driver initiated) hibernate produces more +complex operation. For example, the host controller will have to exit +auto-hibernate simply to allow the driver to enter hibernate state +manually. That is not recommended. + +The default rpm_lvl and spm_lvl is 3, which includes manual hibernate. + +Change the default values to 2, which does not. + +Note, to be simpler to backport to stable kernels, utilize the UFS PCI +driver's ->late_init() call back. Recent commits have made it possible +to set up a controller-specific default in the regular ->init() call +back, but not all stable kernels have those changes. + +Fixes: 4049f7acef3e ("scsi: ufs: ufs-pci: Add support for Intel MTL") +Cc: stable@vger.kernel.org +Signed-off-by: Adrian Hunter +Link: https://lore.kernel.org/r/20250723165856.145750-3-adrian.hunter@intel.com +Reviewed-by: Bart Van Assche +Signed-off-by: Martin K. Petersen +Signed-off-by: Greg Kroah-Hartman +--- + drivers/ufs/host/ufshcd-pci.c | 15 ++++++++++++++- + 1 file changed, 14 insertions(+), 1 deletion(-) + +--- a/drivers/ufs/host/ufshcd-pci.c ++++ b/drivers/ufs/host/ufshcd-pci.c +@@ -468,10 +468,23 @@ static int ufs_intel_adl_init(struct ufs + return ufs_intel_common_init(hba); + } + ++static void ufs_intel_mtl_late_init(struct ufs_hba *hba) ++{ ++ hba->rpm_lvl = UFS_PM_LVL_2; ++ hba->spm_lvl = UFS_PM_LVL_2; ++} ++ + static int ufs_intel_mtl_init(struct ufs_hba *hba) + { ++ struct ufs_host *ufs_host; ++ int err; ++ + hba->caps |= UFSHCD_CAP_CRYPTO | UFSHCD_CAP_WB_EN; +- return ufs_intel_common_init(hba); ++ err = ufs_intel_common_init(hba); ++ /* Get variant after it is set in ufs_intel_common_init() */ ++ ufs_host = ufshcd_get_variant(hba); ++ ufs_host->late_init = ufs_intel_mtl_late_init; ++ return err; + } + + static int ufs_qemu_get_hba_mac(struct ufs_hba *hba) diff --git a/queue-6.16/scsi-ufs-ufs-pci-fix-hibernate-state-transition-for-intel-mtl-like-host-controllers.patch b/queue-6.16/scsi-ufs-ufs-pci-fix-hibernate-state-transition-for-intel-mtl-like-host-controllers.patch new file mode 100644 index 0000000000..9beda38297 --- /dev/null +++ b/queue-6.16/scsi-ufs-ufs-pci-fix-hibernate-state-transition-for-intel-mtl-like-host-controllers.patch @@ -0,0 +1,72 @@ +From 4428ddea832cfdb63e476eb2e5c8feb5d36057fe Mon Sep 17 00:00:00 2001 +From: Archana Patni +Date: Wed, 23 Jul 2025 19:58:49 +0300 +Subject: scsi: ufs: ufs-pci: Fix hibernate state transition for Intel MTL-like host controllers + +From: Archana Patni + +commit 4428ddea832cfdb63e476eb2e5c8feb5d36057fe upstream. + +UFSHCD core disables the UIC completion interrupt when issuing UIC +hibernation commands, and re-enables it afterwards if it was enabled to +start with, refer ufshcd_uic_pwr_ctrl(). For Intel MTL-like host +controllers, accessing the register to re-enable the interrupt disrupts +the state transition. + +Use hibern8_notify variant operation to disable the interrupt during the +entire hibernation, thereby preventing the disruption. + +Fixes: 4049f7acef3e ("scsi: ufs: ufs-pci: Add support for Intel MTL") +Cc: stable@vger.kernel.org +Signed-off-by: Archana Patni +Link: https://lore.kernel.org/r/20250723165856.145750-2-adrian.hunter@intel.com +Reviewed-by: Bart Van Assche +Signed-off-by: Martin K. Petersen +Signed-off-by: Greg Kroah-Hartman +--- + drivers/ufs/host/ufshcd-pci.c | 27 +++++++++++++++++++++++++++ + 1 file changed, 27 insertions(+) + +--- a/drivers/ufs/host/ufshcd-pci.c ++++ b/drivers/ufs/host/ufshcd-pci.c +@@ -216,6 +216,32 @@ out: + return ret; + } + ++static void ufs_intel_ctrl_uic_compl(struct ufs_hba *hba, bool enable) ++{ ++ u32 set = ufshcd_readl(hba, REG_INTERRUPT_ENABLE); ++ ++ if (enable) ++ set |= UIC_COMMAND_COMPL; ++ else ++ set &= ~UIC_COMMAND_COMPL; ++ ufshcd_writel(hba, set, REG_INTERRUPT_ENABLE); ++} ++ ++static void ufs_intel_mtl_h8_notify(struct ufs_hba *hba, ++ enum uic_cmd_dme cmd, ++ enum ufs_notify_change_status status) ++{ ++ /* ++ * Disable UIC COMPL INTR to prevent access to UFSHCI after ++ * checking HCS.UPMCRS ++ */ ++ if (status == PRE_CHANGE && cmd == UIC_CMD_DME_HIBER_ENTER) ++ ufs_intel_ctrl_uic_compl(hba, false); ++ ++ if (status == POST_CHANGE && cmd == UIC_CMD_DME_HIBER_EXIT) ++ ufs_intel_ctrl_uic_compl(hba, true); ++} ++ + #define INTEL_ACTIVELTR 0x804 + #define INTEL_IDLELTR 0x808 + +@@ -533,6 +559,7 @@ static struct ufs_hba_variant_ops ufs_in + .init = ufs_intel_mtl_init, + .exit = ufs_intel_common_exit, + .hce_enable_notify = ufs_intel_hce_enable_notify, ++ .hibern8_notify = ufs_intel_mtl_h8_notify, + .link_startup_notify = ufs_intel_link_startup_notify, + .resume = ufs_intel_resume, + .device_reset = ufs_intel_device_reset, diff --git a/queue-6.16/series b/queue-6.16/series index 248becdd3f..2ac0af3803 100644 --- a/queue-6.16/series +++ b/queue-6.16/series @@ -45,3 +45,28 @@ btrfs-zoned-fix-write-time-activation-failure-for-metadata-block-group.patch btrfs-fix-incorrect-log-message-for-nobarrier-mount-option.patch btrfs-restore-mount-option-info-messages-during-mount.patch btrfs-fix-printing-of-mount-info-messages-for-nodatacow-nodatasum.patch +arm64-dts-apple-t8012-j132-include-touchbar-framebuffer-node.patch +arm64-dts-ti-k3-am62-main-remove-emmc-high-speed-ddr-support.patch +arm64-dts-exynos7870-j6lte-reduce-memory-ranges-to-base-amount.patch +arm64-dts-ti-k3-pinctrl-enable-schmitt-trigger-by-default.patch +arm64-dts-exynos7870-add-quirk-to-disable-usb2-lpm-in-gadget-mode.patch +arm64-dts-rockchip-add-hdmi-phy-pll-clock-source-to-vop2-on-rk3576.patch +arm64-dts-rockchip-enable-hdmi-phy-clk-provider-on-rk3576.patch +arm64-dts-exynos-gs101-ufs-add-dma-coherent-property.patch +arm64-dts-ti-k3-am62a7-sk-fix-pinmux-for-main_uart1.patch +arm64-dts-ti-k3-am62-move-emmc-pinmux-to-top-level-board-file.patch +arm64-dts-exynos7870-on7xelte-reduce-memory-ranges-to-base-amount.patch +arm64-dts-ti-k3-am62-verdin-enable-pull-ups-on-i2c-buses.patch +arm64-dts-rockchip-remove-workaround-that-prevented-turing-rk1-gpu-power-regulator-control.patch +apparmor-fix-8-byte-alignment-for-initial-dfa-blob-streams.patch +dt-bindings-display-sprd-sharkl3-dpu-fix-missing-clocks-constraints.patch +dt-bindings-display-sprd-sharkl3-dsi-host-fix-missing-clocks-constraints.patch +dt-bindings-display-vop2-add-optional-pll-clock-property-for-rk3576.patch +scsi-dt-bindings-mediatek-ufs-add-ufs-disable-mcq-flag-for-ufs-host.patch +scsi-ufs-exynos-fix-programming-of-hci_utrl_nexus_type.patch +scsi-mpi3mr-fix-race-between-config-read-submit-and-interrupt-completion.patch +ata-libata-scsi-fix-ata_to_sense_error-status-handling.patch +ata-libata-scsi-return-aborted-command-when-missing-sense-and-result-tf.patch +scsi-ufs-ufs-pci-fix-hibernate-state-transition-for-intel-mtl-like-host-controllers.patch +scsi-ufs-ufs-pci-fix-default-runtime-and-system-pm-levels.patch +ata-libata-scsi-fix-cdl-control.patch