From: Sasha Levin Date: Thu, 15 Nov 2018 17:38:46 +0000 (-0500) Subject: queue clk-meson-axg-mark-fdiv2-and-fdiv3-as-critical.patch for 4.19 and 4.18 X-Git-Tag: v4.19.3~36 X-Git-Url: http://git.ipfire.org/?a=commitdiff_plain;h=b1e818f4bf55ffa9cf05d14bfa223df35b031963;p=thirdparty%2Fkernel%2Fstable-queue.git queue clk-meson-axg-mark-fdiv2-and-fdiv3-as-critical.patch for 4.19 and 4.18 Signed-off-by: Sasha Levin --- diff --git a/queue-4.18/clk-meson-axg-mark-fdiv2-and-fdiv3-as-critical.patch b/queue-4.18/clk-meson-axg-mark-fdiv2-and-fdiv3-as-critical.patch new file mode 100644 index 00000000000..9426c6810cf --- /dev/null +++ b/queue-4.18/clk-meson-axg-mark-fdiv2-and-fdiv3-as-critical.patch @@ -0,0 +1,59 @@ +From b11111cbc1ab3651f22ed09cb44f538eb8b669b5 Mon Sep 17 00:00:00 2001 +From: Jerome Brunet +Date: Thu, 8 Nov 2018 10:31:23 +0100 +Subject: clk: meson: axg: mark fdiv2 and fdiv3 as critical + +[ Upstream commit d6ee1e7e9004d3d246cdfa14196989e0a9466c16 ] + +Similar to gxbb and gxl platforms, axg SCPI Cortex-M co-processor +uses the fdiv2 and fdiv3 to, among other things, provide the cpu +clock. + +Until clock hand-off mechanism makes its way to CCF and the generic +SCPI claims platform specific clocks, these clocks must be marked as +critical to make sure they are never disabled when needed by the +co-processor. + +Fixes: 05f814402d61 ("clk: meson: add fdiv clock gates") +Signed-off-by: Jerome Brunet +Acked-by: Neil Armstrong +Signed-off-by: Stephen Boyd +Signed-off-by: Sasha Levin +--- + drivers/clk/meson/axg.c | 13 +++++++++++++ + 1 file changed, 13 insertions(+) + +diff --git a/drivers/clk/meson/axg.c b/drivers/clk/meson/axg.c +index bd4dbc696b88..cfd26fd7e404 100644 +--- a/drivers/clk/meson/axg.c ++++ b/drivers/clk/meson/axg.c +@@ -320,6 +320,7 @@ static struct clk_regmap axg_fclk_div2 = { + .ops = &clk_regmap_gate_ops, + .parent_names = (const char *[]){ "fclk_div2_div" }, + .num_parents = 1, ++ .flags = CLK_IS_CRITICAL, + }, + }; + +@@ -344,6 +345,18 @@ static struct clk_regmap axg_fclk_div3 = { + .ops = &clk_regmap_gate_ops, + .parent_names = (const char *[]){ "fclk_div3_div" }, + .num_parents = 1, ++ /* ++ * FIXME: ++ * This clock, as fdiv2, is used by the SCPI FW and is required ++ * by the platform to operate correctly. ++ * Until the following condition are met, we need this clock to ++ * be marked as critical: ++ * a) The SCPI generic driver claims and enable all the clocks ++ * it needs ++ * b) CCF has a clock hand-off mechanism to make the sure the ++ * clock stays on until the proper driver comes along ++ */ ++ .flags = CLK_IS_CRITICAL, + }, + }; + +-- +2.17.1 + diff --git a/queue-4.18/series b/queue-4.18/series index da7f4257c8d..1c9663a4b02 100644 --- a/queue-4.18/series +++ b/queue-4.18/series @@ -52,3 +52,4 @@ scsi-qla2xxx-fix-nvme-session-hang-on-unload.patch arm64-dts-stratix10-support-ethernet-jumbo-frame.patch arm64-dts-stratix10-fix-multicast-filtering.patch clk-meson-gxbb-set-fclk_div3-as-clk_is_critical.patch +clk-meson-axg-mark-fdiv2-and-fdiv3-as-critical.patch diff --git a/queue-4.19/clk-meson-axg-mark-fdiv2-and-fdiv3-as-critical.patch b/queue-4.19/clk-meson-axg-mark-fdiv2-and-fdiv3-as-critical.patch new file mode 100644 index 00000000000..13a16d4a293 --- /dev/null +++ b/queue-4.19/clk-meson-axg-mark-fdiv2-and-fdiv3-as-critical.patch @@ -0,0 +1,59 @@ +From 32347156e41a29ddef5cecf4c61b65b28e206d88 Mon Sep 17 00:00:00 2001 +From: Jerome Brunet +Date: Thu, 8 Nov 2018 10:31:23 +0100 +Subject: clk: meson: axg: mark fdiv2 and fdiv3 as critical + +[ Upstream commit d6ee1e7e9004d3d246cdfa14196989e0a9466c16 ] + +Similar to gxbb and gxl platforms, axg SCPI Cortex-M co-processor +uses the fdiv2 and fdiv3 to, among other things, provide the cpu +clock. + +Until clock hand-off mechanism makes its way to CCF and the generic +SCPI claims platform specific clocks, these clocks must be marked as +critical to make sure they are never disabled when needed by the +co-processor. + +Fixes: 05f814402d61 ("clk: meson: add fdiv clock gates") +Signed-off-by: Jerome Brunet +Acked-by: Neil Armstrong +Signed-off-by: Stephen Boyd +Signed-off-by: Sasha Levin +--- + drivers/clk/meson/axg.c | 13 +++++++++++++ + 1 file changed, 13 insertions(+) + +diff --git a/drivers/clk/meson/axg.c b/drivers/clk/meson/axg.c +index 00ce62ad6416..8cf74fc423e6 100644 +--- a/drivers/clk/meson/axg.c ++++ b/drivers/clk/meson/axg.c +@@ -319,6 +319,7 @@ static struct clk_regmap axg_fclk_div2 = { + .ops = &clk_regmap_gate_ops, + .parent_names = (const char *[]){ "fclk_div2_div" }, + .num_parents = 1, ++ .flags = CLK_IS_CRITICAL, + }, + }; + +@@ -343,6 +344,18 @@ static struct clk_regmap axg_fclk_div3 = { + .ops = &clk_regmap_gate_ops, + .parent_names = (const char *[]){ "fclk_div3_div" }, + .num_parents = 1, ++ /* ++ * FIXME: ++ * This clock, as fdiv2, is used by the SCPI FW and is required ++ * by the platform to operate correctly. ++ * Until the following condition are met, we need this clock to ++ * be marked as critical: ++ * a) The SCPI generic driver claims and enable all the clocks ++ * it needs ++ * b) CCF has a clock hand-off mechanism to make the sure the ++ * clock stays on until the proper driver comes along ++ */ ++ .flags = CLK_IS_CRITICAL, + }, + }; + +-- +2.17.1 + diff --git a/queue-4.19/series b/queue-4.19/series index ad270fe0c05..0a31052209e 100644 --- a/queue-4.19/series +++ b/queue-4.19/series @@ -69,3 +69,4 @@ drm-msm-fix-of-child-node-lookup.patch arm64-dts-stratix10-support-ethernet-jumbo-frame.patch arm64-dts-stratix10-fix-multicast-filtering.patch clk-meson-gxbb-set-fclk_div3-as-clk_is_critical.patch +clk-meson-axg-mark-fdiv2-and-fdiv3-as-critical.patch