From: Greg Kroah-Hartman Date: Wed, 25 Feb 2026 01:18:53 +0000 (-0800) Subject: 6.18-stable patches X-Git-Url: http://git.ipfire.org/?a=commitdiff_plain;h=b21986ed4d52496ce14108c72bb9faf2d65fd2ef;p=thirdparty%2Fkernel%2Fstable-queue.git 6.18-stable patches added patches: net-stmmac-dwmac-loongson-set-clk_csr_i-to-100-150mhz.patch --- diff --git a/queue-6.18/net-stmmac-dwmac-loongson-set-clk_csr_i-to-100-150mhz.patch b/queue-6.18/net-stmmac-dwmac-loongson-set-clk_csr_i-to-100-150mhz.patch new file mode 100644 index 0000000000..d495db9a11 --- /dev/null +++ b/queue-6.18/net-stmmac-dwmac-loongson-set-clk_csr_i-to-100-150mhz.patch @@ -0,0 +1,39 @@ +From e1aa5ef892fb4fa9014a25e87b64b97347919d37 Mon Sep 17 00:00:00 2001 +From: Huacai Chen +Date: Tue, 3 Feb 2026 14:29:01 +0800 +Subject: net: stmmac: dwmac-loongson: Set clk_csr_i to 100-150MHz + +From: Huacai Chen + +commit e1aa5ef892fb4fa9014a25e87b64b97347919d37 upstream. + +Current clk_csr_i setting of Loongson STMMAC (including LS7A1000/2000 +and LS2K1000/2000/3000) are copy & paste from other drivers. In fact, +Loongson STMMAC use 125MHz clocks and need 62 freq division to within +2.5MHz, meeting most PHY MDC requirement. So fix by setting clk_csr_i +to 100-150MHz, otherwise some PHYs may link fail. + +Cc: stable@vger.kernel.org +Fixes: 30bba69d7db40e7 ("stmmac: pci: Add dwmac support for Loongson") +Signed-off-by: Hongliang Wang +Signed-off-by: Huacai Chen +Link: https://patch.msgid.link/20260203062901.2158236-1-chenhuacai@loongson.cn +Signed-off-by: Jakub Kicinski +Signed-off-by: Greg Kroah-Hartman +--- + drivers/net/ethernet/stmicro/stmmac/dwmac-loongson.c | 4 ++-- + 1 file changed, 2 insertions(+), 2 deletions(-) + +--- a/drivers/net/ethernet/stmicro/stmmac/dwmac-loongson.c ++++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-loongson.c +@@ -90,8 +90,8 @@ static void loongson_default_data(struct + /* Get bus_id, this can be overwritten later */ + plat->bus_id = pci_dev_id(pdev); + +- /* clk_csr_i = 20-35MHz & MDC = clk_csr_i/16 */ +- plat->clk_csr = STMMAC_CSR_20_35M; ++ /* clk_csr_i = 100-150MHz & MDC = clk_csr_i/62 */ ++ plat->clk_csr = STMMAC_CSR_100_150M; + plat->core_type = DWMAC_CORE_GMAC; + plat->force_sf_dma_mode = 1; + diff --git a/queue-6.18/series b/queue-6.18/series index e4a57d9608..aafe84a195 100644 --- a/queue-6.18/series +++ b/queue-6.18/series @@ -638,3 +638,4 @@ drivers-hv-vmbus-use-kthread-for-vmbus-interrupts-on-preempt_rt.patch io_uring-rsrc-clean-up-buffer-cloning-arg-validation.patch selftests-bpf-test-bpf_skb_check_mtu-bpf_mtu_chk_segs-when-transport_header-is-not-set.patch drm-amd-display-clear-hdmi-hpd-pending-work-only-if-it-is-enabled.patch +net-stmmac-dwmac-loongson-set-clk_csr_i-to-100-150mhz.patch