From: Ju-Zhe Zhong Date: Sun, 5 Feb 2023 01:50:31 +0000 (+0800) Subject: RISC-V: Add saturating Add && Sub vx constraint tests X-Git-Tag: basepoints/gcc-14~1379 X-Git-Url: http://git.ipfire.org/?a=commitdiff_plain;h=b2691c96efd74c25ba69d6cf14e9f0b3dc48053b;p=thirdparty%2Fgcc.git RISC-V: Add saturating Add && Sub vx constraint tests gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/base/binop_vx_constraint-100.c: New test. * gcc.target/riscv/rvv/base/binop_vx_constraint-101.c: New test. * gcc.target/riscv/rvv/base/binop_vx_constraint-102.c: New test. * gcc.target/riscv/rvv/base/binop_vx_constraint-103.c: New test. * gcc.target/riscv/rvv/base/binop_vx_constraint-104.c: New test. * gcc.target/riscv/rvv/base/binop_vx_constraint-105.c: New test. * gcc.target/riscv/rvv/base/binop_vx_constraint-106.c: New test. * gcc.target/riscv/rvv/base/binop_vx_constraint-107.c: New test. * gcc.target/riscv/rvv/base/binop_vx_constraint-108.c: New test. * gcc.target/riscv/rvv/base/binop_vx_constraint-109.c: New test. * gcc.target/riscv/rvv/base/binop_vx_constraint-110.c: New test. * gcc.target/riscv/rvv/base/binop_vx_constraint-111.c: New test. * gcc.target/riscv/rvv/base/binop_vx_constraint-112.c: New test. * gcc.target/riscv/rvv/base/binop_vx_constraint-113.c: New test. * gcc.target/riscv/rvv/base/binop_vx_constraint-114.c: New test. * gcc.target/riscv/rvv/base/binop_vx_constraint-115.c: New test. * gcc.target/riscv/rvv/base/binop_vx_constraint-116.c: New test. * gcc.target/riscv/rvv/base/binop_vx_constraint-117.c: New test. * gcc.target/riscv/rvv/base/binop_vx_constraint-118.c: New test. * gcc.target/riscv/rvv/base/binop_vx_constraint-119.c: New test. * gcc.target/riscv/rvv/base/binop_vx_constraint-97.c: New test. * gcc.target/riscv/rvv/base/binop_vx_constraint-98.c: New test. * gcc.target/riscv/rvv/base/binop_vx_constraint-99.c: New test. --- diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-100.c b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-100.c new file mode 100644 index 000000000000..667a7656ce1f --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-100.c @@ -0,0 +1,16 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32 -O3" } */ +#include "riscv_vector.h" + +void f (void * in, void *out, int64_t x, int n) +{ + vint64m1_t v = __riscv_vle64_v_i64m1 (in + 1, 4); + vint64m1_t v2 = __riscv_vle64_v_i64m1_tu (v, in + 2, 4); + vint64m1_t v3 = __riscv_vsadd_vx_i64m1 (v2, 0xAAAAAAAAAAAAAAAA, 4); + vint64m1_t v4 = __riscv_vsadd_vx_i64m1_tu (v3, v2, 0xAAAAAAAAAAAAAAAA, 4); + __riscv_vse64_v_i64m1 (out + 2, v4, 4); +} + +/* { dg-final { scan-assembler-times {vlse64\.v\s+v[0-9]+,\s*0\([a-x0-9]+\),\s*zero} 1 } } */ +/* { dg-final { scan-assembler-times {vsadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-not {vmv} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-101.c b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-101.c new file mode 100644 index 000000000000..eefdf455bca8 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-101.c @@ -0,0 +1,16 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32 -O3" } */ +#include "riscv_vector.h" + +void f (void * in, void *out, int64_t x, int n) +{ + vint64m1_t v = __riscv_vle64_v_i64m1 (in + 1, 4); + vint64m1_t v2 = __riscv_vle64_v_i64m1_tu (v, in + 2, 4); + vint64m1_t v3 = __riscv_vsadd_vx_i64m1 (v2, x, 4); + vint64m1_t v4 = __riscv_vsadd_vx_i64m1_tu (v3, v2, x, 4); + __riscv_vse64_v_i64m1 (out + 2, v4, 4); +} + +/* { dg-final { scan-assembler-times {vlse64\.v\s+v[0-9]+,\s*0\([a-x0-9]+\),\s*zero} 1 } } */ +/* { dg-final { scan-assembler-times {vsadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-not {vmv} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-102.c b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-102.c new file mode 100644 index 000000000000..4b24b971cbac --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-102.c @@ -0,0 +1,18 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32 -O3" } */ +#include "riscv_vector.h" + +void f (void * in, void *out, int32_t x, int n) +{ + for (int i = 0; i < n; i++) { + vint64m1_t v = __riscv_vle64_v_i64m1 (in + i + 1, 4); + vint64m1_t v2 = __riscv_vle64_v_i64m1_tu (v, in + i + 2, 4); + vint64m1_t v3 = __riscv_vsadd_vx_i64m1 (v2, x, 4); + vint64m1_t v4 = __riscv_vsadd_vx_i64m1_tu (v3, v2, x, 4); + __riscv_vse64_v_i64m1 (out + i + 2, v4, 4); + } +} + +/* { dg-final { scan-assembler-times {vlse64\.v\s+v[0-9]+,\s*0\([a-x0-9]+\),\s*zero\s+\.L[0-9]+\:\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-not {vmv} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-103.c b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-103.c new file mode 100644 index 000000000000..7ffedd5ceb91 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-103.c @@ -0,0 +1,123 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3" } */ +/* { dg-final { check-function-bodies "**" "" } } */ +#include "riscv_vector.h" + +/* +** f0: +** ... +** vsaddu\.vi\tv[0-9]+,\s*v[0-9]+,\s*-16 +** vsaddu\.vi\tv[0-9]+,\s*v[0-9]+,\s*-16 +** ... +** ret +*/ +void f0 (void * in, void *out, int64_t x, int n) +{ + vuint64m1_t v = __riscv_vle64_v_u64m1 (in + 1, 4); + vuint64m1_t v2 = __riscv_vle64_v_u64m1_tu (v, in + 2, 4); + vuint64m1_t v3 = __riscv_vsaddu_vx_u64m1 (v2, -16, 4); + vuint64m1_t v4 = __riscv_vsaddu_vx_u64m1 (v3, -16, 4); + __riscv_vse64_v_u64m1 (out + 2, v4, 4); +} + +/* +** f1: +** ... +** vsaddu\.vi\tv[0-9]+,\s*v[0-9]+,\s*15 +** vsaddu\.vi\tv[0-9]+,\s*v[0-9]+,\s*15 +** ... +** ret +*/ +void f1 (void * in, void *out, int64_t x, int n) +{ + vuint64m1_t v = __riscv_vle64_v_u64m1 (in + 1, 4); + vuint64m1_t v2 = __riscv_vle64_v_u64m1_tu (v, in + 2, 4); + vuint64m1_t v3 = __riscv_vsaddu_vx_u64m1 (v2, 15, 4); + vuint64m1_t v4 = __riscv_vsaddu_vx_u64m1 (v3, 15, 4); + __riscv_vse64_v_u64m1 (out + 2, v4, 4); +} + +/* +** f2: +** ... +** vsaddu\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+ +** vsaddu\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+ +** ... +** ret +*/ +void f2 (void * in, void *out, int64_t x, int n) +{ + vuint64m1_t v = __riscv_vle64_v_u64m1 (in + 1, 4); + vuint64m1_t v2 = __riscv_vle64_v_u64m1_tu (v, in + 2, 4); + vuint64m1_t v3 = __riscv_vsaddu_vx_u64m1 (v2, 16, 4); + vuint64m1_t v4 = __riscv_vsaddu_vx_u64m1 (v3, 16, 4); + __riscv_vse64_v_u64m1 (out + 2, v4, 4); +} + +/* +** f3: +** ... +** vsaddu\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+ +** vsaddu\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+ +** ... +** ret +*/ +void f3 (void * in, void *out, int64_t x, int n) +{ + vuint64m1_t v = __riscv_vle64_v_u64m1 (in + 1, 4); + vuint64m1_t v2 = __riscv_vle64_v_u64m1_tu (v, in + 2, 4); + vuint64m1_t v3 = __riscv_vsaddu_vx_u64m1 (v2, 0xAAAAAAAA, 4); + vuint64m1_t v4 = __riscv_vsaddu_vx_u64m1 (v3, 0xAAAAAAAA, 4); + __riscv_vse64_v_u64m1 (out + 2, v4, 4); +} + +/* +** f4: +** ... +** vsaddu\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+ +** vsaddu\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+ +** ... +** ret +*/ +void f4 (void * in, void *out, int64_t x, int n) +{ + vuint64m1_t v = __riscv_vle64_v_u64m1 (in + 1, 4); + vuint64m1_t v2 = __riscv_vle64_v_u64m1_tu (v, in + 2, 4); + vuint64m1_t v3 = __riscv_vsaddu_vx_u64m1 (v2, 0xAAAAAAAAAAAAAAAA, 4); + vuint64m1_t v4 = __riscv_vsaddu_vx_u64m1 (v3, 0xAAAAAAAAAAAAAAAA, 4); + __riscv_vse64_v_u64m1 (out + 2, v4, 4); +} + +/* +** f5: +** ... +** vsaddu\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+ +** vsaddu\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+ +** ... +** ret +*/ +void f5 (void * in, void *out, int64_t x, int n) +{ + vuint64m1_t v = __riscv_vle64_v_u64m1 (in + 1, 4); + vuint64m1_t v2 = __riscv_vle64_v_u64m1_tu (v, in + 2, 4); + vuint64m1_t v3 = __riscv_vsaddu_vx_u64m1 (v2, 0xAAAAAAAAAAAAAAAA, 4); + vuint64m1_t v4 = __riscv_vsaddu_vx_u64m1 (v3, 0xAAAAAAAAAAAAAAAA, 4); + __riscv_vse64_v_u64m1 (out + 2, v4, 4); +} + +/* +** f6: +** ... +** vsaddu\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+ +** vsaddu\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+ +** ... +** ret +*/ +void f6 (void * in, void *out, int64_t x, int n) +{ + vuint64m1_t v = __riscv_vle64_v_u64m1 (in + 1, 4); + vuint64m1_t v2 = __riscv_vle64_v_u64m1_tu (v, in + 2, 4); + vuint64m1_t v3 = __riscv_vsaddu_vx_u64m1 (v2, x, 4); + vuint64m1_t v4 = __riscv_vsaddu_vx_u64m1 (v3, x, 4); + __riscv_vse64_v_u64m1 (out + 2, v4, 4); +} diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-104.c b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-104.c new file mode 100644 index 000000000000..612213a60364 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-104.c @@ -0,0 +1,72 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32 -O3" } */ +/* { dg-final { check-function-bodies "**" "" } } */ +#include "riscv_vector.h" + +/* +** f0: +** ... +** vsaddu\.vi\tv[0-9]+,\s*v[0-9]+,\s*-16 +** vsaddu\.vi\tv[0-9]+,\s*v[0-9]+,\s*-16 +** ... +** ret +*/ +void f0 (void * in, void *out, int64_t x, int n) +{ + vuint64m1_t v = __riscv_vle64_v_u64m1 (in + 1, 4); + vuint64m1_t v2 = __riscv_vle64_v_u64m1_tu (v, in + 2, 4); + vuint64m1_t v3 = __riscv_vsaddu_vx_u64m1 (v2, -16, 4); + vuint64m1_t v4 = __riscv_vsaddu_vx_u64m1 (v3, -16, 4); + __riscv_vse64_v_u64m1 (out + 2, v4, 4); +} + +/* +** f1: +** ... +** vsaddu\.vi\tv[0-9]+,\s*v[0-9]+,\s*15 +** vsaddu\.vi\tv[0-9]+,\s*v[0-9]+,\s*15 +** ... +** ret +*/ +void f1 (void * in, void *out, int64_t x, int n) +{ + vuint64m1_t v = __riscv_vle64_v_u64m1 (in + 1, 4); + vuint64m1_t v2 = __riscv_vle64_v_u64m1_tu (v, in + 2, 4); + vuint64m1_t v3 = __riscv_vsaddu_vx_u64m1 (v2, 15, 4); + vuint64m1_t v4 = __riscv_vsaddu_vx_u64m1 (v3, 15, 4); + __riscv_vse64_v_u64m1 (out + 2, v4, 4); +} + +/* +** f2: +** ... +** vsaddu\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+ +** vsaddu\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+ +** ... +** ret +*/ +void f2 (void * in, void *out, int64_t x, int n) +{ + vuint64m1_t v = __riscv_vle64_v_u64m1 (in + 1, 4); + vuint64m1_t v2 = __riscv_vle64_v_u64m1_tu (v, in + 2, 4); + vuint64m1_t v3 = __riscv_vsaddu_vx_u64m1 (v2, 16, 4); + vuint64m1_t v4 = __riscv_vsaddu_vx_u64m1 (v3, 16, 4); + __riscv_vse64_v_u64m1 (out + 2, v4, 4); +} + +/* +** f3: +** ... +** vsaddu\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+ +** vsaddu\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+ +** ... +** ret +*/ +void f3 (void * in, void *out, int64_t x, int n) +{ + vuint64m1_t v = __riscv_vle64_v_u64m1 (in + 1, 4); + vuint64m1_t v2 = __riscv_vle64_v_u64m1_tu (v, in + 2, 4); + vuint64m1_t v3 = __riscv_vsaddu_vx_u64m1 (v2, 0xAAAAAAA, 4); + vuint64m1_t v4 = __riscv_vsaddu_vx_u64m1 (v3, 0xAAAAAAA, 4); + __riscv_vse64_v_u64m1 (out + 2, v4, 4); +} diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-105.c b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-105.c new file mode 100644 index 000000000000..86825c088b1f --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-105.c @@ -0,0 +1,16 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32 -O3" } */ +#include "riscv_vector.h" + +void f (void * in, void *out, int64_t x, int n) +{ + vuint64m1_t v = __riscv_vle64_v_u64m1 (in + 1, 4); + vuint64m1_t v2 = __riscv_vle64_v_u64m1_tu (v, in + 2, 4); + vuint64m1_t v3 = __riscv_vsaddu_vx_u64m1 (v2, 0xAAAAAAAA, 4); + vuint64m1_t v4 = __riscv_vsaddu_vx_u64m1_tu (v3, v2, 0xAAAAAAAA, 4); + __riscv_vse64_v_u64m1 (out + 2, v4, 4); +} + +/* { dg-final { scan-assembler-times {vlse64\.v\s+v[0-9]+,\s*0\([a-x0-9]+\),\s*zero} 1 } } */ +/* { dg-final { scan-assembler-times {vsaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-not {vmv} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-106.c b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-106.c new file mode 100644 index 000000000000..94bff68ba5ea --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-106.c @@ -0,0 +1,16 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32 -O3" } */ +#include "riscv_vector.h" + +void f (void * in, void *out, int64_t x, int n) +{ + vuint64m1_t v = __riscv_vle64_v_u64m1 (in + 1, 4); + vuint64m1_t v2 = __riscv_vle64_v_u64m1_tu (v, in + 2, 4); + vuint64m1_t v3 = __riscv_vsaddu_vx_u64m1 (v2, 0xAAAAAAAAAAAAAAAA, 4); + vuint64m1_t v4 = __riscv_vsaddu_vx_u64m1_tu (v3, v2, 0xAAAAAAAAAAAAAAAA, 4); + __riscv_vse64_v_u64m1 (out + 2, v4, 4); +} + +/* { dg-final { scan-assembler-times {vlse64\.v\s+v[0-9]+,\s*0\([a-x0-9]+\),\s*zero} 1 } } */ +/* { dg-final { scan-assembler-times {vsaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-not {vmv} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-107.c b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-107.c new file mode 100644 index 000000000000..a3d08de06c47 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-107.c @@ -0,0 +1,16 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32 -O3" } */ +#include "riscv_vector.h" + +void f (void * in, void *out, int64_t x, int n) +{ + vuint64m1_t v = __riscv_vle64_v_u64m1 (in + 1, 4); + vuint64m1_t v2 = __riscv_vle64_v_u64m1_tu (v, in + 2, 4); + vuint64m1_t v3 = __riscv_vsaddu_vx_u64m1 (v2, x, 4); + vuint64m1_t v4 = __riscv_vsaddu_vx_u64m1_tu (v3, v2, x, 4); + __riscv_vse64_v_u64m1 (out + 2, v4, 4); +} + +/* { dg-final { scan-assembler-times {vlse64\.v\s+v[0-9]+,\s*0\([a-x0-9]+\),\s*zero} 1 } } */ +/* { dg-final { scan-assembler-times {vsaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-not {vmv} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-108.c b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-108.c new file mode 100644 index 000000000000..99acc51b4ffb --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-108.c @@ -0,0 +1,18 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32 -O3" } */ +#include "riscv_vector.h" + +void f (void * in, void *out, int32_t x, int n) +{ + for (int i = 0; i < n; i++) { + vuint64m1_t v = __riscv_vle64_v_u64m1 (in + i + 1, 4); + vuint64m1_t v2 = __riscv_vle64_v_u64m1_tu (v, in + i + 2, 4); + vuint64m1_t v3 = __riscv_vsaddu_vx_u64m1 (v2, x, 4); + vuint64m1_t v4 = __riscv_vsaddu_vx_u64m1_tu (v3, v2, x, 4); + __riscv_vse64_v_u64m1 (out + i + 2, v4, 4); + } +} + +/* { dg-final { scan-assembler-times {vlse64\.v\s+v[0-9]+,\s*0\([a-x0-9]+\),\s*zero\s+\.L[0-9]+\:\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-not {vmv} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-109.c b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-109.c new file mode 100644 index 000000000000..9127b869f535 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-109.c @@ -0,0 +1,123 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3" } */ +/* { dg-final { check-function-bodies "**" "" } } */ +#include "riscv_vector.h" + +/* +** f0: +** ... +** vsadd\.vi\tv[0-9]+,\s*v[0-9]+,\s*15 +** vsadd\.vi\tv[0-9]+,\s*v[0-9]+,\s*15 +** ... +** ret +*/ +void f0 (void * in, void *out, int64_t x, int n) +{ + vint64m1_t v = __riscv_vle64_v_i64m1 (in + 1, 4); + vint64m1_t v2 = __riscv_vle64_v_i64m1_tu (v, in + 2, 4); + vint64m1_t v3 = __riscv_vssub_vx_i64m1 (v2, -15, 4); + vint64m1_t v4 = __riscv_vssub_vx_i64m1 (v3, -15, 4); + __riscv_vse64_v_i64m1 (out + 2, v4, 4); +} + +/* +** f1: +** ... +** vsadd\.vi\tv[0-9]+,\s*v[0-9]+,\s*-16 +** vsadd\.vi\tv[0-9]+,\s*v[0-9]+,\s*-16 +** ... +** ret +*/ +void f1 (void * in, void *out, int64_t x, int n) +{ + vint64m1_t v = __riscv_vle64_v_i64m1 (in + 1, 4); + vint64m1_t v2 = __riscv_vle64_v_i64m1_tu (v, in + 2, 4); + vint64m1_t v3 = __riscv_vssub_vx_i64m1 (v2, 16, 4); + vint64m1_t v4 = __riscv_vssub_vx_i64m1 (v3, 16, 4); + __riscv_vse64_v_i64m1 (out + 2, v4, 4); +} + +/* +** f2: +** ... +** vssub\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+ +** vssub\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+ +** ... +** ret +*/ +void f2 (void * in, void *out, int64_t x, int n) +{ + vint64m1_t v = __riscv_vle64_v_i64m1 (in + 1, 4); + vint64m1_t v2 = __riscv_vle64_v_i64m1_tu (v, in + 2, 4); + vint64m1_t v3 = __riscv_vssub_vx_i64m1 (v2, 17, 4); + vint64m1_t v4 = __riscv_vssub_vx_i64m1 (v3, 17, 4); + __riscv_vse64_v_i64m1 (out + 2, v4, 4); +} + +/* +** f3: +** ... +** vssub\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+ +** vssub\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+ +** ... +** ret +*/ +void f3 (void * in, void *out, int64_t x, int n) +{ + vint64m1_t v = __riscv_vle64_v_i64m1 (in + 1, 4); + vint64m1_t v2 = __riscv_vle64_v_i64m1_tu (v, in + 2, 4); + vint64m1_t v3 = __riscv_vssub_vx_i64m1 (v2, 0xAAAAAAAA, 4); + vint64m1_t v4 = __riscv_vssub_vx_i64m1 (v3, 0xAAAAAAAA, 4); + __riscv_vse64_v_i64m1 (out + 2, v4, 4); +} + +/* +** f4: +** ... +** vssub\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+ +** vssub\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+ +** ... +** ret +*/ +void f4 (void * in, void *out, int64_t x, int n) +{ + vint64m1_t v = __riscv_vle64_v_i64m1 (in + 1, 4); + vint64m1_t v2 = __riscv_vle64_v_i64m1_tu (v, in + 2, 4); + vint64m1_t v3 = __riscv_vssub_vx_i64m1 (v2, 0xAAAAAAAAAAAAAAAA, 4); + vint64m1_t v4 = __riscv_vssub_vx_i64m1 (v3, 0xAAAAAAAAAAAAAAAA, 4); + __riscv_vse64_v_i64m1 (out + 2, v4, 4); +} + +/* +** f5: +** ... +** vssub\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+ +** vssub\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+ +** ... +** ret +*/ +void f5 (void * in, void *out, int64_t x, int n) +{ + vint64m1_t v = __riscv_vle64_v_i64m1 (in + 1, 4); + vint64m1_t v2 = __riscv_vle64_v_i64m1_tu (v, in + 2, 4); + vint64m1_t v3 = __riscv_vssub_vx_i64m1 (v2, 0xAAAAAAAAAAAAAAAA, 4); + vint64m1_t v4 = __riscv_vssub_vx_i64m1 (v3, 0xAAAAAAAAAAAAAAAA, 4); + __riscv_vse64_v_i64m1 (out + 2, v4, 4); +} + +/* +** f6: +** ... +** vssub\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+ +** vssub\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+ +** ... +** ret +*/ +void f6 (void * in, void *out, int64_t x, int n) +{ + vint64m1_t v = __riscv_vle64_v_i64m1 (in + 1, 4); + vint64m1_t v2 = __riscv_vle64_v_i64m1_tu (v, in + 2, 4); + vint64m1_t v3 = __riscv_vssub_vx_i64m1 (v2, x, 4); + vint64m1_t v4 = __riscv_vssub_vx_i64m1 (v3, x, 4); + __riscv_vse64_v_i64m1 (out + 2, v4, 4); +} diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-110.c b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-110.c new file mode 100644 index 000000000000..d70789e1810b --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-110.c @@ -0,0 +1,72 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32 -O3" } */ +/* { dg-final { check-function-bodies "**" "" } } */ +#include "riscv_vector.h" + +/* +** f0: +** ... +** vsadd\.vi\tv[0-9]+,\s*v[0-9]+,\s*15 +** vsadd\.vi\tv[0-9]+,\s*v[0-9]+,\s*15 +** ... +** ret +*/ +void f0 (void * in, void *out, int64_t x, int n) +{ + vint64m1_t v = __riscv_vle64_v_i64m1 (in + 1, 4); + vint64m1_t v2 = __riscv_vle64_v_i64m1_tu (v, in + 2, 4); + vint64m1_t v3 = __riscv_vssub_vx_i64m1 (v2, -15, 4); + vint64m1_t v4 = __riscv_vssub_vx_i64m1 (v3, -15, 4); + __riscv_vse64_v_i64m1 (out + 2, v4, 4); +} + +/* +** f1: +** ... +** vsadd\.vi\tv[0-9]+,\s*v[0-9]+,\s*-16 +** vsadd\.vi\tv[0-9]+,\s*v[0-9]+,\s*-16 +** ... +** ret +*/ +void f1 (void * in, void *out, int64_t x, int n) +{ + vint64m1_t v = __riscv_vle64_v_i64m1 (in + 1, 4); + vint64m1_t v2 = __riscv_vle64_v_i64m1_tu (v, in + 2, 4); + vint64m1_t v3 = __riscv_vssub_vx_i64m1 (v2, 16, 4); + vint64m1_t v4 = __riscv_vssub_vx_i64m1 (v3, 16, 4); + __riscv_vse64_v_i64m1 (out + 2, v4, 4); +} + +/* +** f2: +** ... +** vssub\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+ +** vssub\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+ +** ... +** ret +*/ +void f2 (void * in, void *out, int64_t x, int n) +{ + vint64m1_t v = __riscv_vle64_v_i64m1 (in + 1, 4); + vint64m1_t v2 = __riscv_vle64_v_i64m1_tu (v, in + 2, 4); + vint64m1_t v3 = __riscv_vssub_vx_i64m1 (v2, 17, 4); + vint64m1_t v4 = __riscv_vssub_vx_i64m1 (v3, 17, 4); + __riscv_vse64_v_i64m1 (out + 2, v4, 4); +} + +/* +** f3: +** ... +** vssub\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+ +** vssub\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+ +** ... +** ret +*/ +void f3 (void * in, void *out, int64_t x, int n) +{ + vint64m1_t v = __riscv_vle64_v_i64m1 (in + 1, 4); + vint64m1_t v2 = __riscv_vle64_v_i64m1_tu (v, in + 2, 4); + vint64m1_t v3 = __riscv_vssub_vx_i64m1 (v2, 0xAAAAAAA, 4); + vint64m1_t v4 = __riscv_vssub_vx_i64m1 (v3, 0xAAAAAAA, 4); + __riscv_vse64_v_i64m1 (out + 2, v4, 4); +} diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-111.c b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-111.c new file mode 100644 index 000000000000..e02b21554a87 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-111.c @@ -0,0 +1,16 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32 -O3" } */ +#include "riscv_vector.h" + +void f (void * in, void *out, int64_t x, int n) +{ + vint64m1_t v = __riscv_vle64_v_i64m1 (in + 1, 4); + vint64m1_t v2 = __riscv_vle64_v_i64m1_tu (v, in + 2, 4); + vint64m1_t v3 = __riscv_vssub_vx_i64m1 (v2, 0xAAAAAAAA, 4); + vint64m1_t v4 = __riscv_vssub_vx_i64m1_tu (v3, v2, 0xAAAAAAAA, 4); + __riscv_vse64_v_i64m1 (out + 2, v4, 4); +} + +/* { dg-final { scan-assembler-times {vlse64\.v\s+v[0-9]+,\s*0\([a-x0-9]+\),\s*zero} 1 } } */ +/* { dg-final { scan-assembler-times {vssub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-not {vmv} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-112.c b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-112.c new file mode 100644 index 000000000000..8cd9c4d09ba0 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-112.c @@ -0,0 +1,16 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32 -O3" } */ +#include "riscv_vector.h" + +void f (void * in, void *out, int64_t x, int n) +{ + vint64m1_t v = __riscv_vle64_v_i64m1 (in + 1, 4); + vint64m1_t v2 = __riscv_vle64_v_i64m1_tu (v, in + 2, 4); + vint64m1_t v3 = __riscv_vssub_vx_i64m1 (v2, 0xAAAAAAAAAAAAAAAA, 4); + vint64m1_t v4 = __riscv_vssub_vx_i64m1_tu (v3, v2, 0xAAAAAAAAAAAAAAAA, 4); + __riscv_vse64_v_i64m1 (out + 2, v4, 4); +} + +/* { dg-final { scan-assembler-times {vlse64\.v\s+v[0-9]+,\s*0\([a-x0-9]+\),\s*zero} 1 } } */ +/* { dg-final { scan-assembler-times {vssub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-not {vmv} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-113.c b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-113.c new file mode 100644 index 000000000000..6090a1da69d9 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-113.c @@ -0,0 +1,16 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32 -O3" } */ +#include "riscv_vector.h" + +void f (void * in, void *out, int64_t x, int n) +{ + vint64m1_t v = __riscv_vle64_v_i64m1 (in + 1, 4); + vint64m1_t v2 = __riscv_vle64_v_i64m1_tu (v, in + 2, 4); + vint64m1_t v3 = __riscv_vssub_vx_i64m1 (v2, x, 4); + vint64m1_t v4 = __riscv_vssub_vx_i64m1_tu (v3, v2, x, 4); + __riscv_vse64_v_i64m1 (out + 2, v4, 4); +} + +/* { dg-final { scan-assembler-times {vlse64\.v\s+v[0-9]+,\s*0\([a-x0-9]+\),\s*zero} 1 } } */ +/* { dg-final { scan-assembler-times {vssub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-not {vmv} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-114.c b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-114.c new file mode 100644 index 000000000000..d595c4465030 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-114.c @@ -0,0 +1,18 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32 -O3" } */ +#include "riscv_vector.h" + +void f (void * in, void *out, int32_t x, int n) +{ + for (int i = 0; i < n; i++) { + vint64m1_t v = __riscv_vle64_v_i64m1 (in + i + 1, 4); + vint64m1_t v2 = __riscv_vle64_v_i64m1_tu (v, in + i + 2, 4); + vint64m1_t v3 = __riscv_vssub_vx_i64m1 (v2, x, 4); + vint64m1_t v4 = __riscv_vssub_vx_i64m1_tu (v3, v2, x, 4); + __riscv_vse64_v_i64m1 (out + i + 2, v4, 4); + } +} + +/* { dg-final { scan-assembler-times {vlse64\.v\s+v[0-9]+,\s*0\([a-x0-9]+\),\s*zero\s+\.L[0-9]+\:\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vssub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-not {vmv} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-115.c b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-115.c new file mode 100644 index 000000000000..9722f5e61188 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-115.c @@ -0,0 +1,72 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32 -O3" } */ +/* { dg-final { check-function-bodies "**" "" } } */ +#include "riscv_vector.h" + +/* +** f0: +** ... +** vssubu\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+ +** vssubu\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+ +** ... +** ret +*/ +void f0 (void * in, void *out, uint64_t x, int n) +{ + vuint64m1_t v = __riscv_vle64_v_u64m1 (in + 1, 4); + vuint64m1_t v2 = __riscv_vle64_v_u64m1_tu (v, in + 2, 4); + vuint64m1_t v3 = __riscv_vssubu_vx_u64m1 (v2, -16, 4); + vuint64m1_t v4 = __riscv_vssubu_vx_u64m1 (v3, -16, 4); + __riscv_vse64_v_u64m1 (out + 2, v4, 4); +} + +/* +** f1: +** ... +** vssubu\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+ +** vssubu\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+ +** ... +** ret +*/ +void f1 (void * in, void *out, uint64_t x, int n) +{ + vuint64m1_t v = __riscv_vle64_v_u64m1 (in + 1, 4); + vuint64m1_t v2 = __riscv_vle64_v_u64m1_tu (v, in + 2, 4); + vuint64m1_t v3 = __riscv_vssubu_vx_u64m1 (v2, 15, 4); + vuint64m1_t v4 = __riscv_vssubu_vx_u64m1 (v3, 15, 4); + __riscv_vse64_v_u64m1 (out + 2, v4, 4); +} + +/* +** f2: +** ... +** vssubu\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+ +** vssubu\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+ +** ... +** ret +*/ +void f2 (void * in, void *out, uint64_t x, int n) +{ + vuint64m1_t v = __riscv_vle64_v_u64m1 (in + 1, 4); + vuint64m1_t v2 = __riscv_vle64_v_u64m1_tu (v, in + 2, 4); + vuint64m1_t v3 = __riscv_vssubu_vx_u64m1 (v2, 16, 4); + vuint64m1_t v4 = __riscv_vssubu_vx_u64m1 (v3, 16, 4); + __riscv_vse64_v_u64m1 (out + 2, v4, 4); +} + +/* +** f3: +** ... +** vssubu\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+ +** vssubu\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+ +** ... +** ret +*/ +void f3 (void * in, void *out, uint64_t x, int n) +{ + vuint64m1_t v = __riscv_vle64_v_u64m1 (in + 1, 4); + vuint64m1_t v2 = __riscv_vle64_v_u64m1_tu (v, in + 2, 4); + vuint64m1_t v3 = __riscv_vssubu_vx_u64m1 (v2, 0xAAAAAAA, 4); + vuint64m1_t v4 = __riscv_vssubu_vx_u64m1 (v3, 0xAAAAAAA, 4); + __riscv_vse64_v_u64m1 (out + 2, v4, 4); +} diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-116.c b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-116.c new file mode 100644 index 000000000000..066365dc744f --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-116.c @@ -0,0 +1,16 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32 -O3" } */ +#include "riscv_vector.h" + +void f (void * in, void *out, uint64_t x, int n) +{ + vuint64m1_t v = __riscv_vle64_v_u64m1 (in + 1, 4); + vuint64m1_t v2 = __riscv_vle64_v_u64m1_tu (v, in + 2, 4); + vuint64m1_t v3 = __riscv_vssubu_vx_u64m1 (v2, 0xAAAAAAAA, 4); + vuint64m1_t v4 = __riscv_vssubu_vx_u64m1_tu (v3, v2, 0xAAAAAAAA, 4); + __riscv_vse64_v_u64m1 (out + 2, v4, 4); +} + +/* { dg-final { scan-assembler-times {vlse64\.v\s+v[0-9]+,\s*0\([a-x0-9]+\),\s*zero} 1 } } */ +/* { dg-final { scan-assembler-times {vssubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-not {vmv} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-117.c b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-117.c new file mode 100644 index 000000000000..bfc6773f198d --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-117.c @@ -0,0 +1,16 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32 -O3" } */ +#include "riscv_vector.h" + +void f (void * in, void *out, uint64_t x, int n) +{ + vuint64m1_t v = __riscv_vle64_v_u64m1 (in + 1, 4); + vuint64m1_t v2 = __riscv_vle64_v_u64m1_tu (v, in + 2, 4); + vuint64m1_t v3 = __riscv_vssubu_vx_u64m1 (v2, 0xAAAAAAAAAAAAAAAA, 4); + vuint64m1_t v4 = __riscv_vssubu_vx_u64m1_tu (v3, v2, 0xAAAAAAAAAAAAAAAA, 4); + __riscv_vse64_v_u64m1 (out + 2, v4, 4); +} + +/* { dg-final { scan-assembler-times {vlse64\.v\s+v[0-9]+,\s*0\([a-x0-9]+\),\s*zero} 1 } } */ +/* { dg-final { scan-assembler-times {vssubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-not {vmv} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-118.c b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-118.c new file mode 100644 index 000000000000..05a7a1d9e65a --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-118.c @@ -0,0 +1,16 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32 -O3" } */ +#include "riscv_vector.h" + +void f (void * in, void *out, uint64_t x, int n) +{ + vuint64m1_t v = __riscv_vle64_v_u64m1 (in + 1, 4); + vuint64m1_t v2 = __riscv_vle64_v_u64m1_tu (v, in + 2, 4); + vuint64m1_t v3 = __riscv_vssubu_vx_u64m1 (v2, x, 4); + vuint64m1_t v4 = __riscv_vssubu_vx_u64m1_tu (v3, v2, x, 4); + __riscv_vse64_v_u64m1 (out + 2, v4, 4); +} + +/* { dg-final { scan-assembler-times {vlse64\.v\s+v[0-9]+,\s*0\([a-x0-9]+\),\s*zero} 1 } } */ +/* { dg-final { scan-assembler-times {vssubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-not {vmv} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-119.c b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-119.c new file mode 100644 index 000000000000..0b51175f66ca --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-119.c @@ -0,0 +1,18 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32 -O3" } */ +#include "riscv_vector.h" + +void f (void * in, void *out, uint64_t x, int n) +{ + for (int i = 0; i < n; i++) { + vuint64m1_t v = __riscv_vle64_v_u64m1 (in + i + 1, 4); + vuint64m1_t v2 = __riscv_vle64_v_u64m1_tu (v, in + i + 2, 4); + vuint64m1_t v3 = __riscv_vssubu_vx_u64m1 (v2, x, 4); + vuint64m1_t v4 = __riscv_vssubu_vx_u64m1_tu (v3, v2, x, 4); + __riscv_vse64_v_u64m1 (out + i + 2, v4, 4); + } +} + +/* { dg-final { scan-assembler-times {vlse64\.v\s+v[0-9]+,\s*0\([a-x0-9]+\),\s*zero\s+\.L[0-9]+\:\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vssubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-not {vmv} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-97.c b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-97.c new file mode 100644 index 000000000000..d1283d89a934 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-97.c @@ -0,0 +1,123 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3" } */ +/* { dg-final { check-function-bodies "**" "" } } */ +#include "riscv_vector.h" + +/* +** f0: +** ... +** vsadd\.vi\tv[0-9]+,\s*v[0-9]+,\s*-16 +** vsadd\.vi\tv[0-9]+,\s*v[0-9]+,\s*-16 +** ... +** ret +*/ +void f0 (void * in, void *out, int64_t x, int n) +{ + vint64m1_t v = __riscv_vle64_v_i64m1 (in + 1, 4); + vint64m1_t v2 = __riscv_vle64_v_i64m1_tu (v, in + 2, 4); + vint64m1_t v3 = __riscv_vsadd_vx_i64m1 (v2, -16, 4); + vint64m1_t v4 = __riscv_vsadd_vx_i64m1 (v3, -16, 4); + __riscv_vse64_v_i64m1 (out + 2, v4, 4); +} + +/* +** f1: +** ... +** vsadd\.vi\tv[0-9]+,\s*v[0-9]+,\s*15 +** vsadd\.vi\tv[0-9]+,\s*v[0-9]+,\s*15 +** ... +** ret +*/ +void f1 (void * in, void *out, int64_t x, int n) +{ + vint64m1_t v = __riscv_vle64_v_i64m1 (in + 1, 4); + vint64m1_t v2 = __riscv_vle64_v_i64m1_tu (v, in + 2, 4); + vint64m1_t v3 = __riscv_vsadd_vx_i64m1 (v2, 15, 4); + vint64m1_t v4 = __riscv_vsadd_vx_i64m1 (v3, 15, 4); + __riscv_vse64_v_i64m1 (out + 2, v4, 4); +} + +/* +** f2: +** ... +** vsadd\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+ +** vsadd\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+ +** ... +** ret +*/ +void f2 (void * in, void *out, int64_t x, int n) +{ + vint64m1_t v = __riscv_vle64_v_i64m1 (in + 1, 4); + vint64m1_t v2 = __riscv_vle64_v_i64m1_tu (v, in + 2, 4); + vint64m1_t v3 = __riscv_vsadd_vx_i64m1 (v2, 16, 4); + vint64m1_t v4 = __riscv_vsadd_vx_i64m1 (v3, 16, 4); + __riscv_vse64_v_i64m1 (out + 2, v4, 4); +} + +/* +** f3: +** ... +** vsadd\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+ +** vsadd\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+ +** ... +** ret +*/ +void f3 (void * in, void *out, int64_t x, int n) +{ + vint64m1_t v = __riscv_vle64_v_i64m1 (in + 1, 4); + vint64m1_t v2 = __riscv_vle64_v_i64m1_tu (v, in + 2, 4); + vint64m1_t v3 = __riscv_vsadd_vx_i64m1 (v2, 0xAAAAAAAA, 4); + vint64m1_t v4 = __riscv_vsadd_vx_i64m1 (v3, 0xAAAAAAAA, 4); + __riscv_vse64_v_i64m1 (out + 2, v4, 4); +} + +/* +** f4: +** ... +** vsadd\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+ +** vsadd\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+ +** ... +** ret +*/ +void f4 (void * in, void *out, int64_t x, int n) +{ + vint64m1_t v = __riscv_vle64_v_i64m1 (in + 1, 4); + vint64m1_t v2 = __riscv_vle64_v_i64m1_tu (v, in + 2, 4); + vint64m1_t v3 = __riscv_vsadd_vx_i64m1 (v2, 0xAAAAAAAAAAAAAAAA, 4); + vint64m1_t v4 = __riscv_vsadd_vx_i64m1 (v3, 0xAAAAAAAAAAAAAAAA, 4); + __riscv_vse64_v_i64m1 (out + 2, v4, 4); +} + +/* +** f5: +** ... +** vsadd\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+ +** vsadd\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+ +** ... +** ret +*/ +void f5 (void * in, void *out, int64_t x, int n) +{ + vint64m1_t v = __riscv_vle64_v_i64m1 (in + 1, 4); + vint64m1_t v2 = __riscv_vle64_v_i64m1_tu (v, in + 2, 4); + vint64m1_t v3 = __riscv_vsadd_vx_i64m1 (v2, 0xAAAAAAAAAAAAAAAA, 4); + vint64m1_t v4 = __riscv_vsadd_vx_i64m1 (v3, 0xAAAAAAAAAAAAAAAA, 4); + __riscv_vse64_v_i64m1 (out + 2, v4, 4); +} + +/* +** f6: +** ... +** vsadd\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+ +** vsadd\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+ +** ... +** ret +*/ +void f6 (void * in, void *out, int64_t x, int n) +{ + vint64m1_t v = __riscv_vle64_v_i64m1 (in + 1, 4); + vint64m1_t v2 = __riscv_vle64_v_i64m1_tu (v, in + 2, 4); + vint64m1_t v3 = __riscv_vsadd_vx_i64m1 (v2, x, 4); + vint64m1_t v4 = __riscv_vsadd_vx_i64m1 (v3, x, 4); + __riscv_vse64_v_i64m1 (out + 2, v4, 4); +} diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-98.c b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-98.c new file mode 100644 index 000000000000..ed7477b3ca8d --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-98.c @@ -0,0 +1,72 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32 -O3" } */ +/* { dg-final { check-function-bodies "**" "" } } */ +#include "riscv_vector.h" + +/* +** f0: +** ... +** vsadd\.vi\tv[0-9]+,\s*v[0-9]+,\s*-16 +** vsadd\.vi\tv[0-9]+,\s*v[0-9]+,\s*-16 +** ... +** ret +*/ +void f0 (void * in, void *out, int64_t x, int n) +{ + vint64m1_t v = __riscv_vle64_v_i64m1 (in + 1, 4); + vint64m1_t v2 = __riscv_vle64_v_i64m1_tu (v, in + 2, 4); + vint64m1_t v3 = __riscv_vsadd_vx_i64m1 (v2, -16, 4); + vint64m1_t v4 = __riscv_vsadd_vx_i64m1 (v3, -16, 4); + __riscv_vse64_v_i64m1 (out + 2, v4, 4); +} + +/* +** f1: +** ... +** vsadd\.vi\tv[0-9]+,\s*v[0-9]+,\s*15 +** vsadd\.vi\tv[0-9]+,\s*v[0-9]+,\s*15 +** ... +** ret +*/ +void f1 (void * in, void *out, int64_t x, int n) +{ + vint64m1_t v = __riscv_vle64_v_i64m1 (in + 1, 4); + vint64m1_t v2 = __riscv_vle64_v_i64m1_tu (v, in + 2, 4); + vint64m1_t v3 = __riscv_vsadd_vx_i64m1 (v2, 15, 4); + vint64m1_t v4 = __riscv_vsadd_vx_i64m1 (v3, 15, 4); + __riscv_vse64_v_i64m1 (out + 2, v4, 4); +} + +/* +** f2: +** ... +** vsadd\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+ +** vsadd\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+ +** ... +** ret +*/ +void f2 (void * in, void *out, int64_t x, int n) +{ + vint64m1_t v = __riscv_vle64_v_i64m1 (in + 1, 4); + vint64m1_t v2 = __riscv_vle64_v_i64m1_tu (v, in + 2, 4); + vint64m1_t v3 = __riscv_vsadd_vx_i64m1 (v2, 16, 4); + vint64m1_t v4 = __riscv_vsadd_vx_i64m1 (v3, 16, 4); + __riscv_vse64_v_i64m1 (out + 2, v4, 4); +} + +/* +** f3: +** ... +** vsadd\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+ +** vsadd\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+ +** ... +** ret +*/ +void f3 (void * in, void *out, int64_t x, int n) +{ + vint64m1_t v = __riscv_vle64_v_i64m1 (in + 1, 4); + vint64m1_t v2 = __riscv_vle64_v_i64m1_tu (v, in + 2, 4); + vint64m1_t v3 = __riscv_vsadd_vx_i64m1 (v2, 0xAAAAAAA, 4); + vint64m1_t v4 = __riscv_vsadd_vx_i64m1 (v3, 0xAAAAAAA, 4); + __riscv_vse64_v_i64m1 (out + 2, v4, 4); +} diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-99.c b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-99.c new file mode 100644 index 000000000000..5a4f58bfc1a7 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-99.c @@ -0,0 +1,16 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32 -O3" } */ +#include "riscv_vector.h" + +void f (void * in, void *out, int64_t x, int n) +{ + vint64m1_t v = __riscv_vle64_v_i64m1 (in + 1, 4); + vint64m1_t v2 = __riscv_vle64_v_i64m1_tu (v, in + 2, 4); + vint64m1_t v3 = __riscv_vadd_vx_i64m1 (v2, 0xAAAAAAAA, 4); + vint64m1_t v4 = __riscv_vadd_vx_i64m1_tu (v3, v2, 0xAAAAAAAA, 4); + __riscv_vse64_v_i64m1 (out + 2, v4, 4); +} + +/* { dg-final { scan-assembler-times {vlse64\.v\s+v[0-9]+,\s*0\([a-x0-9]+\),\s*zero} 1 } } */ +/* { dg-final { scan-assembler-times {vadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-not {vmv} } } */